On Mon, Sep 8, 2014 at 11:01 PM, Ricardo Nobre <[email protected]> wrote: > Other question that maybe is not be that smart... but I'm a little new to > this hardware simulation stuff. > > Can I also use fusesoc (with some adaptation) to work with MiSoC? > https://github.com/m-labs/misoc >
migen/misoc and fusesoc/orpsoc-cores does in some areas try to solve the same problem, so using them together is perhaps not the right way forward. Adapting the verilator testbench from the orpsoc-cores testbenches to misoc is probably a more reasonable thing to do. > I would also like to be able to use verilator to simulate the LatticeMico32 > softcore. > Sebastien might have some insight on how to best get a misoc based verilator simulation running. I also think Jose and his associates did some tests and comparisons on both OpenRISC (mor1kx/or1200) and LatticeMico32. I know that he ran verilator on the operisc side at least, and I wouldn't be surprised if they did the same with LM32. I added Sebastien and Jose to CC to make them (more) aware of this conversation. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
