On Tue, Sep 9, 2014 at 3:14 PM, Ricardo Nobre <[email protected]> wrote: > Fortunatelly I bought a DE0-NANO some time ago, wich to my luck is > compatible with MiSoC. > I will test the LM32 there ;-) > > I'm a little bit confused about some stuff. > What is the number of pipeline stages of the ESPRESSO, PRONTO ESPRESSO and > CAPPUCCINO? >
cappuccino has a 6 stage pipeline (addr, fetch, decode, execute, mem, wb) I'm pretty sure (Julius should be certain) that (pronto)espresso has a 2 stage pipeline (fetch, execute) > In some online post people say the ESPRESSO and PRONTO EXPRESSO have a > 2-stage pipeline, and in other posts they say it has a 3-stage pipeline. > How many stages do these mor1kx cores have in the implementations from the > 'orpsoc-cores' github repository? > Where can I see that information? > > 2014-09-09 4:28 GMT+01:00 Sébastien Bourdeauducq <[email protected]>: >> >> On 09/09/2014 11:21 AM, Ricardo Nobre wrote: >> > I would love to be able to benchmark the LatticeMico32. >> >> Don't forget to include the LUT count, something that your simulations >> will not show. From my tests with Coremark, LM32 and mor1kx have similar >> maximum clock frequencies in FPGAs, and run at roughly the same speed >> (in coremark iterations per second). >> But mor1kx uses a lot more LUTs than LM32 (this is the "bloat" I've been >> complaining about on IRC and this mailing list), even though its >> performance and functionality are not better. >> >> By the way, if you use MiSoC, you can switch between LM32 and mor1kx >> with a single command-line parameter of build.py. System-level >> simulations are not implemented though (only synthesis, with ISE, Vivado >> and Quartus). >> >> Sébastien >> > _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
