My configuration actually isn't created by me. It is default configuration
for Atlys SoC (I haven't change it). The configuration is:
.FEATURE_DEBUGUNIT("ENABLED"),
.FEATURE_CMOV("ENABLED"),
.FEATURE_INSTRUCTIONCACHE("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH(5),
.OPTION_ICACHE_SET_WIDTH(8),
.OPTION_ICACHE_WAYS(4),
.OPTION_ICACHE_LIMIT_WIDTH(32),
.FEATURE_IMMU("ENABLED"),
.OPTION_IMMU_SET_WIDTH(7),
.FEATURE_DATACACHE("ENABLED"),
.OPTION_DCACHE_BLOCK_WIDTH(5),
.OPTION_DCACHE_SET_WIDTH(8),
.OPTION_DCACHE_WAYS(4),
.OPTION_DCACHE_LIMIT_WIDTH(31),
.FEATURE_DMMU("ENABLED"),
.OPTION_DMMU_SET_WIDTH(7),
.OPTION_PIC_TRIGGER("LATCHED_LEVEL"),
.IBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0("CAPPUCCINO"),
.OPTION_RESET_PC(32'hf0000100),
.FEATURE_MULTIPLIER("THREESTAGE")
FEATURE_DIVIDER = "SERIAL", // default setting for mor1kx
Compiler
flags: -O2 -funroll-loops -fgcse-sm -mboard=atlys -mhard-div -mhard-mul -DPERFORMANCE_RUN=1
At least the cache configuration is more powerful (I don't know about
multiplier & divider implementation in LM32) . Additionally to Stefan's
list of mor1kx features, the mor1kx includes branch prediction engine as
default and not configurable part. Could LM32 be configured with such
feature?
However, I don't think that it is unfair. If somebody wants to achieve
better score, he/she have to pay for it. Personally, I would be happy with
coremark's score lying in region 2.4-2.7 (more is better for me). I foreseen
a pipeline with such performance could be even more bloated :).
P.S. Talking about 50 MHz constrain. It looks like just nobody have tried to
set it faster and play with router's settings to find corner value.
Andrey
-----Исходное сообщение-----
From: Sébastien Bourdeauducq
Sent: Monday, September 15, 2014 6:16 AM
To: BAndViG ; Ricardo Nobre ; Stefan Kristiansson ; List on OpenRISC.net ;
[email protected] ; Julius Baxter ; Jose de Sousa
Subject: Re: [OpenRISC] mor1kx and counting clock cycles?
On 09/15/2014 02:49 AM, BAndViG wrote:
By the way, I run coremark today on atlys board SoC (latest mor1kx
cappuccino pipeline) and measured 99.800399 Iterations/sec, that means
99.800399/ 50 MHz = 1,996. What is exactly value for LM32?
I've done tests in May/June with LM32 and mor1kx at 83 1/3MHz, and I
measured 133 iterations/s in both cases, so the score I got was 1.6.
This is my mor1kx configuration:
https://github.com/m-labs/misoc/blob/master/misoclib/mor1kx/__init__.py
This is slower than yours - are you using a faster configuration, or did
mor1kx improve in the meantime?
Sébastien
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