On Tue, Apr 9, 2013 at 4:08 PM, Michel Stempin <[email protected]> wrote: > Hi John, > > Le 09/04/2013 21:13, [email protected] a écrit : >> Does any one actually have one of the TopLink minPCIe boards? Their >> datasheet doesn't clearly identify the pins. They have pins called >> LINK1, LINK2, LINK3, LINK4. It is not clear what those pins do. They >> only expose two of the Ethernet ports so there is no need for four >> link status pins. > > Not yet, but asked for their datasheet and comparing it to the RT5350 > Preliminary datasheet, trying to sort things out like you do! > > Yes, LINK0-4 are the 5 link status LED pins, but these can also be used for > bootstrapping configuration and as standard GPIO #22-26, respectively, see > table 1-4 in RT5350 datasheet. > > Regarding the remainging pins, according to same table: > - GPIO #17-21 also correspond to the JTAG pins > - UART_TX and UART_RX are probably GPIO #15-16, respectively > - GPIO #11-12 are clearly identified as such in the pinout > - I2SCLK can only be GPIO #7, according to table 1-5 > - SPI_CS1 is GPIO #27, and SP_CLK, SPI_MOSI and SPI_MISO are GPIO #4-6, > respectively (GPIO #3 is SPI_CS0 and is probably used onboard for selecting > the SPI Flash chip) > - I2C_SD and I2C_SCLK are GPIO #1-2, respectively > > CPURST_N is probably PORST_N and WLAN_LED is WLAN_LED_N. > > This leaves GPIO #0, GPIO #8-10 and GPIO #13-14 to implement TopLink pins > PWR_LED, SECU_LED, RST_PBC, WPS_LED and WPS_PBC. These can probably be > guessed by probing using /sys/class/gpio.
I put two and two together and figured out that those are the names from the Ralink reference design, not the datasheet. So based on that observation.... TopLink RT5350 Function Group 1 WLAN_LED K1 WLANK_LED_N 3 LINK1 L1 EPHY1 GPIO23 5 LINK3 M1 EPHY3 GPIO25 7 SPI_CLK N1 SPI 9 UART_TX N2 UART-lite 11 I2SCLK P2 UART RTS_N, GPIO7 13 RST_PBC N3 UART RXD 15 GPIO11 N4 UART DTR_N, GPIO11 17 TXOM0 L5 Ethernet 19 TXOP0 M5 Ethernet 21 RXIP0 P5 Ethernet 23 RXiM0 N5 Ethernet 25 TXOP4 P9 Ethernet 27 TXOM4 N9 Ethernet 29 RXIP4 L9 Ethernet 31 RXIM4 M9 Ethernet 33 GND 35 UPHY_PADM N12 USB 37 UPHY_PADP P12 USB 39 GND 41 SDRAM_CS1N C14 SDRAM REFCLK0_OUT 43 I2C_SCLK B14 I2C 45 GPIO18 A14 JTAG TDI 47 WPS_PBC B12 GPIO0 49 GPIO17 A15 JTAG TDO 51 CPURST_N C10 PORST_N 2 TXD K2 UART TXD 4 SPI_CS1 L2 SPI 6 SPI_MISO M2 SPI 8 SPI_MISI J3 SPI 10 GPIO12 J4 UART DCD_N 12 LINK0 K3 EPHY0 GPIO22 14 PWR_LED K4 UART CTS_N 16 SECU_LED L3 UART DSR_N 18 GND 20 GND 22 3.3V 24 3.3V 26 GND 28 GND 30 3.3V 32 3.3V 34 LINK2 L4 EPHY2 GPIO24 36 WPS_LED M3 UART RIN 38 3.3V 40 UART_RX P3 UART-lite 42 LINK4 M4 EPHY4 GPIO26 44 I2C_SD B13 I2C 46 GPIO19 A13 JTAG TMS 48 GPIO20 A12 JTAG TCLK 50 GPIO21 A11 JTAG TRST_N 52 1.8V Looks like they have exposed all of the important pins. -- Jon Smirl [email protected] _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
