On Mon, 07 May 2001 10:48:49 +1000, Don wrote:

>
>> Combined in what way? Personally I write HDL (verilog), draw schematics,
>> layout PCBs, and write embedded software - I doubt many Protel customers
>do
>> all that as individuals although many will as companies. What use is a
>VHDL
>> or C compiler to a guy like...
>>
>> Brad Velander,
>> Lead PCB Designer,

>If you have a look at the current toolchain for the AT94 it will be
>immediately clear ( look for co-verification ) as to why it would be
>advantageous for Atmel to be able to source low cost modules to make the
>CPU&sea of gates ubiquitous.  

That still doesn't answer the question what does Brad want a C compiler
for. 

>Currently their tools are sourced from the big
>guys such as Mentor & have licensing & cost issues which prevent the devices
>from common usage.

I will agree providing low cost tools needed to do the job would help Atmel
and it's customers. 

>The manner in which the AT94 style of devices ( just about everyone has
>one ) operate, with strong interaction between CPU & FPGA requires tight
>coupling between CPU compiler & FPGA compiler. So there is a need for a CPU
>compiler, VHDL compiler ( With Schematic entry module ), Synthesis engine,
>Placer & a few dozen more bits.  Having the placer communicate with the Sch
>or PCB module to update  external netlists with revised pin functions would
>be a boon.

And now I'm going to get very cynical. Has anyone here managed to create a
schematic which could be simulated and could generate a netlist for PCB
layout? 

Protel's PLD product can't even create a schematic symbol with pin names
for compiled devices let alone support back and forward annotation. 

As for coverification? A company I used to work for had this big box in one
corner of the CAE area - I asked someone what it was for and was told it
was a hardware simulator (from Mentor or someone like that) cost $100k +
and was going to let them simulator all their HDL designs in real time, you
could even plug processor boards into it so if your design had a 386 you
could plug a 386 board into the simulator. As far as I could tell it hadn't
been used for anything more than dust collection because it didn't work or
was too complicated to try to make it work and what it might have been able
to tell you was not of enough interest. Of course the salesmen had no
problem suckering management into buying it with the promise of faultless
designs first time. 

Now if you are doing silicon with lots of expense and weeks/months of turn
round maybe it would be worth trying harder to get it right first time but
for something like the FPSLIC (why did they call it that, any fool knows
SLIC = Subscriber Line Interface Circuit) which you can re-program in a
couple of minutes why bother? 

I don't see C writers using simulators to test their code much, I don't see
HDL designers making use of much more than processor bus models for
stimulation in their testbenches. I don't know the AT94, is it more than an
AVR core an FPGA on the same die? can you actually extend the instruction
set with a bit of the FPGA for example? 

Coverification may be more reasonable for soft cores placed in FPGAs where
the core may be modified or the placement proved, but, are C coders really
going to debug thousands of lines of code on a gate level simulator? More
like the HDL writer is going to use a handful of assembler in his
testbenches so why integrate a C compiler? 

And the only reason for integrating a VHDL synthesiser is so you can back
annotate to schematic? Or write VHDL in schematic (spit).

Basically I don't much buy the idea of integrating everything in design
explorer (actually I would have bought the idea of using design explorer as
a container for all design information including C and VHDL code if they
hadn't made such a mess of it  - I don't have any compilers which read
source files as OLE objects for example). 




>
>Don
>

Cheers, Terry.


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