Forum members,
Does anyone know whether or not Protel can find
entities in a PCB design that are extraneous and
should be removed [like hangers of etch from removed
components, unnecessary vias, etc.]? I would think
that setting up the design rules a specific way may
accomplish this, but it isn't indicated in any
documentation I can put a finger on so far. I welcome
any suggestions and look forward to everyone's
responses in this matter. Take it easy and thanks in
advance for your feedback.
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