The is a server add-on for P98 that calculates the manhattan ratio which 
is  density metric of some sort.  has not been reworked/recompiled for 
P99SE that I could see.  Though it couldn't be too hard to do so if someone 
so desired.

Also, George Messner covers density evaluations in moderate detail in 
Section 1.5 of Printed Circuits Handbook 4th Edition. (Ed Clyde F Coombs, 
McGraw-Hill, ISBN 0-07-012754-9).  But this is possibly not much use to you.

You can also get a density map (PCB:  Tools-Density Map) but this is only 
useful to show possible bottlenecks for routing after placement.  It is not 
useful for estimating degree of difficulty or possibility of success.

Advanced Route 3 had a pre-route phase where it estimated the likelihood of 
success based on number of nets, placement, routing constraints etc.  But 
this was also post-placement.

Some sort of industry standard (or at least accepted/published) calculation 
based only on number of connections, component footprints, pad/via sizes 
and routing technology (number of layers, blind/buried vias etc) would be 
possible.  The calculation could show the required routing area given a 
wiring efficiency factor Weff, (a number that is usually about 50% but with 
some blind/buried stack-ups may get close to 75%) or the required Weff 
given a board.  But I am not sure how useful this would be - I have the 
details for doing the calcs but I have never done them.

Something to toss about.  Maybe such analysis can be done effectively these 
days.

Ian Wilson


On 07:39 AM 7/02/2001 +0100, Georg Beckmann said:


>A real good idea,
>
>That means, that you see a percentage of board space used every time
>you place a new part in schematic.
>Relatively easy would be a sum of all the part-space divides the total
>board - space.
>But does this help ?
>Example: a 100 by 100 board can't have to parts 51 x 51, even only a bit
>more then the
>half board space is used.
>
>The next step would be an optimising program which is not done over weekend.
>
>Georg
>[EMAIL PROTECTED]
>
> >
> > Hi everyone.
> > How often have you come across a design where you just not
> > quite sure if
> > the electronic required actually fits the "board".
> > Oh yes - we all do know - Once we've spent all those hours
> > trying your very
> > best in achieving, not only the "Perfect Layout" to suit the
> > circuit, but
> > also trying your very hardest to squeese and squash, because of the
> > awareness of tight and or limited boardspace.
> > However - isn't that a bit too late to realise that it won't fit the
> > current situation.
> > It would be a tremendous help to get a density report based
> > on boardsize
> > and physical component-outline, incl. pads - whichever is bigger,
> > overhanging. Care however needs to be taken not to include
> > any component
> > designators and comments, as they are placed outside the footprint.
> > Well, thats one of so many features I could get used to so quick.
> > Lets wait and see what Protels Softies think about this feature.
> > Thank you Protel for considering.
> > Cheers
> > Robi
> >
> > Robi Artwork  -  PCB Design Bureau
> > PO-Box 199,    Lot 33 Jamaica Drive
> > Deception Bay  Q4508        Australia
> > ------------------------------------------------------
> > C/o Robi Bittler
> > Ph: 07-3203 0634   Fx: 07-3203 3958
> >
> >
> >
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