At 08:27 AM 2/8/01 -0800, Brad Velander wrote:
>Stuart,
>         are your missing holes single layer (top or bottom) pads by chance?

Stuart had written "vias." Vias don't have a top/bottom attribute.

However, let me take the occasion to ask that reports like this come with a 
little more information. What size were the vias? Were there any special 
characteristics about them, such as blind or buried? What were the drill 
drawing plot settings?

If the plots are run again after unloading and reloading Protel and the 
DDB, does the problem still appear? If so, then it becomes possible for 
others to examine it in detail. Sometimes it is good to attempt to cut such 
a file down to a small file that still displays the error, which makes it 
easy to send to others and also keeps the actual design confidential.


Abd ul-Rahman Lomax
LOMAX DESIGN ASSOCIATES
PCB design, consulting, and training
Protel EDA brokering (resale) services
Sonoma, California, USA
(707) 939-7021, efax (419) 730-4777
[EMAIL PROTECTED]
[EMAIL PROTECTED]




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