the quoted dielectric constants for the materials should be stated
for the completed product (laminated). Therefore it will be that figure
specified for the material. There are some variances due to the variations
in pressing, but that is the fabricators responsibility to properly process
the materials they use. If they do it right then the Dk should be very close
to the stated spec. If they do it wrong, then it can be way off.
        On your copper sizing. Again the fabricator should process the board
(including artwork generation) to end up at the figures which your Gerber
has specified. This will mean that they will tweak the line widths of their
starting artwork to allow for their process tolerances. Good shops will do
this automatically for all jobs, some shops will only do it for jobs which
demand it in their order/fab dwg/readme. For good measure, we include the
following statement in our fab dwgs or readme files.

"The widths and gaps given in the Gerber data, arte the finished sizes
required. Etching tolerances shall be no greater than +/- 0.0005" across the
widths and gaps from that given in the Gerber data."

        For this spec we are using 1/2oz copper foil and most manufacturers
should be able to obtain the 0.5 mil tolerance spec. They may protest
slightly but in practice they can typically meet this figure. If they are
scared about their process tolerances then they could step down to 1/4oz Cu
foil and easily meet this spec. This spec does not include undercut but just
the general track width when measured from above.

        Tim, one of the better websites that I have found over the years is
at the following URL. I don't remember exactly what is on their site but you
should find it interesting. Check out their resource center.


Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com

> -----Original Message-----
> From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, August 23, 2001 8:18 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Warping on small odd layer boards.
> Got it.  Thanks.  Does anybody have any ideas about how much 
> the dielectric
> constant generally changes as a result of the pressing 
> process and by how
> much a 5-mil trace shrinks on average?  If I had a general 
> idea about this I
> could make a better estimate of the target configuration 
> needed for the best
> impedance match.
> Thanks in advance.
> Tim Hutcheson
> Institute for Human and Machine Cognition
> 40 S. Alcaniz St.
> Pensacola, FL.  32503

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