AuRL> If the design is so much low speed that you need not pay attention to power
AuRL> routing topology, then it is so much low speed that probably doing pours is 
AuRL> unnecessary. The same arguments apply to both!
Well,  the design presented an excellent opportunity to experiment
with poly pours,  which I took advantage of.  Low cost, 2 layer,
in-house,  low speed proto.  Where better to do some experimenting?
(was well worth it too,  as I learned several things.)

AuRL> A *direct* way to not route VCC and GND would be to delete the nets using
AuRL> the Netlist Manager. Then resynchronize the PCB and schematic....
The schematic was imported in from an Orcad design.  We did this a few
times,  as someone else did the schematic in Orcad.  There was also a
problem where the net labels were not attaching themselves to the

AuRL> Don't do a VCC pour.
Good advice.  Yeah,  a good board to experiment on...  :)

AuRL> Another way to prevent the routing of a net, with a through-hole design, is
AuRL> to create an inner plane for the net....
There were no inner planes here,  just a cheap 2 sided board.

AuRL> But there was no good reason I can see to prevent the routing of those 
AuRL> nets. The pour, if one insists on having one, can then be poured over the 
AuRL> existing nets. The only problem with this is that there will likely be 
AuRL> extra copper ties to the pour, which is harmless but unsightly.
It was a combination of the "stepping on" of the thermal relief by the
routed net,  along with having some wide VCC tracks on the GND pour
side (and vice-versa) from the routing.  Either by itself might have been
"good enough for proto work".  Indeed we almost shipped it.  But I decided to
look for a way to make it a bit less unsightly.

AuRL> Abdulrahman Lomax
AuRL> Easthampton, Massachusetts USA

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