Phillip,
looking at just your comment below, seems that you had accomplished
your task. However, it sounds like you did not assign the correct netname to
your polygon pour or you did not check the pour over same net checkbox in
the polygon pour control, when you made that attempt.
Brad Velander,
Lead PCB Designer,
Norsat International Inc.,
#300 - 4401 Still Creek Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com
> -----Original Message-----
> From: Phillip Stevens [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, September 05, 2001 1:23 PM
> To: Protel EDA Forum
> Subject: [PEDA] Not routing nets and poly pours...and maybe a bug for
> the bug list?
>
> Not seeing a direct way to do this, I tried a few things like making
> rules for VCC/GND nets to be 0 width traces.
> If you do this, when you do the pours, you get whatever
> the clearance is on both sides of a 0 width trace, so you end up
> with holes in the poly pour around a 0 length trace. In a way what I
> told it to do I guess, but not what I really wanted...
>
>
> Anyway, I finished my board. Wanted to report the router bug, and
> ask if there is a more direct path I can use for this next time.
>
> ---Phil
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
