At 04:23 PM 9/5/01 -0400, Phillip Stevens wrote:

>How does one specify a Net not be routed,  but still be checked
>for in the ERC?  I have a pretty simple 2 layer board.  2" X 2.7"
>with a few parts on it.  I'm using P99SE SP6 on Win98
>What I wanted to do was to route all the signal lines first and then poly pour
>VCC/GND.  (This is a simple,  low speed, low cost, 2 layer design btw..)

If the design is so much low speed that you need not pay attention to power 
routing topology, then it is so much low speed that probably doing pours is 
unnecessary. The same arguments apply to both!

>Not seeing a direct way to do this,  I tried a few things like making
>rules for VCC/GND nets to be 0 width traces.

>If you do this,  when you do the pours,  you get whatever
>the clearance is on both sides of a 0 width trace,  so you end up
>with holes in the poly pour around a 0 length trace.   In a way what I
>told it to do I guess,  but not what I really wanted...

Mr. Velander inferred from this, I think correctly, that Mr. Stevens had 
not set "pour over same net," which would have accomplished what he wanted.

A *direct* way to not route VCC and GND would be to delete the nets using 
the Netlist Manager. Then resynchronize the PCB and schematic....

But I would suggest, for a board like this, unless there is some condition 
which has not been explained, that power and ground be routed *first*, 
manually, which is the only way you are going to get a good low-impedance 
power route (it might not be necessary, but it won't hurt, for sure), then 
route the signals (and if this is a very small design one might skip the 
autorouter anyway, but to each his own...), then do ground pours. Don't do 
a VCC pour.

It's been noted that "there is no ground" but there sure is when one is 
considering possible shorts to a case or what can happen with a careless 

Then I tried making the trace width impossibly large.  It's a 2" X 2.7"
>board,  so I made the (min/max/pref) trace width all 5".  That
>way it can't _possibly_ route those nets.... then I'll just do the poly
>pour over it...  The router happily placed 3-4 VCC/GND tracks down
>on the board.  At maybe 50-100 mil width.  This has to be a bug?
>The router should not put down tracks that fail to meet the design

Hmmm, a designer considers the program's behavior a bug; perhaps the 
program would have the right to call the designer's behavior a bug! Feeding 
a program data which is outside what would have been thoroughly tested is a 
good way to discover unanticipated results. If it works, great! But don't 
be surprised when it doesn't work!

Another way to prevent the routing of a net, with a through-hole design, is 
to create an inner plane for the net....

But there was no good reason I can see to prevent the routing of those 
nets. The pour, if one insists on having one, can then be poured over the 
existing nets. The only problem with this is that there will likely be 
extra copper ties to the pour, which is harmless but unsightly. If the 
original track is highlighted -- which could be easily done with a global 
edit of track with the appropriate net as a selection criterion -- and then 
deleted, this would quickly clean that up.

>I also tried net unroute,  but this seems to just take out a segment
>of the net,  and not the whole net (though I think this may have
>worked in the past).  Even had this worked though,  the traces would
>not have been as direct as they could have been without the VCC/GND nets in
>the way.

And since it is a low-speed design, why care about that?

Abdulrahman Lomax
Easthampton, Massachusetts USA

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