Ian, this is a good suggestion, however, the PCB hasn't any named nets. He
just wires point to point, and keeps track of the wiring in his head by
using his rough schematic.
Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170
----- Original Message -----
From: "Ian Wilson" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, November 12, 2001 5:28 PM
Subject: Re: [PEDA] HELP!

> On 02:36 PM 12/11/2001 -0500, Sean James said:
> >Has anybody out there ever have to upated a schematic's reference
> >designators based on a PCB layout, when there is NOT a netlist to back
> >annotate.
> Yes.
> >  I have to clean up an engineer's schematics, and he refuses to use an
> > inteligent schematic & layout. He just places the parts on the board and
> > wires them up.
> Replace the engineer - I certainly do not accept any engineers work
> (including my own) that is this sloppy.  Engineering is a discipline not a
> place for artisan w*nkers.  The artisans may create good designs but can
> you produce, test and maintain them?  Especially when just a little more
> work would make it easy for someone else to come through and fix up the
> problems.  (This is similar to the difference between a talented software
> hacker and a software engineer - one may be very good at creating code but
> who do you want writing your automobile ABS software?)
> Lloyd and Abd ul-Rahman's idea of putting responsibility for sign-off back
> where it belongs (the engineer) is very good, I think. But if the engineer
> involved is the boss then you are stuffed :-).  All you can do is document
> well the time spent so when the issue comes up, due to time to market lag
> or a parts ordering stuffup or whatever, you at least have some
> documentation.  Bum covering is not a good way to operate, I think, but I
> am fully aware that in situation like you could see the engineer may well
> have the bluster and the respect of those above to make your position
> difficult if there is a problem.  I have backed up techs and untrained
> people when engineering colleagues (and engineering managers) started to
> get bombastic and overbearing.
> >Not only does this create a situation where I have to clean up the
> >schematics (Ref Des's; missing or incorrect parts; wrong connections,
> >etc.), it is also difficult and time cosuming to go back through the
> >and assign our company's part numbers.
> For cleaning up the layout of the sch - manual operation.  Protel Sch has
> very little in the way of Sch layout intelligence.  The rubber banding is
> poor as well so it can be a very slow operation if you have lots of clean
> up to do.  Even much cheaper packages have better rubber banding.  This
> been a mark against Protel Sch for a long time, as has the issue of *not*
> merging co-linear line segments, which is something to be wary of when
> doing bulk neatening up.
> For adding company info to the sch symbols you may find the spreadsheet
> format is useful as you can block copy similar info quickly and then
> the Sch.  Use the Export-to-Spread process.  There are issues with how you
> manage the process - basically:
> 1) do not mess about with the hidden handles (column B, I think, that is
> hidden),
> 2) Keep the hidden handles sorted with the other columns, as they are the
> association back into the Sch (it is not by designator, which is very
> useful when you have bulk designator changes to do)
> 3) The hidden handles are not persistent so you must keep the Protel
> session open while doing the edits in the spreadsheet.
> 4) When you export from the Sch (or PCB) you can then select everything
> paste into a more capable spreadsheet, do you edits, select all and paste
> back and then update - as long as you observe rule number 1.  (This allows
> you to run more elaborate macros.)
> Maybe the database linking function would help as well - but it is
> as being deathly slow.
> You say there is not a netlist.  Why is this?  You can generate the
> from the PCB and then do a compare with the sch netlist. (as AL offered in
> his recipe).  As I understood it you have a Sch but it needs cleaning
> up.  is the Sch a paper copy of a Protel sch?  If you have a problem with
> the PCB and the Sch designators not matching, then I would get them
> matching using the spreadsheet option or simply double clicking each
> component, using the netlist compare as a help, and the synchronize to
> allow all the other info to be matched - but watch out during
> synchronization that you go the best way - if you got from Sch to PCB you
> will want to make sure that the PCB footprints are not updated.  Then once
> all the value info is correct in the PCB you can transfer the PCB
> footprints back into the Sch using the synch.
> You may also find it helpful in doing Abd ul-Rahman's netlist matching to
> make as many multi-pinned components match as possible.  So all the
> manually match as many ICs and some of the R's and C's that are easy - as
> this will make the netlist matching much easier as many of the designators
> in each net will be correct.
> Bye,
> Ian Wilson

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