I don't have help for you, but maybe I have help for him.

If the reason he won't use schematic capture is that he thinks optimum
placement and routing is achieved by placing and routing, then figuring out
the schematic later, I have a suggestion for him.  I have had to do
something like this before, where placement and routing dictacted all else.
I did it by designing a tentative schematic first (with netlist), routing
the board, and then changing the schematic to match the board.  Many changes
were required, but it was still worth the effort.  It was a bit of "tail
wagging the dog", but was necessary due to extreme placement and routing
requirements.  This was tougher to do back in the days of v2.8.  It should
be easier now with 99SE synchronizer.

Is he using non-netlist-aware layout software?  As I recall, PCBExpress
gives away free software that can be used to lay out double-sided boards,
but it is not netlist-aware.  So I don't think you could generate a netlist
from it, unless you generate it from Gerbers.

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com

----- Original Message -----
From: "Sean James" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, November 12, 2001 2:36 PM
Subject: [PEDA] HELP!

Has anybody out there ever have to upated a schematic's reference
designators based on a PCB layout, when there is NOT a netlist to back
annotate. I have to clean up an engineer's schematics, and he refuses to use
an inteligent schematic & layout. He just places the parts on the board and
wires them up. Not only does this create a situation where I have to clean
up the schematics (Ref Des's; missing or incorrect parts; wrong connections,
etc.), it is also difficult and time cosuming to go back through the board
and assign our company's part numbers.

Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170

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