The one test program I wrote for testing  a 4 by 4 crosspoint switch ended up at
24  A4 pages of test patterns. The other memory chip we where testing at the
time (a CAM memory) used the automatic pattern generator in the tester and was
truely massive in being in the 100's of thousands of lines of test vectors.
These where just the functional tests and the other DC type tests also where
done. The point is that the device is pretty thourougly tested


_______________________________________________________________

Clive Broome
IDT Sydney Design Centre        Ph:         +61 2 9763 3513
8 Bayswater Dr, Homebush        Fax:        +61 2 9763 3409
Sydney,  NSW, 2127              Email:[EMAIL PROTECTED]
Australia

_______________________________________________________________







"Jon Elson" <[EMAIL PROTECTED]> on 11/20/2001 09:49:30 AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:    (bcc: Clive Broome/sdc)

Subject:  Re: [PEDA] Protel's Good/Bad points (WAS:Using 3D)





Not to continue this off-topic thread too far, but they only test the
memory chips for a few seconds in each condition (hot, cold, etc.)
and with the number of bits in a chip, it has to be a cursory test.
The noise conditions present on the chips after they are mounted
on the SEMM/DEMM module may not be ideal in all systems,
either.

> At any rate... if anyone is interested in FULLY testing your







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