If your only requirement is to avoid instances where the designator is
placed over a via/pad, then the following is a solution, all be it not too
elegant;

Add an extra internal layer
Change the layer your designators are on to this new layer
Set up a clearance rule between tracks on this layer and vias/pads.

Any violations will then be flagged as usual. Just remember to return your
text to the original layer before producing your gerber files.

This works well with boards that have designator on one side only, but is
more painful with double sided boards as you can't globally select
designators on specific layers.

Dave




"Anthony Whitesell" <[EMAIL PROTECTED]> on 28/12/2001 14:17:54

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:

Subject:  [PEDA] Design Rules



Does anyone know if it is possible (or how to) set a design rule to check
between the overlay and the soldermask layers?  If you place a designator
over a pad or via then it does not appear correctly on the finished PCB.  I
have simplified the solution to check the reference designators versus the
[inverted] soldermask of the same side and make sure they don't overlap.  I
was hoping to automate the process with a design rule.  Any ideas?

Anthony Whitesell
Sunrise Labs




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