I could never get the Schematic/Compile/JED/PLD chain to work. I have used the CUPL text entry exclusively and it works ok.
Jeff Stout P.S. People here have urged me to dump Protel when I had problems targeting an Altera EPM7032 (see "Fun with PLD 99"). Well, I've resolved the problems and it's working ok now. ----- Original Message ----- From: "Geoff Harland" <[EMAIL PROTECTED]> To: "Protel EDA Users" <[EMAIL PROTECTED]> Sent: Tuesday, February 19, 2002 10:05 PM Subject: [PEDA] Cpld question > This is a question I am posing on behalf of a workplace colleague. > > Does anyone have a working schematic capture example for the Xilinx- CPLD > 9536VQ44 producing .jed file? (Either for Protel 99 SE or Protel 98.) > > Regards, > Geoff Harland. > ----------------------------- [snip] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
