> >
> > Does anyone have a working schematic capture example for the Xilinx- CPLD
> > 9536VQ44  producing .jed file? (Either for Protel 99 SE or Protel 98.)

Oh, yes.  I remember one other thing I found that was responsible
for part of the problem.  There are different libraries for specific
chip families.  In one of the Xilinx families, the common library
components like counters had been converted automatically from
some other source.  The conversion program dropped connection
'dots' from part (or maybe all) of a number of the components.
These seemed to fall heavily on the clock wires for a bunch of the
binary counters.  What it meant was that usually only one flip-flop
of the counter received the clock signal.  The design rule check
would find that many of the FFs had no clock, so it was hard to miss
that something was seriously wrong.  I had to pick through the HDL
code to figure out what had happened.  There were no schematic
definitions of these symbols, but I found them on an old Protel
disk, and the missing dots exactly corresponded to the missing
connections in the HDL definitions for the symbols.  So, I corrected
the schematic sheets, and recompiled those components.  This fixed
things at the schematic -> HDL level so I could simulate the circuit,
but I still couldn't get from HDL to a placed and routed device.

Jon

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