> I have used Protel PLD to create GALs with much success, but then I had
> used CUPL for that purpose in the past.. I do not like PLDs created in
> schematic capture and my experience trying to support the ones I inherited
> that were done in schematic capture has led me to conclude that it is a big
> mistake.

Well, there are certainly a lot of people on your side, but schematics still
make more sense to me.

> With Xilinx you have to be careful what library items you use and make sure
> that the correct XNF for the library items are used by the Xilinx tool.  If
> this is a current Xilinx part supported by the current Xilinx tools I would
> use VHDL or Verilog to create the source files than use the Xilinx tool to
> compile it.

  When designing DSP filters or highly numerical circuits, then the HDL
makes a lot of sense.  When things are highly repetitive, HDL also makes
things easier.  I do a lot of control logic, bus interfaces, etc. and a
just is much faster to glance at and see the area where one is concentrating
one's interest at the moment.  I just finished a design that pretty much
fills a Spartan XCS30 (30K gate) array.  It has a bus interface, 4 24-bit
quadrature encoder counters, 4 24-bit programmable rate generators with
some extra logic to adjust setup and hold times at the outputs, and some
digital I/O pins.  This all fits on about 5 sheets of schematics.  The Xilinx-

generated VHDL runs on for 50+ pages.  Hand-coded VHDL would be shorter,
of course, but I think still more cryptic than the schematics.  This is not
on all projects, but for me, I prefer it this way.  A recent project had
binary to Gray code and Gray code to binary converters.  I did these in
VHDL, as it was a LOT more concise (about 8 lines each).  I then created
schematic symbols from these VHDL modules and put them on the schematic

I am using Xilinx Foundation for this, as I just couldn't get Protel to handle

Xilinx parts properly.  I really prefer the schematic editor and the simulator

in Protel, they are a lot more user friendly and intuitive that Xilinx, but
back-end would not work for Xilinx parts.


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