Jason, You indicate the "Profile is Optimum" according to Fab. Which I conclude to be, that the layer stack up order is balanced around the center line of the board stack up.. As well , you indicated or implied the copper is equally distributed on each signal pair and internal plane pairs on either side of the center line of the layer stack up. Which means No odd numbered plane layers or signal layers..in the stack up.. etc.. No predominate copper pour areas in one section of the board vs. another. No split plane areas that are not balanced by a corresponding split plane area.. on the other side of the centerline of the layer stack up...etc.
I have discovered that a balanced copper distribution is the number one requirement to control and or minimize warpage. If there is substantial difference in the percentage or density of copper on the signal layers, you will see differential expansions during reflow. That differential force will warp and twist the board and as it has been said in the past post a quick cool down will set the twist or warp. You indicated the component layout and thermal profile are probably not to blame. The question I ask, Is there a higher concentration of direct connection to the plane in one area vs.another? This will have a tremendous heat sinking differential and could cause a warpage as well. If all is well in the areas mention above.. Then that leaves Fab. shop with the lions share of the responsibility for warped boards if in fact the above conditions are met. Generally plating differentials are not enough to warp a board beyond 10% out of plane.. Fab. will need to review their process controls. Speed (time in the flow) and temperature here are the main parameters. I would look at the speed or the amount of time the board in the jig is sent through the Flow. If you can prove and or get fabrication to admit it is not in the design or layer stack up then it becomes their full responsibility and you should not have to pay for warped boards. Here, I assume you have in your fabrication drawings a specification that defines the acceptable percentage of warpage. That is my two cents.. Sam Cox. At 04:40 PM 4/4/2002 +0100, you wrote: >Thanks for all the advice and suggestions. > >Some more info that I missed from the first post: > >We've been trying to solve this for some time. We've tried boards supplied >from more than one house and populated at more than one house, all with the >same sorts of results. > >We're not the fab, so we have no control on the process, its up to their QA. > >The profile is optimum (according to fab) and any change would result in bad >joints. > >We've tried reflow and wave with the same or similar results. > >We've tried with and without components with the same or similar results. > >So the component layout and thermal profile probably are not to blame. > >It must be the board design or the results of that combined with the >conventional layup for such a design. > >I can't say who designed the rack, but to our knowlege their own cards fit >into the rack OK - even though our samples are twisted to a small degree. > >We're prepared to try adding hashing to the inner layers - it seems logical, >but as the PCB house seem not to be sure we don't want to spend the money on >a run without all the available information (it costs 2k for each run). > >I'll keep you all informed of the solution and the outcome, thanks once >again for all the help. > >Jason > > >-----Original Message----- >From: Jon Elson [mailto:[EMAIL PROTECTED]] >Sent: 03 April 2002 21:53 >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >Jason Morgan wrote: > > > Many thanks, > > > > Details are as follows: > > > > 6 Layer 1.6 FR4 > > 8" x 10" Board > > > > PCB support is a wasted rectangle 10mm wide along all edges, supporting >PCB > > at 2 or 3 points along each edge. (First observation is that this should > > have copper layers) > >A number of different ways to even out copper coverage on layers on >opposing sides of board were mentioned, and these are probably aimed >at solving residual stresses left in the board. That sounds good, but may >be difficult to accomplish, dpending on board density, etc. > >One thing that comes to mind is that the boards come out of the laminating >press flat, go through all the additional steps in PCB fabrication OK, but >then warp when YOU process them to attach components. Are you sure >you have to heat the boards as hot, for as long as you are doing, to get >good soldering? That may have something to do with it. > >Finally, could you give the boards some mechanical support during the reflow >soldering? Making some simple metal frames that hold the board edges >during the entire time it is heated might keep them flat as they cool. > >Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
