I have to backpedal on the CTE differences, I jumped on it because the pure CTEs are that much different, all other things being equal. I have no idea what Ni-Au alloy CTE is vs Cu.
I think Mr. Selfridge enumerates the more likely culprits. I have experienced some of those, albeit on MUCH larger boards, e.g. 14" x 17" x 0.093 with a LOT of weight--many rows of small relays. 8 by 10 is pretty small, so I agree that you would look at the laminate process, copper distribution on matched layers, and the jig. > -----Original Message----- > From: H. Selfridge [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, April 03, 2002 13:24 > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Some things to consider: > > 1. FR4 resin transition temperature is between 115C and > 135C. Reflow > soldering temperatures are typically 215C to 255C. Any > internal stress in > the board will be relieved by warp and twist when the board > becomes plastic > at the reflow temperature. The board fab must use care when > pressing to > ensure that cooldown is controlled and uniform - otherwise > internal stress > is created which will try to relieve in the reflow process. > > 2. Since reflow temperature is typically above resin transition > temperature, the board must be properly supported during > reflow. If the > jigs are not properly set, the board will deform during reflow. > > 3. Component placement on thin boards is a factor because of > weight during > reflow, and because of component heat-sinking during reflow. > Again, the > jig placement, and cooldown control are critical. > > 4. Your details suggest you have tried to keep a balanced copper > distribution. If, however, there is substantial difference in the > percentage of copper on the signal layers, you will see differential > expansion during reflow. That differential force will warp > and twist the > board - quick cooldown will set the twist. > > From your comment that the board tends to flatten after a > period of time, > it seems likely that one of items 2 thru 4 above is at play. On the > limited information available, I would look especially > carefully at the > copper balance in opposing layers. > > > > > At 04:52 PM 4/3/02 +0100, you wrote: > >Many thanks, > > > >Details are as follows: > > > >6 Layer 1.6 FR4 > >8" x 10" Board > > > >PCB support is a wasted rectangle 10mm wide along all edges, > supporting PCB > >at 2 or 3 points along each edge. (First observation is > that this should > >have copper layers) > > > >Layer stack up is two cores + two foils (sizes rounded to 1 > decimal place) > > > >R/P Layer Type thou > >- - Resist 0.4 > >R 1 Ni/Au 0.5oz 1.1 > >R 1 Foil 0.5oz 0.7 > >- - Prepreg 7630 7.0 > >P 2 1oz Copper 1.4 > >- - Core 15.0 > >R 3 1oz Copper 1.4 > >- - Prepreg 1080 5.0 > >- - Prepreg 1080 5.0 > >R 4 1oz Copper 1.4 > >- - Core 15.0 > >P 5 1oz Copper 1.4 > >- - Prepreg 7630 7.0 > >R 6 Foil 0.5oz 0.7 > >R 6 Ni/Au 0.5oz 1.1 > >- - Resist 0.4 > >--------------------------------- > >Total 64 = 1.625mm > > > >Effects are: > >Boards are flat from production, but twist on heating in > solder reflow or > >wave solder. > > > >An analysis of 5 board produced 1 that exceeded the IPC warpage > >specifications. > > > >Trouble is all but one was too twisted to fit into the rack > without effort. > > > >We had the same problem with the alpha version, but here > this was put down > >to an incomplete plane > >on the two plance layers, this has been changed to a full > plane - no change > >to warp. > > > >Suggestions so far have been to: > >0: Add copper to waste (breakout) parts layers > >1: Change the breakout to a waste part scored along the > two long edges. > >2: Use a three core construction > >3: Add copper hash to layers 3 and 4, (other either > side of the two > >cores) > >4: Change warp and weft of cores > >5: Increase core thickness and decrease 1080 prepreg thickness. > >6: Use 1.8 FR4 by increasing core thickness (undesireable) > > > >So far we've had no input from the manufacturer as to what > (if any) of the > >above will be better, though > >they agree that all should have some affect (positive or > negative) on bow > >and twist. > > > >We've also noticed that over a long period (weeks) the twist > gets less. > > > >Regards > > > >Jason. > > > > > >-----Original Message----- > >From: Mike Reagan [mailto:[EMAIL PROTECTED]] > >Sent: 03 April 2002 16:43 > >To: Protel EDA Forum > >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > >Jason > >Some of our advice is free > >What process is warping the boards? Reflow or > manufacturing? or upset > >employee? > > > >Mike Reagan > >EDSI > > > > > > > >----- Original Message ----- > >From: Jason Morgan <[EMAIL PROTECTED]> > >To: 'Protel EDA Forum' <[EMAIL PROTECTED]> > >Sent: Wednesday, April 03, 2002 9:03 AM > >Subject: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > > > Hi, > > > > > > We have a board warping problem and are looking for a PCB > expert to help > > > resolve it. > > > (Preferably located in the UK, but not important) > > > > > > When I say expert, I mean *EXPERT*. The problem is quite > complex and > >already > > > has baffled two manufacturers. > > > > > > We will pay the going rate for any consultation. > > > > > > Regards, > > > > > > Jason Morgan > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
