Monitoring - sort of, bit busy for full followup. Anyway, I did post a full explanation that the plating would be Cu+Ni+Au, no idea on the proportions.
J. -----Original Message----- From: Mark E Witherite [mailto:[EMAIL PROTECTED]] Sent: 09 April 2002 15:34 To: Protel EDA Forum Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Hi Igor, There were many other post to this subject. Have you examined the gerbers? The only reason I could think of to use such a thick nickel plating would be to provide some EMI shielding. If that were the case then I would suspect there would be polygons. Jason never verified that the nickel plating was 1.1 mils. I also assumed that all the most common problems have been investigated. That's a bad assumption. This last year I learned that a board house is only as good as it's production employees. a company that was once a NASA's top ten list, sent me batch of boards with two nets shorted. And yes they were ordered with bed of nails testing. Lastly I did the math on the expansion ( assuming low stress nickel). I only got a difference of about 4mils in the two metals. I would think that this would only cause a bow of less than 4 mils. Sorry for shooting off before I pick up the calculator. I would still like to know if the nickel plating thickness was really 1.1mil. How about it Jason ? Are you still monitoring this thread? Cheers Mark At 08:47 AM 4/9/02 +1000, you wrote: >Agree witht that. Also, there seem to be no polygons placed on the routing >layers, which might add to the problem. > >Igor > >-----Original Message----- >From: Mark E Witherite [mailto:[EMAIL PROTECTED]] >Sent: Thursday, 4 April 2002 4:56 AM >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >My Money is on the mismatch of thermal coefficient of expansion between the >copper and the nickle gold foil. > >At 04:52 PM 4/3/02 +0100, you wrote: > >Many thanks, > > > >Details are as follows: > > > >6 Layer 1.6 FR4 > >8" x 10" Board > > > >PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB > >at 2 or 3 points along each edge. (First observation is that this should > >have copper layers) > > > >Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) > > > >R/P Layer Type thou > >- - Resist 0.4 > >R 1 Ni/Au 0.5oz 1.1 > >R 1 Foil 0.5oz 0.7 > >- - Prepreg 7630 7.0 > >P 2 1oz Copper 1.4 > >- - Core 15.0 > >R 3 1oz Copper 1.4 > >- - Prepreg 1080 5.0 > >- - Prepreg 1080 5.0 > >R 4 1oz Copper 1.4 > >- - Core 15.0 > >P 5 1oz Copper 1.4 > >- - Prepreg 7630 7.0 > >R 6 Foil 0.5oz 0.7 > >R 6 Ni/Au 0.5oz 1.1 > >- - Resist 0.4 > >--------------------------------- > >Total 64 = 1.625mm > > > >Effects are: > >Boards are flat from production, but twist on heating in solder reflow or > >wave solder. > > > >An analysis of 5 board produced 1 that exceeded the IPC warpage > >specifications. > > > >Trouble is all but one was too twisted to fit into the rack without effort. > > > >We had the same problem with the alpha version, but here this was put down > >to an incomplete plane > >on the two plance layers, this has been changed to a full plane - no change > >to warp. > > > >Suggestions so far have been to: > >0: Add copper to waste (breakout) parts layers > >1: Change the breakout to a waste part scored along the two long >edges. > >2: Use a three core construction > >3: Add copper hash to layers 3 and 4, (other either side of the two > >cores) > >4: Change warp and weft of cores > >5: Increase core thickness and decrease 1080 prepreg thickness. > >6: Use 1.8 FR4 by increasing core thickness (undesireable) > > > >So far we've had no input from the manufacturer as to what (if any) of the > >above will be better, though > >they agree that all should have some affect (positive or negative) on bow > >and twist. > > > >We've also noticed that over a long period (weeks) the twist gets less. > > > >Regards > > > >Jason. > > > > > >-----Original Message----- > >From: Mike Reagan [mailto:[EMAIL PROTECTED]] > >Sent: 03 April 2002 16:43 > >To: Protel EDA Forum > >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > >Jason > >Some of our advice is free > >What process is warping the boards? Reflow or manufacturing? or upset > >employee? > > > >Mike Reagan > >EDSI > > > > > > > >----- Original Message ----- > >From: Jason Morgan <[EMAIL PROTECTED]> > >To: 'Protel EDA Forum' <[EMAIL PROTECTED]> > >Sent: Wednesday, April 03, 2002 9:03 AM > >Subject: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > > > Hi, > > > > > > We have a board warping problem and are looking for a PCB expert to help > > > resolve it. > > > (Preferably located in the UK, but not important) > > > > > > When I say expert, I mean *EXPERT*. The problem is quite complex and > >already > > > has baffled two manufacturers. > > > > > > We will pay the going rate for any consultation. > > > > > > Regards, > > > > > > Jason Morgan > > > > >Mark Witherite C.I.D. >Assistant Research Engineer >Astronomy & Astrophysics >Penn State University >2565 Park Center Blvd >Suite 200 >State College, PA. 16801 >email [EMAIL PROTECTED] >telephone 814 865 9839 >fax 814 865 9100 > > Mark Witherite C.I.D. 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