Tony,

Usually with a large BGA such as this, it is sometimes preferrable to handle
all of the routing of traces in the immediate vicinity of (under the) BGA,
as part of the BGA Symbol itself.

This allows you to work out the little nuances and problems with the BGA
"escape routes" in the Component Library, while not having to worry about
making changes to the actual board and fouling up nets or having vias, and
traces always dissappearing, etc..

My Preference, is to place all of the "vias" and initial routing to the
"perimeter" of the BGA in a seperate Component Symbol all by itself, in
addition to the actual BGA Symbol. In either case, this seperate or combined
Symbol, by its very design, must have multiple layers.

This appears to be where the problem is comming in that Anand is having, in
getting the layers of the Component Symbol to properly transfer to the
layers of the PCB.

The trick is that you can place the BGA Symbol (or seperate BGA Symbol and
routing / via Symbol), and then connect it (route it) to the outside world,
and if you have any problems, you can simply update the Symbol.

In actual practice in Protel, this means placing the Symbol, and then going
to the Netlist Manager Menu and doing an "Update Free Primitives From
Component Pads", which will "propigate" the net names to the vias and trace
routing in the Symbol, and then going from there.

In reality, this may take several iterations to get everything resolved into
the design the way that you want, and then once that yoyu get to that point,
you can "release" all of the "primitives" (vias and traces) of the special
Symbol into the design using "Tools > Convert > Explode Component to Free
Primitives" (although this latter step is only necessary if you want to go
back into the routing and delete any unused segments or vias).

JaMi

----- Original Message -----
From: "Tony Karavidas" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Wednesday, October 09, 2002 4:35 PM
Subject: Re: [PEDA] question about layer synchronization between PCB and
footprint library


> The xilinx FPGA has to be mounted to the outside of the board, right?
> Then how would you have ANY layer information besides the top layer pads
> (BGA, TQFP, whatever)? What are you trying to do with layers and parts?
>
>
>
> > -----Original Message-----
> > From: Anand Kulkarni [mailto:[EMAIL PROTECTED]]
> > Sent: Wednesday, October 09, 2002 12:57 PM
> > To: PROTEL USER Group
> > Subject: [PEDA] question about layer synchronization between
> > PCB and footprint library
> >
> >
> > Hi everybody,
> >
> > I have struggled with this problem for sometime now;
> > I hope you can help me.
> >
> > I defined a PCB in Protel with 6 layers.
> > The layers were named :
> >
> > top,midlayer1,midlayer2,midlayer29,midlayer30,bottom
> >
> > by default.
> >
> > Now I also created a footprint for a xilinx FPGA part with 6
> > layers in it and named them the same as above.
> >
> > Now when I do an update of the PCB from the schematics
> > only the layers
> >  top,midlayer1,midlayer2 and bottom
> > are  copied form the footprint to the PCB ;
> > the layers
> >  midlayer29 and midlayer30
> > do not get copied ;
> >
> > I don't know what is happening ;
> >
> > I'd greatly appreciate any suggestions
> >
> > thanks and regards
> >
> > Anand Kulkarni
> >
> >
> >
> >
> >
> >
> >
> >
> > ____________________________________________________________
> > Watch a championship game with Elway or McGwire.
> > Enter Now at http://champions.lycos.com
> >

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