Hi everybody, Well, i'll explain what I am doing as follows : the xilinx part that I am trying to make this board for has 1156 balls. [ball grid array] I referred to the board routability guidelines by xilinx ,i.e application note 157 [XAPP 157] In this document they have specified the fan-out of this particular fine pitch ball grid array [FG1156.] i.e, they have given diagrams of where the vias must be placed and how each pad is routed out of the part throught vias and tracks placed on different layers.
I took the footprint provided by protel which had only top layer pads information and to this footprint I added the vias and the the tracks on the different layers that do the fan-out and thus created a new footprint.I am trying to use this new footprint in my PCB ,i.e , my in my schematic the xilinx part references this new footprint. Now,after you have raised a question I am no longer sure if this [i.e what I just described] is okay. Also,I am faced with a new problem. If I go along with what I have done so far, I cannot see the "ratsnest" after doing the "UPDATE-PCB" step. Probably this is because the tracks are buried in the different layers and their destination ,i.e the part to which these nets must connect after leaving the Xilinx FPGA balls are surface mount connectors; i.e these tracks must resurface onto the top signal layer [ using vias again ] before they can be routed to the connectors, Again am I right ? Is there a simpler way of doing what I am trying to do ? I hope you are able to help me; I'd appreciate any suggestions , thanks very much Anand Kulkarni -- On Wed, 9 Oct 2002 16:35:41 Tony Karavidas wrote: >The xilinx FPGA has to be mounted to the outside of the board, right? >Then how would you have ANY layer information besides the top layer pads >(BGA, TQFP, whatever)? What are you trying to do with layers and parts? > > > >> -----Original Message----- >> From: Anand Kulkarni [mailto:[EMAIL PROTECTED]] >> Sent: Wednesday, October 09, 2002 12:57 PM >> To: PROTEL USER Group >> Subject: [PEDA] question about layer synchronization between >> PCB and footprint library >> >> >> Hi everybody, >> >> I have struggled with this problem for sometime now; >> I hope you can help me. >> >> I defined a PCB in Protel with 6 layers. >> The layers were named : >> >> top,midlayer1,midlayer2,midlayer29,midlayer30,bottom >> >> by default. >> >> Now I also created a footprint for a xilinx FPGA part with 6 >> layers in it and named them the same as above. >> >> Now when I do an update of the PCB from the schematics >> only the layers >> top,midlayer1,midlayer2 and bottom >> are copied form the footprint to the PCB ; >> the layers >> midlayer29 and midlayer30 >> do not get copied ; >> >> I don't know what is happening ; >> >> I'd greatly appreciate any suggestions >> >> thanks and regards >> >> Anand Kulkarni >> >> >> >> >> >> >> >> >> ____________________________________________________________ >> Watch a championship game with Elway or McGwire. >> Enter Now at http://champions.lycos.com >> > ____________________________________________________________ Watch a championship game with Elway or McGwire. Enter Now at http://champions.lycos.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://email@example.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *