----- Original Message -----
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, October 11, 2002 4:29 AM
Subject: Re: [PEDA] signal integrity


> > It always says that there are warnings about my PCB, however it seems to
> > work fine when I let it continue.  I assume that these are undefined
> > integrity (IBIS or similar) libraries.
>
> Actually they are probably loops in the tracks. These loops may be under
> pads and thus hard to find.
> I ran into this on a board I was doing in P99SE and found that after it
> complained most signals would work but a few would not simulate. I later
> brought the board into DXP and DXP comlained that the signals had loops in
> them and thus could not be simulated. One loop was obvious, but others
> were under pads so hard to find without DXP pointing out the location.
> Protel explained that this was due to the agorithm using the tracks not
> the copper. I fixed the loops and SI worked great.

So I should probably get DXP back to find these kind of errors...


> > How do you define the IBIS (or protel library file) to use for each
> > component??
>
> Once you take over a net you can double click on a pin in the net and
> change the model and stimulus for that pin.

Is there a way to assign a component a whole IBIS file (ie the IBIS file for
that component includign pins etc) as opposed to just each individual pin??
I was thinking in terms of a component properties entry or similar.  ie In
the PCB or Schematic workflow...

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