I did play round with it a while ago, actually testing some of our design
centres  IBIS models to see if they converted correctly. The engineer involved
in writing the models was quite interested and the results I got when running
waveforms around 150MHz seemed to give the sort of ringing and results as would
be expected from our test boards.
The prop delays of the traces however never seem to be exactly as calculated and
if you really need accurate results you have to measure using a correctly
deskewed scope.

"Bevan Weiss" <[EMAIL PROTECTED]> on 11/10/2002 07:50:21 AM

Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>

To:   "Protel EDA Forum" <[EMAIL PROTECTED]>
cc:    (bcc: Clive Broome/sdc)

Subject:  Re: [PEDA] signal integrity

It's very easy to use, you just set up what the output device is, what the
input device is (in terms of pins) on a particular net.  You set up the
output and input device family
Then you can transmit a waveform (rising edge, falling edge, clock) down the
line.  And get the waveform at each node.

I wouldn't expect the voltage levels to be good for anything analog based,
however if dealing with a digital system (at the lower speeds where an error
in the calculations won't be catastrophic) it is very handy for a quick idea
of the min/max voltages on the line and whether you are borerline on the
threshold voltages for whatever signalling you're using.
I assume that if you used actual manufacturer's IBIS files (as opposed to
simple logic family buffers) then the accuracy would increase slightly.

I'm not too sure whether it takes into account such things as varying plane
spacing and other oddities such as via-via capacitence etc (ad nauseam).
You could test this yourself of course.  I will probably test it a little

----- Original Message -----
From: "JaMi Smith" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Cc: "JaMi Smith" <[EMAIL PROTECTED]>
Sent: Friday, October 11, 2002 9:12 AM
Subject: Re: [PEDA] signal integrity

> Robert and Bevan,
> While I have not done any playing around with Protels Signal Integrity
> capability, primarily because I haven't had the time and I know it will
> some study time to understand it's implementation and proper usage, and
> secondarily because I know that models are somehow involved which means
> have to have a model for everything involved, which usually means that you
> have to build some, and to do that properly, and make sure the ones you
> are good, you have to fully understand the models.
> Anyway, even though I do not know anything about Protels implementation, I
> have been following your posts on this thread here in the forum, and one
> thing that was stated here kind of reached out and hit me over the head
> a club sized question mark.
> If I understand what you have said regarding "loops" under "pads", it
> appears that you are actually saying that Protel (in either the 99 SE or
> incarnation) cannot distinguish that the continuity of the trace "merged
> with" (as it were) the continuity of the pad, or possibly a better way to
> put it might be that the signal trace "transitioned" into a different,
> we say conductor.
> This is a little scary to me, in that it appears that it would therefore
> making improper calculations, especially if the calculations consider that
> portion of the trace that extends under the pad as an extension or
> continuation of the same trace for that specific length (whether it be in
> addition to or in place of the characteristics of the pad itself).
> It would appear that it may be ignoring the change in conductor
> characteristics, and that from the perspective of capacitance (being
> certainly more with respect to adjacent planes) and inductance (being
> probably less), which both will effect impedance at least to the point of
> being a discontinuity, and more importantly from the perspective cross
> due to the change in environment to adjacent conductors, etc., etc..
> All of this prompts me to wonder and question whether or not Protel takes
> things that may drastically affect the characteristics of the signal
> conductor into account, such as changes in conductor width, vias, and
> transitions to different layers (with different relationships to planes
> (read distances)).
> Quite possibly I am worrying about things that appear to be trivial to
> and quite possibly I am thinking of Protels SI capability far beyond its
> intended design, but I am thinking of its usability and accuracy in terms
> a recent design which used two 16 bit LVDS controlled impedance
> data busses operating at 500 MHz between 3 large BGA's, with BGA
> packs in the middle of the whole thing.
> One of the very unfortunate side effects if using high density BGA's is
> fact that you are sometimes forced to use vias to get into or out of the
> connection array, which forces you to use these vias on a signal conductor
> that you otherwise would never dream of using a via on.
> At these speeds, and especially in a controlled impedance environment,
> kinds of things, and things like recognizing a loop under a pad that in
> reality is not even there from the electrical perspective, make me wonder
> just what the Protel (99SE/DXP) Signal Integrity capabilities really are,
> and whether or not it is even realistically usable, and therefore worth
> time to learn how to use.
> In my recent designs I have dealt with one RF Engineer who really is
> about the size and shape of the pads on the components of a 1 GHz
> synthesizer, down to the point of the direction that the trace has to
> the pad, and with another RF Engineer who wants to use 20 mil controlled
> impedance traces which go directly into the pads of an 0402 component
> without any width transitions, which also have the ground plane cleared
> under the component to compensate for the capacitance introduced by the
> of the component itself (this is in a 2.75 GHz RF / Fiber Optic design).
> These are the types of things that I am dealing with that prompt me to ask
> the kinds of questions I am asking.
> From your guys experience and familiarity with Protels SI capability, am I
> just worrying over minutiae, or stuff that doesn't really even enter into
> the picture, or am I thinking way over Protels (99SE/DXP) capability.
> Another question that I have about Protels SI capabilities, is whether or
> not, when it models traces that are over a ground (or other) plane, does
> simulate a solid (imaginary) ground plane, or does it take into account
> actual topography of the actual ground under the trace, including any gaps
> or splits due to clusters of vias or thru hole component pins, or things
> such as thermal reliefs. Actually, for that matter, does it deal with the
> real topography of the trace itself, or does it just simulate a trace of x
> length and y width and let it go at that.
> Thanks,
> JaMi
> ----- Original Message -----
> To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> Sent: Thursday, October 10, 2002 9:52 AM
> Subject: Re: [PEDA] signal integrity
> > >> the copper. I fixed the loops and SI worked great.
> > >
> > > So I should probably get DXP back to find these kind of errors...
> > >
> >
> > Well it does do a bit better job at it, and from the sounds of it the
> > first Service pack will fix almost all the issues and requests for
> > improvements.
> >
> >
> > >> Once you take over a net you can double click on a pin in the net and
> > >> change the model and stimulus for that pin.
> > >
> > > Is there a way to assign a component a whole IBIS file (ie the IBIS
> > for
> > > that component includign pins etc) as opposed to just each individual
> > pin??
> > > I was thinking in terms of a component properties entry or similar.
> > In
> > > the PCB or Schematic workflow...
> >
> > This is another area where DXP improved things. It is much easier to
> > assign models to a component and they stay with it since you assign them
> > while creating an integrated library.
> >
> > I have noticed with 99SE that once you assign a model to one pin the
> > pins of that type get most of the fields from that one. Unfortunately
> > all the fields carry over.
> >
> > Robert D. LaMoreaux

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