do you really mean '2.4mm rout'
not '2.54mm route' ?

not trying to be a ball buster here but i have been thinking about this
dimension lately

here in the land of Feet and Pounds some of my fabricators like 0.093
router bits since that is a fractional inch dimension

this is of course a pain for design, so we draw everything at 0.100" and
they either joggle the bit or use an actual 0.100 bit

anyway, i have been thinking about going to 0.050 router bit width
do you have any comments on the ups and downs of that?

are the router bits too thin and breakable or whatever ?
(062 thick bds)

i have a board where it would actually save an appreciable amount of

also regarding your breakaway holes
we have been fiddling with those for some time 
(the size, count and arrangement)
but we always seem to get little 'tits' where the breakaway occurs
these are small sharp protrusions that in some cases need to be cleaned

i see that you (Ian) use .029 holes
we use holes more like 0.020 - 0.022 spaced pretty close
(else the little plating barrels can be an electrical hazard as they

also on a related topic
anyone have a feel for a reasonable design tolerance for the location of
V grooves?
i know they are a bit sloppier than routing
but they are attractive in certain cases

Dennis Saputelli

Ian Wilson wrote:
> On 06:28 PM 14/03/2003, Z Hylton said:
> >I need some help.
> >
> >I am panelizing a number of small boards, (5 caps, two SOP16 packages). I'm
> >using DXP and when I copy the second board, all the designator's names are
> >changed. C1 becomes C1_1, ...the third board has designator's changed from
> >C1 to C1_2... and so on.
> >
> >Does anyone know how to turn this feature off? Or maybe it's best to move
> >everything back to 99SE once again and do the work there?
> What I usually do is design just one board but lay up the full panel
> (including tooling strips, routs (and breakoff tabs) or v-grooves,
> etc).  So my mech layer 1 (renamed Board Outline) is a complex thing
> showing 2.4mm routs and break off strips if I am routing the panel, or
> lines crossing right across the panel (and tooling strips) if I am
> v-grooving.  (In the case of a routed board with break off tabs, I place
> all the breakoff holes on all tabs - I then make a note to the PCB maker
> that the break off holes and Mech Layer 1 and possibly some dimension
> layers etc are not to be stepped and repeated, while everything else should
> be.  The breakoff holes are easily identifiable, they are the only 0.75mm
> unplated holes on the board).
> I fully dimension the step and repeat and then get the PCB maker to do the
> actual step and repeat.  This works very well and I always have a fully
> checkable design.
> This works a treat for me.  (BTW - I set the DXP board shape to just the
> size of my single board, not the full panel.  DXP users will know what I mean.)
> (This method does not work when you are trying to panelise multiple
> different boards - in this case I would probably use the Camtastic method.)
> Alternatively, use Camtastic to do the panelising.  This is available in DXP.
> The problem with panelisation in a CAE pkg is the problem of having two
> files to maintain - the individual PCB and the panel.  In a fully panelised
> design, the panel is not really an editable files.  I gave up on this some
> time ago as it was always tiresome and subject to risk. But if you really
> have to panelise in DXP use the same technique you have to use in P99SE,
> that is Paste Special then check the "Duplicate designator" and possibly
> "Keep net name".
> There is a forum specifically targeting DXP users.  It has lots of traffic
> and lots of Altium involvement.
> Good luck,
> Ian Wilson

Dennis Saputelli

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