I have been going over this for the better part of the day now, and cannot find the solution.

On the processor schematic I have the busses [COL0..COL2] and [R\O\W\0..R\O\W\7] with pullups on COL0..COL2. The COL bus is connected to an input port, the ROW bus to an output port. All busses and ports are properly named and labelled.

One sheet up, the peripheral schematic, I have a sheet symbol with a sheet entry (type: input) called [COL0..COL2] connected to a connector, some capacitors and some diodes.
Another sheet entry (type: output) called [R\O\W\0..R\O\W\7] connects to the other side of the diodes and that same connector. Again, all items named and labelled as they should be.

ERC finds no other errors than multiple lables on some other nets, all there on purpose.

When I run 'Update PCB' with the connectivity set to 'Sheet Symbol / Port Connections' no errors are reported, but on the PCB I get two nets COL0, two nets COL1 etc. One net is exactly what is on the processor schematic, the other net is exactly what is on the peripheral schematic.
All other nets (including data and address bus) connect fine....
The same thing happens when I run 'Create Netlist'.

I can get the connectivity correct by stating 'Net Labels and Ports Global' but that should not be necessary: I did another project with nested sheets and that went fine.

Surely I miss something so obvious that it will be embarassing to learn what it is, but I haven't been able to figure it out on my own for the past six hours.....

Would any of you gentlemen be prepared to share his thoughts over this and get this project back on track (no pun intended)?

Leo Potjewijd hardware designer IE Keyprocessor bv.

+31 20 4620700

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