At 04:24 PM 27/11/2003 +0100, you wrote:
HELP!

I have been going over this for the better part of the day now, and cannot find the solution.

On the processor schematic I have the busses [COL0..COL2] and [R\O\W\0..R\O\W\7] with pullups on COL0..COL2. The COL bus is connected to an input port, the ROW bus to an output port. All busses and ports are properly named and labelled.

One sheet up, the peripheral schematic, I have a sheet symbol with a sheet entry (type: input) called [COL0..COL2] connected to a connector, some capacitors and some diodes.
Another sheet entry (type: output) called [R\O\W\0..R\O\W\7] connects to the other side of the diodes and that same connector. Again, all items named and labelled as they should be.

Leo,


Protel applications use a bus format like COL[0..2] - that is only the bus indexes are in the brackets. If you rework the bus net labels and sheet entries to this form does it help?

Ian Wilson



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