Could you just elaborate a little on
The automatic generation of the *entire* FPGA's schematic sheet,
drawing all the wires, assigning nets to the wires, creating
the off sheet ports, creating the pin constraints file, and the FPGA pin
assignments can be passed down to the PCB automagically. It's all really very nice.
I assume that the schematic sheet that is created is simply a block with all the I/Os brought out as named nets? i.e. it doesn't attempt to interpret your VHDL and produce a schematic representation of your code?
I'm not arguing, just trying to see where the big benefit is. Right now I use the Xilinx software, and most design entry is via their schematic editor (crappy as it is!)and as little as possible in plain VHDL. Constraint entry is done on the schematic. Granted that I have to manually create a library entry with pin names and numbers in Protel, and I have to edit that every time I change something in the design, I agree that it would be nice to have it done automatically, but... am I missing something more?
For me, as a non-vhdl sort of person, NEXAR allows me to design and probe my FPGA design as if it is a bit of hardware on the bench. So without needing to know VHDL you can do quite elaborate designs and you can use instruments like logic analysers, digital I/O etc to probe much as you would on the bench - these instruments use resources inside the FPGA, but assuming you have the spare resources you get a hardware engineers sort of view of your FPGA design.
I have not done enough with FPGA to be able to comment on whether a front-end tool like Nexar is better or worse than the vendor tools (Nexar does need the vendor tools for place and fit), but the following things come to mind on the plus side for Nexar - some of which I am sure the vendor tools have as well:
1) The royalty free IP, if you have the Nexar product you get Z80, PIC and 8051 style clones with the dev tools (Tasking). The non-Nexar version, get the instruments (logic analyser, digital I/O etc)
2) You get access to royalty free TCP/IP code, I think - check this out with Altium though, there is KB item about this.
3) The instruments work well - they allowed me, as an not-very-experienced FPGA designer, to quickly knock up the PortSwitcher reference design. I wrote the internal processor code and exercised all the PortSwitching muxes without waiting for the PCB, also I did not need to reserve FPGA pins to allow me to bring out internal nodes for debugging ( I used them all to allow the design to be able to switch LPT-style parallel ports (not many/if any pins spare). Leaving the PCB until late in the design reduced risk.
4) The Sch editor is much better than the vendor tools from what I can see.
5) The integration is OK, but we have all worked with disparate tools successfully for some time now. It was quite nice using the one tool for FPGA Sch, PCB Sch, Code, Debugging (code and FPGA).
6) The code editor is not too bad, not as good as dedicated programmers editors or even some other IDEs but certainly *much* better than many.
The business of being able to switch device or vendor is not really a big selling point to me as I would generally imagine that a device family has been pretty well selected by appropriate engineering analysis before the design is really underway. It is for me anyway.
Things against Nexar - I am sure there are many. Limited support apart from Altera and Xilinx - hopefully this will change. Dealing with the constraint files is text based - can be a pain. Maybe there will be integration problems in the future as new vendor tools come and old one go, dunno. If you use the Altium IP will it be as well tested as similar vendor IP (it might be but it may not be, another dunno). The logic analyser instrument may have some limitations compared to an external LA - I am sure but I have not used the Nexar LA instrument a great deal. Again due to lack of experience I don't know for sure, but it may be a little harder to get to the vendors nitty-gritty settings when you need to in those odd situations where you have to tweak something unusual.
BTW there is a design error in the PortSwitcher PCB. The JTAG interface is a bit screwy.
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