In all of my fabrication notes I include a note from to the board manufacture that 
basically says:  BOW AND TWIST SHALL NOT EXCEED THE REQUIREMENTS AS OUTLINED IN IPC 
6012 SECTION 3.4.4 AND  AS MEASURED IN ACCORCDANCE WITH IPC TM650 METHOD 2.4.2

A second note I add is:   LAYER STACK UP ORDER MAY NOT BE ADJUSTED BY THE FABRICATOR.

Mr. Dennis Saputelli is correct, there are many factors that will contribute to 
warpage, aspect ratio of the design, part location, copper distribution and layer 
stack.  Since I specifically outline my requirements, most board houses will call me 
to inform me that my stack up sucks according to their manufacturing.  So I have to 
make a decision... a little bit of warpage vs controlled impedance and/ or EMI 
protection.  I will opt for meeting electrical requirements. 
I believe the acceptable warpage comes out to about .007 inch per inch. (someone feel 
free to correct me if I am wrong)  On a 10 inch board this translates to potato chip 
as acceptable.  So just looking at the board may not be enough criteria to reject the 
board.  Second if the boards are warped a little....who cares if it isn't creating an 
immediate problem with solderabilty. Application of heat is what I call distructive 
testing. I would look closely at the IPC spec,  the boards may be acceptable according 
to the IPC leve of accepatbilty

Mike Reagan
EDSI



* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/[EMAIL PROTECTED]
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to