Oh well, if Peter Graf can upgrade my Q68 to v1.05 in May I might be
able to do more research...
Please remind me prior to the QL meeting so I bring the equipment and
FPGA data.
I might be able to get a second hand FPGA programmer for cheap, I'll let
you know when I get it.
As I wrote at several occasions, it turned out to make a difference on
which operating system I had synthesized FPGA version 1.05. If
synthesized under Windows 10, there was a stability problem that Martyn
could reproduce. If synthesized under Windows XP, everything should be
allright. Unfortunately, I never suspected such a problem with the FPGA
toolchain, and it is now not traceable. Very unlucky.
I've discussed this with Mark, his Q68 was not affected by this.
Dilwyn Jones via Ql-Users wrote:
Mind you, my Q68 has never been able to run Jan's Minerva port either.
If the latest Minerva and/or returning to FPGA version 1.02 does not
help, I would suspect an actual hardware problem and your Q68 should be
replaced.
I'm not sure whether the latest Minerva port will solve all problems.
Mark and I managed to pinpoint some issues but so far we haven't been
able to solve it completely.
One point of interest remains the interrupt register at $18021. I know
about the frame and external interrupt bits (3 and 4, respectively)
which are emulated from a BBQL. The other bits are irrelevant to Minerva
(in fact only bit 3 is checked for a frame interrupt call, else it
treats it as external interrupt since early Q68s don't set bit 4).
But does writing to this register have any effect? The only purpose
would be to clear the respective interrupt by setting bit 3 or 4 (which
Minerva does). Bits 0-2 and 5-7 were used for gap, IPC, and transmit
interrupts respectively, which are irrelevant to the Q68 and should
really be ignored. Minerva doesn't set these bits except when
initialising the hardware.
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