On (10 Feb 95) [EMAIL PROTECTED] wrote... s> From: Simon Cooke <[EMAIL PROTECTED]> s> Date: Fri, 10 Feb 1995 12:58:47 +0000 (GMT)
s> And as soon as we can get hold of that damned 20MHz Z80, we'll build one s> too... Have you tried STC head office at Harlow 01279 626 777 original Type No. Z84C0020PEC Stock No. 034275F from 1991 catalogue the price was listed as P.O.A. they may still stock it, I don't know... s> the only problem I can see is the Dynamic RAM refresh circuitry. Anyone s> know any reference text that's perfect for the job? How about using DRAMS that support /CAS before /RAS internal refresh address counters? Text from a 256k by 1 DRAM data 'sheet':- "Refresh row addresses can be supplied from an internal row address counter. Thereby the need is eliminated for external refresh circuitry to provide and increment the refresh addresses. The internal refresh function is implemented by asserting /CAS prior to driving /RAS active. This will cause the internal refresh counter to provide a row address to the memory row decoder input, thereby refreshing that row. At the end of that cycle, the internal counter will be automatically incremented by one to prepare for refreshing the next row. During /CAS (before /RAS refresh), all external address inputs are ignored." >From the above one would simply use z80 /RFSH line to cause a global /CAS before /RAS access on all such DRAMS and they'd all be refreshed internally, totally ignoring the 7bit /RAS address the z80 provides:-) Johnathan. -- |Fidonet: Johnathan Taylor 2:2501/307.9 |Internet: [EMAIL PROTECTED] | | Standard disclaimer: The views of this user are strictly his own.
