[gem5-dev] Change in gem5/gem5[develop]: sim: Add checkpoint parameters for VMA list

[Ian Jiang (Gerrit) via gem5-dev]

Ian Jiang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31875 )


Change subject: sim: Add checkpoint parameters for VMA list
..

sim: Add checkpoint parameters for VMA list

Add checkpoint parameters (together with corresponding serialization
and unserialization) for VMA list of class MemState into a separate
section named 'vmalist'.

Without these VMA list parameters, a page table fault will occur when
running with --restore-simpoint-checkpoint, because of an empty VMA
list. For example:

  $ ./build/RISCV/gem5.debug --debug-flags=Exec configs/example/se.py \
  -c tests/test-progs/hello/bin/riscv/linux/hello \
  --cpu-type=NonCachingSimpleCPU --restore-simpoint-checkpoint \
  --checkpoint-dir m5out/ -r 2
  ...
  2404000: system.switch_cpus: T0 : @_int_malloc+3392: sd a5, 8(a0) \
  : MemWrite :  D=0x0001ed21 A=0x862e8
  panic: Page table fault when accessing virtual address 0x862e8
  ...

Example checkpoint output:

  [system.cpu.workload.vmalist]
  size=3

  [system.cpu.workload.vmalist.Vma0]
  name=stack
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma1]
  name=heap
  addrRangeStart=...
  addrRangeEnd=...

  [system.cpu.workload.vmalist.Vma2]
  ...

Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Signed-off-by: Ian Jiang 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31875
Reviewed-by: Daniel Carvalho 
Reviewed-by: Bobby R. Bruce 
Reviewed-by: Alexandru Duțu 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/mem_state.hh
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  Alexandru Duțu: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index 1ca80da..c052389 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -190,7 +190,18 @@
 paramOut(cp, "stackMin", _stackMin);
 paramOut(cp, "nextThreadStackBase", _nextThreadStackBase);
 paramOut(cp, "mmapEnd", _mmapEnd);
+
+ScopedCheckpointSection sec(cp, "vmalist");
+paramOut(cp, "size", _vmaList.size());
+int count = 0;
+for (auto vma : _vmaList) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", count++));
+paramOut(cp, "name", vma.getName());
+paramOut(cp, "addrRangeStart", vma.start());
+paramOut(cp, "addrRangeEnd", vma.end());
+}
 }
+
 void
 unserialize(CheckpointIn ) override
 {
@@ -201,6 +212,20 @@
 paramIn(cp, "stackMin", _stackMin);
 paramIn(cp, "nextThreadStackBase", _nextThreadStackBase);
 paramIn(cp, "mmapEnd", _mmapEnd);
+
+int count;
+ScopedCheckpointSection sec(cp, "vmalist");
+paramIn(cp, "size", count);
+for (int i = 0; i < count; ++i) {
+ScopedCheckpointSection sec(cp, csprintf("Vma%d", i));
+std::string name;
+Addr start;
+Addr end;
+paramIn(cp, "name", name);
+paramIn(cp, "addrRangeStart", start);
+paramIn(cp, "addrRangeEnd", end);
+_vmaList.emplace_back(AddrRange(start, end), _pageBytes, name);
+}
 }

 /**

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2fa7ad2c34fe667ce95bc4b10a1affcf60d9c1f
Gerrit-Change-Number: 31875
Gerrit-PatchSet: 3
Gerrit-Owner: Ian Jiang 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Ian Jiang 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Possible race condition (Remote GDB)

[Boris Shingarov via gem5-dev]

It gets worse: I am beginning to suspect that this race is what ultimately 
causes the "xml for the wrong xlen" mystery (if the timing is unlucky, the CSPR 
isn't set yet).

-"Boris Shingarov via gem5-dev"  wrote: -
To: gem5-dev@gem5.org
From: "Boris Shingarov via gem5-dev" 
Date: 08/06/2020 08:14PM
Cc: "Boris Shingarov" 
Subject: [gem5-dev] Possible race condition (Remote GDB)

It looks to me that there is a race condition inherent in the design of 
DataEvent.
The effect is that, even when CPU.wait_for_gdb attr is set and after the the 
RSP socket has connected, the relative timing of gdb's vs gem5's execution may 
or may not lead to gdb's presence being ignored.  It's like "hey gdb,I know you 
already connected, but if you aren't quick enough that the qSupported reaches 
the queue within N ms after connecting, I am going ahead without you; (and no I 
am not telling you what N is)".

It looks like one fundamental issue here is the historical packet-oriented 
nature of RSP.  But it also looks like remote_gdb.cc:434,

if (!active) {
active = true;
} else {
// Tell remote host that an exception has occurred.
send(csprintf("S%02x", type).c_str());
}

plays a central role.
Can someone comment on how this is intended to work?  I must admit the comment 
above that code doesn't make sense to me.
 
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[gem5-dev] Possible race condition (Remote GDB)

[Boris Shingarov via gem5-dev]

It looks to me that there is a race condition inherent in the design of 
DataEvent.
The effect is that, even when CPU.wait_for_gdb attr is set and after the the 
RSP socket has connected, the relative timing of gdb's vs gem5's execution may 
or may not lead to gdb's resece being ignored.  It's like "hey gdb,I know you 
already connected, but if you aren't quick enough that the qSupported reaches 
the queue within N ms after connecting, I am going ahead without you; (and no I 
am not telling you what N is)".

It looks like one fundamental issue here is the historical packet-oriented 
nature of RSP.  But it also looks like remote_gdb.cc:434,

if (!active) {
active = true;
} else {
// Tell remote host that an exception has occurred.
send(csprintf("S%02x", type).c_str());
}

plays a central role.
Can someone comment on how this is intended to work?  I must admit the comment 
above that code doesn't make sense to me.
 
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[gem5-dev] Change in gem5/gem5[develop]: python: Import reduce function in FileSystemConfig

[Jason Lowe-Power (Gerrit) via gem5-dev]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32374 )



Change subject: python: Import reduce function in FileSystemConfig
..

python: Import reduce function in FileSystemConfig

Not sure if this is required due to python3 or something else, but I got
the error "NameError: name 'reduce' is not defined". This fixes that
error.

Change-Id: I2dd71674306abcad1a90311664b18b9eee29b9ac
Signed-off-by: Jason Lowe-Power 
---
M configs/common/FileSystemConfig.py
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/configs/common/FileSystemConfig.py  
b/configs/common/FileSystemConfig.py

index ec27656..29041fd 100644
--- a/configs/common/FileSystemConfig.py
+++ b/configs/common/FileSystemConfig.py
@@ -42,6 +42,7 @@
 from m5.objects import *
 from m5.util.convert import *

+from functools import reduce
 import operator, os, platform, getpass
 from os import mkdir, makedirs, getpid, listdir, stat, access
 from pwd import getpwuid

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Gerrit-Change-Id: I2dd71674306abcad1a90311664b18b9eee29b9ac
Gerrit-Change-Number: 32374
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Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove remnants of /dev/shm mapping from apu_se

[Kyle Roarty (Gerrit) via gem5-dev]

Kyle Roarty has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32354 )



Change subject: configs: Remove remnants of /dev/shm mapping from apu_se
..

configs: Remove remnants of /dev/shm mapping from apu_se

Change-Id: Iec2598c715223d079bc5dfd2ea52859945706cfc
---
M configs/example/apu_se.py
1 file changed, 0 insertions(+), 5 deletions(-)



diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 82e4022..3c532c4 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -623,9 +623,6 @@
dests = ["%s/fs/sys"  % m5.options.outdir]),
   RedirectPath(src = "/tmp",
dests = ["%s/fs/tmp"  % m5.options.outdir]),
-  RedirectPath(src = "/dev/shm",
-   dests = ["/dev/shm/%s/gem5_%s"  %
-   (getpass.getuser(), os.getpid())])]

 system.redirect_paths = redirect_paths

@@ -681,6 +678,4 @@
 print("Ticks:", m5.curTick())
 print('Exiting because ', exit_event.getCause())

-FileSystemConfig.cleanup_filesystem(options)
-
 sys.exit(exit_event.getCode())

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[gem5-dev] A question about setting the memory access latency of some stores to zero in Minor CPU model

[Jianping Zeng via gem5-dev]

Hello,

I am working on a research project and need to dynamically set the memory
access latency of some store instructions to 0 on a simulated gem5 Minor
CPU+NVMain without cache. I have no idea where I should start to modify
the code. Is there someone who might help me with this?
Thanks,
Jianping.
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Adding FS support for MOESI_AMD_Base

[Pouya Fotouhi (Gerrit) via gem5-dev]

Pouya Fotouhi has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32317 )



Change subject: mem-ruby: Adding FS support for MOESI_AMD_Base
..

mem-ruby: Adding FS support for MOESI_AMD_Base

WIP

Change-Id: Ic424cc6e78399e9cd73d6419ea0ad6f8c9397673
---
M configs/ruby/MOESI_AMD_Base.py
M src/mem/ruby/protocol/MOESI_AMD_Base.slicc
2 files changed, 56 insertions(+), 3 deletions(-)



diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 91ff4d2..ae17031 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -260,6 +260,12 @@
 dir_cntrl.create(options, dir_ranges, ruby_system, system)

 # Connect the Directory controller to the ruby network
+dir_cntrl.requestFromDMA = MessageBuffer(ordered = True)
+dir_cntrl.requestFromDMA.slave = ruby_system.network.master
+
+dir_cntrl.responseToDMA = MessageBuffer()
+dir_cntrl.responseToDMA.master = ruby_system.network.slave
+
 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
 dir_cntrl.requestFromCores.slave = ruby_system.network.master

@@ -290,7 +296,7 @@
 # level config files, such as the ruby_random_tester, will get  
confused if
 # the number of cpus does not equal the number of sequencers.  Thus  
make

 # sure that an even number of cpus is specified.
-assert((options.num_cpus % 2) == 0)
+#assert((options.num_cpus % 2) == 0)

 # For an odd number of CPUs, still create the right number of  
controllers

 cpuCluster = Cluster(extBW = 512, intBW = 512)  # 1 TB/s
@@ -378,8 +384,54 @@
 cpus = [n for n in
 range(options.num_cpus)])

-# Assuming no DMA devices
-assert(len(dma_devices) == 0)
+### Assuming no DMA devices
+##assert(len(dma_devices) == 0)
+##dma_cntrl_nodes = []
+
+for i, dma_port in enumerate(dma_devices):
+# Create the Ruby objects associated with the dma controller
+dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
+   slave = dma_port)
+
+dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
+   transitions_per_cycle = options.ports,
+   ruby_system = ruby_system)
+
+exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+#dma_cntrl_nodes.append(dma_cntrl)
+
+# Connect the dma controller to the network
+dma_cntrl.mandatoryQueue = MessageBuffer()
+dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
+dma_cntrl.responseFromDir.slave = ruby_system.network.master
+dma_cntrl.requestToDir = MessageBuffer()
+dma_cntrl.requestToDir.master = ruby_system.network.slave
+
+mainCluster.add(dma_cntrl)
+
+# Create the io controller and the sequencer
+if full_system:
+io_seq = DMASequencer(version = len(dma_devices),
+  ruby_system = ruby_system)
+ruby_system._io_port = io_seq
+io_controller = DMA_Controller(version = len(dma_devices),
+   dma_sequencer = io_seq,
+   ruby_system = ruby_system)
+ruby_system.io_controller = io_controller
+
+# Connect the dma controller to the network
+io_controller.mandatoryQueue = MessageBuffer()
+io_controller.responseFromDir = MessageBuffer(ordered = True)
+io_controller.responseFromDir.slave = ruby_system.network.master
+io_controller.requestToDir = MessageBuffer()
+io_controller.requestToDir.master = ruby_system.network.slave
+
+#dma_cntrl_nodes.append(io_controller)
+mainCluster.add(io_controller)
+
+
+#mainCluster.add(dma_cntrl_nodes)
+

 # Add cpu/gpu clusters to main cluster
 mainCluster.add(cpuCluster)
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc  
b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc

index b381452..dd4b0fc 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
@@ -4,3 +4,4 @@
 include "MOESI_AMD_Base-CorePair.sm";
 include "MOESI_AMD_Base-L3cache.sm";
 include "MOESI_AMD_Base-dir.sm";
+include "MOESI_AMD_Base-dma.sm";

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[gem5-dev] Change in gem5/gem5[develop]: mem: Update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32314 )



Change subject: mem: Update port terminology
..

mem: Update port terminology

Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
---
M src/mem/AddrMapper.py
M src/mem/Bridge.py
M src/mem/CommMonitor.py
M src/mem/ExternalMaster.py
M src/mem/MemChecker.py
M src/mem/MemDelay.py
M src/mem/SerialLink.py
M src/mem/XBar.py
M src/mem/addr_mapper.hh
M src/mem/bridge.cc
M src/mem/bridge.hh
M src/mem/cache/Cache.py
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/comm_monitor.hh
M src/mem/external_master.hh
M src/mem/hmc_controller.cc
M src/mem/mem_checker_monitor.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/packet_queue.cc
M src/mem/packet_queue.hh
M src/mem/port_proxy.hh
M src/mem/qos/QoSMemSinkCtrl.py
M src/mem/qport.hh
M src/mem/ruby/network/MessageBuffer.py
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
M src/mem/ruby/system/Sequencer.py
M src/mem/serial_link.cc
M src/mem/serial_link.hh
M src/mem/snoop_filter.cc
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/token_port.hh
M src/mem/xbar.cc
M src/mem/xbar.hh
41 files changed, 155 insertions(+), 153 deletions(-)



diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index 1e8dfea..52d7ef8 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -48,8 +48,8 @@
 abstract = True

 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")


 # Range address mapper that maps a set of original ranges to a set of
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 95caa0c..a89e7f9 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -42,8 +42,8 @@
 class Bridge(ClockedObject):
 type = 'Bridge'
 cxx_header = "mem/bridge.hh"
-slave = SlavePort('Slave port')
-master = MasterPort('Master port')
+slave = ResponsePort('Slave port')
+master = RequestPort('Master port')
 req_size = Param.Unsigned(16, "The number of requests to buffer")
 resp_size = Param.Unsigned(16, "The number of responses to buffer")
 delay = Param.Latency('0ns', "The latency of this bridge")
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index b1229c7..0fd884d 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -47,8 +47,8 @@
 system = Param.System(Parent.any, "System that the monitor belongs  
to.")


 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")

 # control the sample period window length of this monitor
 sample_period = Param.Clock("1ms", "Sample period for histograms")
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index bcc3836..6d8b5df 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -41,7 +41,7 @@
 type = 'ExternalMaster'
 cxx_header = "mem/external_master.hh"

-port = MasterPort("Master port")
+port = RequestPort("Master port")

 port_type = Param.String('stub', 'Registered external port handler'
 ' to pass this port to in instantiation')
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 0671962..714ea79 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -46,10 +46,10 @@
 cxx_header = "mem/mem_checker_monitor.hh"

 # one port in each direction
-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
-cpu_side = SlavePort("Alias for slave")
-mem_side = MasterPort("Alias for master")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")
+cpu_side = ResponsePort("Alias for slave")
+mem_side = RequestPort("Alias for master")
 warn_only = Param.Bool(False, "Warn about violations only")
 memchecker = Param.MemChecker("Instance shared with other monitors")

diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index fdc0350..7ffb608 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -41,8 +41,8 @@
 cxx_header = 'mem/mem_delay.hh'
 abstract = True

-master = MasterPort("Master port")
-slave = SlavePort("Slave port")
+master = RequestPort("Master port")
+slave = ResponsePort("Slave port")

 class SimpleMemDelay(MemDelay):
 type = 'SimpleMemDelay'
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index 254c623..2174bc7 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -46,8 +46,8 @@
 class SerialLink(ClockedObject):
 type = 'SerialLink'
 cxx_header = 

[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32310

to review the following change.


Change subject: learning-gem5: update port terminology
..

learning-gem5: update port terminology

Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
---
M src/learning_gem5/part2/SimpleCache.py
M src/learning_gem5/part2/SimpleMemobj.py
M src/learning_gem5/part2/simple_cache.hh
M src/learning_gem5/part2/simple_memobj.hh
4 files changed, 22 insertions(+), 22 deletions(-)



diff --git a/src/learning_gem5/part2/SimpleCache.py  
b/src/learning_gem5/part2/SimpleCache.py

index bd5ebfc..40892b5 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -36,7 +36,7 @@
 # Vector port example. Both the instruction and data ports connect to  
this

 # port which is automatically split out into two ports.
 cpu_side = VectorSlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+mem_side = RequestPort("Memory side port, sends requests")

 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

diff --git a/src/learning_gem5/part2/SimpleMemobj.py  
b/src/learning_gem5/part2/SimpleMemobj.py

index aee81c4..b72ebe2 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -32,6 +32,6 @@
 type = 'SimpleMemobj'
 cxx_header = "learning_gem5/part2/simple_memobj.hh"

-inst_port = SlavePort("CPU side port, receives requests")
-data_port = SlavePort("CPU side port, receives requests")
-mem_side = MasterPort("Memory side port, sends requests")
+inst_port = ResponsePort("CPU side port, receives requests")
+data_port = ResponsePort("CPU side port, receives requests")
+mem_side = RequestPort("Memory side port, sends requests")
diff --git a/src/learning_gem5/part2/simple_cache.hh  
b/src/learning_gem5/part2/simple_cache.hh

index dbc128b..4e57c87 100644
--- a/src/learning_gem5/part2/simple_cache.hh
+++ b/src/learning_gem5/part2/simple_cache.hh
@@ -51,7 +51,7 @@
  * Port on the CPU-side that receives requests.
  * Mostly just forwards requests to the cache (owner)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// Since this is a vector port, need to know what number this one  
is

@@ -71,7 +71,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
-SlavePort(name, owner), id(id), owner(owner), needRetry(false),
+ResponsePort(name, owner), id(id), owner(owner),  
needRetry(false),

 blockedPacket(nullptr)
 { }

@@ -137,7 +137,7 @@
  * Port on the memory-side that receives responses.
  * Mostly just forwards requests to the cache (owner)
  */
-class MemSidePort : public MasterPort
+class MemSidePort : public RequestPort
 {
   private:
 /// The object that owns this object (SimpleCache)
@@ -151,7 +151,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 MemSidePort(const std::string& name, SimpleCache *owner) :
-MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
+RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
 { }

 /**
diff --git a/src/learning_gem5/part2/simple_memobj.hh  
b/src/learning_gem5/part2/simple_memobj.hh

index b7c57ca..11a4b36 100644
--- a/src/learning_gem5/part2/simple_memobj.hh
+++ b/src/learning_gem5/part2/simple_memobj.hh
@@ -48,7 +48,7 @@
  * Mostly just forwards requests to the owner.
  * Part of a vector of ports. One for each CPU port (e.g., data, inst)
  */
-class CPUSidePort : public SlavePort
+class CPUSidePort : public ResponsePort
 {
   private:
 /// The object that owns this object (SimpleMemobj)
@@ -65,7 +65,7 @@
  * Constructor. Just calls the superclass constructor.
  */
 CPUSidePort(const std::string& name, SimpleMemobj *owner) :
-SlavePort(name, owner), owner(owner), needRetry(false),
+ResponsePort(name, owner), owner(owner), needRetry(false),
 blockedPacket(nullptr)
 { }

@@ -79,7 +79,7 @@

 /**
  * Get a list of the non-overlapping address ranges the owner is
- * responsible for. All slave ports must override this function
+ * responsible for. All response ports must override this function
  * and return a populated list with at least one item.
  *
  * @return a list of ranges responded to
@@ -94,14 +94,14 @@

   protected:
 /**
- * Receive an atomic request packet from the master port.
+ * Receive an 

[gem5-dev] Change in gem5/gem5[develop]: cpu: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32312

to review the following change.


Change subject: cpu: update port terminology
..

cpu: update port terminology

Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9
---
M src/cpu/BaseCPU.py
M src/cpu/base.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/kvm/base.hh
M src/cpu/minor/cpu.hh
M src/cpu/o3/fetch.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/noncaching.cc
M src/cpu/simple/noncaching.hh
M src/cpu/simple/timing.hh
M src/cpu/testers/directedtest/InvalidateGenerator.cc
M src/cpu/testers/directedtest/RubyDirectedTester.cc
M src/cpu/testers/directedtest/RubyDirectedTester.hh
M src/cpu/testers/directedtest/SeriesRequestGenerator.cc
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
M src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
M src/cpu/testers/memtest/MemTest.py
M src/cpu/testers/memtest/memtest.hh
M src/cpu/testers/rubytest/Check.cc
M src/cpu/testers/rubytest/RubyTester.cc
M src/cpu/testers/rubytest/RubyTester.hh
M src/cpu/testers/traffic_gen/BaseTrafficGen.py
M src/cpu/testers/traffic_gen/base.hh
M src/cpu/trace/trace_cpu.hh
29 files changed, 67 insertions(+), 67 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e487cbb..5d47f4c 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -177,8 +177,8 @@

 tracer = Param.InstTracer(default_tracer, "Instruction tracer")

-icache_port = MasterPort("Instruction Port")
-dcache_port = MasterPort("Data Port")
+icache_port = RequestPort("Instruction Port")
+dcache_port = RequestPort("Data Port")
 _cached_ports = ['icache_port', 'dcache_port']

 if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b9456a9..51dd6be 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -163,7 +163,7 @@
 virtual PortProxy::SendFunctionalFunc
 getSendFunctional()
 {
-auto port = dynamic_cast(());
+auto port = dynamic_cast(());
 assert(port);
 return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 }
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index d9d6d7e..b016938 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -113,13 +113,13 @@
 }

 void
-CheckerCPU::setIcachePort(MasterPort *icache_port)
+CheckerCPU::setIcachePort(RequestPort *icache_port)
 {
 icachePort = icache_port;
 }

 void
-CheckerCPU::setDcachePort(MasterPort *dcache_port)
+CheckerCPU::setDcachePort(RequestPort *dcache_port)
 {
 dcachePort = dcache_port;
 }
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 6bd7022..3c04064 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -99,9 +99,9 @@

 void setSystem(System *system);

-void setIcachePort(MasterPort *icache_port);
+void setIcachePort(RequestPort *icache_port);

-void setDcachePort(MasterPort *dcache_port);
+void setDcachePort(RequestPort *dcache_port);

 Port &
 getDataPort() override
@@ -127,8 +127,8 @@

 System *systemPtr;

-MasterPort *icachePort;
-MasterPort *dcachePort;
+RequestPort *icachePort;
+RequestPort *dcachePort;

 ThreadContext *tc;

diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index eff7a3c..e999499 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -572,15 +572,15 @@


 /**
- * KVM memory port.  Uses default MasterPort behavior and provides an
+ * KVM memory port.  Uses default RequestPort behavior and provides an
  * interface for KVM to transparently submit atomic or timing requests.
  */
-class KVMCpuPort : public MasterPort
+class KVMCpuPort : public RequestPort
 {

   public:
 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
-: MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
+: RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
 { }
 /**
  * Interface to send Atomic or Timing IO request.  Assumes that  
the pkt

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index b8ca087..579a96b 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -95,7 +95,7 @@
   public:
 /** Provide a non-protected base class for Minor's Ports as derived
  *  classes are created by Fetch1 and Execute */
-class MinorCPUPort : public MasterPort
+class MinorCPUPort : public RequestPort
 {
   public:
 /** The enclosing cpu */
@@ -103,7 +103,7 @@

   public:
 MinorCPUPort(const std::string& name_, MinorCPU _)
-: MasterPort(name_, _), cpu(cpu_)
+: RequestPort(name_, _), cpu(cpu_)
 { }

 };
diff --git 

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32313

to review the following change.


Change subject: gpu-compute: update port terminology
..

gpu-compute: update port terminology

Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
---
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/gpu_tlb.hh
M src/gpu-compute/lds_state.hh
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
9 files changed, 35 insertions(+), 35 deletions(-)



diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 7408bf9..f6f29de 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -161,10 +161,10 @@

 memory_port = VectorMasterPort("Port to the memory system")
 translation_port = VectorMasterPort('Port to the TLB hierarchy')
-sqc_port = MasterPort("Port to the SQC (I-cache")
-sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)")
-scalar_port = MasterPort("Port to the scalar data cache")
-scalar_tlb_port = MasterPort("Port to the TLB for the scalar data  
cache")

+sqc_port = RequestPort("Port to the SQC (I-cache")
+sqc_tlb_port = RequestPort("Port to the TLB for the SQC (I-cache)")
+scalar_port = RequestPort("Port to the scalar data cache")
+scalar_tlb_port = RequestPort("Port to the TLB for the scalar data  
cache")

 perLaneTLB = Param.Bool(False, "enable per-lane TLB")
 prefetch_depth = Param.Int(0, "Number of prefetches triggered at a  
time"\

"(0 turns off prefetching)")
@@ -192,7 +192,7 @@
 max_cu_tokens = Param.Int(4, "Maximum number of tokens, i.e., the  
number"\
 " of instructions that can be sent to  
coalescer")

 ldsBus = Bridge() # the bridge between the CU and its LDS
-ldsPort = MasterPort("The port that goes to the LDS")
+ldsPort = RequestPort("The port that goes to the LDS")
 localDataStore = Param.LdsState("the LDS for this CU")

 vector_register_file = VectorParam.VectorRegisterFile("Vector  
register "\

diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index 2cf8c3a..6bd0a7e 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -44,4 +44,4 @@
 bankConflictPenalty = Param.Int(1, 'penalty per LDS bank conflict  
when '\

 'accessing data')
 banks = Param.Int(32, 'Number of LDS banks')
-cuPort = SlavePort("port that goes to the compute unit")
+cuPort = ResponsePort("port that goes to the compute unit")
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index 701743d..bd22bee 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -40,7 +40,7 @@
 class X86PagetableWalker(SimObject):
 type = 'X86PagetableWalker'
 cxx_class = 'X86ISA::Walker'
-port = SlavePort("Port for the hardware table walker")
+port = ResponsePort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")

 class X86GPUTLB(ClockedObject):
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index 067c254..849fe35 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -2593,7 +2593,7 @@
 computeUnit->cu_id, gpuDynInst->simdId,
 gpuDynInst->wfSlotId);
 return false;
-} else if (!MasterPort::sendTimingReq(pkt)) {
+} else if (!RequestPort::sendTimingReq(pkt)) {
 // need to stall the LDS port until a recvReqRetry() is received
 // this indicates that there is more space
 stallPort();
@@ -2637,7 +2637,7 @@

 DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id);

-if (!MasterPort::sendTimingReq(packet)) {
+if (!RequestPort::sendTimingReq(packet)) {
 // Stall port
 stallPort();
 DPRINTF(GPUPort, ": LDS send failed again\n");
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 22960c0..a3d308e 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -671,11 +671,11 @@
 GMTokenPort gmTokenPort;

 /** Data access Port **/
-class DataPort : public MasterPort
+class DataPort : public RequestPort
 {
   public:
 DataPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
-: MasterPort(_name, _cu), computeUnit(_cu),
+: RequestPort(_name, _cu), computeUnit(_cu),
   index(_index) { }

 bool snoopRangeSent;
@@ -721,12 +721,12 @@
 };

 // Scalar data cache access port
-class ScalarDataPort : public MasterPort
+class 

[gem5-dev] Change in gem5/gem5[develop]: dev: Update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32315 )



Change subject: dev: Update port terminology
..

dev: Update port terminology

Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9
---
M src/dev/Device.py
M src/dev/arm/Gic.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/gic_v3_its.hh
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/dev/x86/I82094AA.py
9 files changed, 19 insertions(+), 18 deletions(-)



diff --git a/src/dev/Device.py b/src/dev/Device.py
index 8950763..d9f351d 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -46,7 +46,7 @@
 type = 'PioDevice'
 cxx_header = "dev/io_device.hh"
 abstract = True
-pio = SlavePort("Programmed I/O port")
+pio = ResponsePort("Programmed I/O port")
 system = Param.System(Parent.any, "System this device is part of")

 def generateBasicPioDeviceNode(self, state, name, pio_addr,
@@ -79,7 +79,7 @@
 type = 'DmaDevice'
 cxx_header = "dev/dma_device.hh"
 abstract = True
-dma = MasterPort("DMA port")
+dma = RequestPort("DMA port")

 _iommu = None

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 59ade75..e2229b8 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -177,7 +177,7 @@
 type = 'Gicv3Its'
 cxx_header = "dev/arm/gic_v3_its.hh"

-dma = MasterPort("DMA port")
+dma = RequestPort("DMA port")
 pio_size = Param.Unsigned(0x2, "Gicv3Its pio size")

 # CIL [36] = 0: ITS supports 16-bit CollectionID
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 5be09de..0b9ab21 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -43,9 +43,9 @@
 type = 'SMMUv3SlaveInterface'
 cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'

-slave = SlavePort('Device port')
-ats_master = MasterPort('ATS master port')
-ats_slave  = SlavePort('ATS slave port')
+slave = ResponsePort('Device port')
+ats_master = RequestPort('ATS master port')
+ats_slave  = ResponsePort('ATS slave port')

 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
 wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
@@ -74,10 +74,11 @@
 type = 'SMMUv3'
 cxx_header = 'dev/arm/smmu_v3.hh'

-master = MasterPort('Master port')
-master_walker = MasterPort(
+master = RequestPort('Master port')
+master_walker = RequestPort(
 'Master port for SMMU initiated HWTW requests (optional)')
-control = SlavePort('Control port for accessing memory-mapped  
registers')

+control = ResponsePort(
+'Control port for accessing memory-mapped registers')
 sample_period = Param.Clock('10us', 'Stats sample period')
 reg_map = Param.AddrRange('Address range for control registers')
 system = Param.System(Parent.any, "System this device is part of")
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index 8575f7e..54beb3e 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -77,14 +77,14 @@
 friend class ::ItsTranslation;
 friend class ::ItsCommand;
   public:
-class DataPort : public MasterPort
+class DataPort : public RequestPort
 {
   protected:
 Gicv3Its 

   public:
 DataPort(const std::string &_name, Gicv3Its &_its) :
-MasterPort(_name, &_its),
+RequestPort(_name, &_its),
 its(_its)
 {}

diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index f972fcf..3f54250 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -42,7 +42,7 @@
 #include "dev/arm/smmu_v3_slaveifc.hh"

 SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) :
-MasterPort(_name, &_smmu),
+RequestPort(_name, &_smmu),
 smmu(_smmu)
 {}

@@ -60,7 +60,7 @@

 SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name,
  SMMUv3 &_smmu) :
-MasterPort(_name, &_smmu),
+RequestPort(_name, &_smmu),
 smmu(_smmu)
 {}

diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index 9d54f13..ee68bbb 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -44,7 +44,7 @@
 class SMMUv3;
 class SMMUv3SlaveInterface;

-class SMMUMasterPort : public MasterPort
+class SMMUMasterPort : public RequestPort
 {
   protected:
 SMMUv3 
@@ -58,7 +58,7 @@
 };

 // Separate master port to send MMU initiated requests on
-class SMMUMasterTableWalkPort : public MasterPort
+class SMMUMasterTableWalkPort : public RequestPort
 {
   protected:
 SMMUv3 
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 63642c9..03882e3 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -51,7 +51,7 @@

 DmaPort::DmaPort(ClockedObject *dev, System *s,
  

[gem5-dev] Change in gem5/gem5[develop]: arch: update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32311

to review the following change.


Change subject: arch: update port terminology
..

arch: update port terminology

Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d
---
M src/arch/arm/ArmTLB.py
M src/arch/generic/BaseTLB.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/pagetable_walker.hh
M src/arch/x86/X86LocalApic.py
M src/arch/x86/X86TLB.py
M src/arch/x86/pagetable_walker.hh
7 files changed, 11 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 721d062..a821a04 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -54,7 +54,7 @@
 # to the Stage2MMU, and shared by the two table walkers, but we
 # access it through the ITB and DTB walked objects in the CPU for
 # symmetry with the other ISAs.
-port = MasterPort("Port used by the two table walkers")
+port = RequestPort("Port used by the two table walkers")

 sys = Param.System(Parent.any, "system object parameter")

diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 02776e6..cca7da6 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -34,4 +34,4 @@
 cxx_header = "arch/generic/tlb.hh"
 # Ports to connect with other TLB levels
 slave  = VectorSlavePort("Port closer to the CPU side")
-master = MasterPort("Port closer to memory side")
+master = RequestPort("Port closer to memory side")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 884b71f..4844feb 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -37,7 +37,7 @@
 type = 'RiscvPagetableWalker'
 cxx_class = 'RiscvISA::Walker'
 cxx_header = 'arch/riscv/pagetable_walker.hh'
-port = MasterPort("Port for the hardware table walker")
+port = RequestPort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")
 num_squash_per_cycle = Param.Unsigned(4,
 "Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/riscv/pagetable_walker.hh  
b/src/arch/riscv/pagetable_walker.hh

index 60826a0..d9ab569 100644
--- a/src/arch/riscv/pagetable_walker.hh
+++ b/src/arch/riscv/pagetable_walker.hh
@@ -58,11 +58,11 @@
 {
   protected:
 // Port for accessing memory
-class WalkerPort : public MasterPort
+class WalkerPort : public RequestPort
 {
   public:
 WalkerPort(const std::string &_name, Walker * _walker) :
-  MasterPort(_name, _walker), walker(_walker)
+  RequestPort(_name, _walker), walker(_walker)
 {}

   protected:
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index a28f6f3..442a5e1 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -48,11 +48,11 @@
 type = 'X86LocalApic'
 cxx_class = 'X86ISA::Interrupts'
 cxx_header = 'arch/x86/interrupts.hh'
-int_master = MasterPort("Port for sending interrupt messages")
-int_slave = SlavePort("Port for receiving interrupt messages")
+int_master = RequestPort("Port for sending interrupt messages")
+int_slave = ResponsePort("Port for receiving interrupt messages")
 int_latency = Param.Latency('1ns', \
 "Latency for an interrupt to propagate through this device.")
-pio = SlavePort("Programmed I/O port")
+pio = ResponsePort("Programmed I/O port")
 system = Param.System(Parent.any, "System this device is part of")

 pio_latency = Param.Latency('100ns', 'Programmed IO latency')
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index bb35526..d9dd980 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -43,7 +43,7 @@
 type = 'X86PagetableWalker'
 cxx_class = 'X86ISA::Walker'
 cxx_header = 'arch/x86/pagetable_walker.hh'
-port = MasterPort("Port for the hardware table walker")
+port = RequestPort("Port for the hardware table walker")
 system = Param.System(Parent.any, "system object")
 num_squash_per_cycle = Param.Unsigned(4,
 "Number of outstanding walks that can be squashed per cycle")
diff --git a/src/arch/x86/pagetable_walker.hh  
b/src/arch/x86/pagetable_walker.hh

index a269426..55bb098 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -57,11 +57,11 @@
 {
   protected:
 // Port for accessing memory
-class WalkerPort : public MasterPort
+class WalkerPort : public RequestPort
 {
   public:
 WalkerPort(const std::string &_name, Walker * _walker) :
-  MasterPort(_name, _walker), walker(_walker)
+  RequestPort(_name, _walker), walker(_walker)
 {}

   

[gem5-dev] Change in gem5/gem5[develop]: mem: Deprecate SlavePort and MasterPort classes

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32308 )



Change subject: mem: Deprecate SlavePort and MasterPort classes
..

mem: Deprecate SlavePort and MasterPort classes

After this change, if you use these classes or inherit from these
classes, the compiler will now give you a warning that these names are
deprecated. Instead, you should use ResponsePort and RequestPort,
respectively.

This patch simply deprecates these names. The following patches will
convert all of the code in gem5 to use these new names. The first step
is converting the class names and the uses of these classes, then we
will update the variable names to be more precise as well.

Change-Id: I5e6e90b2916df4dbfccdaabe97423f377a1f6e3f
---
M src/mem/port.cc
M src/mem/port.hh
2 files changed, 114 insertions(+), 95 deletions(-)



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 47e94f4..6460b59 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -50,7 +50,7 @@
 namespace
 {

-class DefaultMasterPort : public MasterPort
+class DefaultRequestPort : public RequestPort
 {
   protected:
 [[noreturn]] void
@@ -60,7 +60,7 @@
 }

   public:
-DefaultMasterPort() : MasterPort("default_master_port", nullptr) {}
+DefaultRequestPort() : RequestPort("default_request_port", nullptr) {}

 // Atomic protocol.
 Tick recvAtomicSnoop(PacketPtr) override { blowUp(); }
@@ -75,7 +75,7 @@
 void recvFunctionalSnoop(PacketPtr) override { blowUp(); }
 };

-class DefaultSlavePort : public SlavePort
+class DefaultResponsePort : public ResponsePort
 {
   protected:
 [[noreturn]] void
@@ -85,7 +85,7 @@
 }

   public:
-DefaultSlavePort() : SlavePort("default_slave_port", nullptr) {}
+DefaultResponsePort() : ResponsePort("default_response_port", nullptr)  
{}


 // Atomic protocol.
 Tick recvAtomic(PacketPtr) override { blowUp(); }
@@ -103,54 +103,55 @@
 AddrRangeList getAddrRanges() const override { return AddrRangeList();  
}

 };

-DefaultMasterPort defaultMasterPort;
-DefaultSlavePort defaultSlavePort;
+DefaultRequestPort defaultRequestPort;
+DefaultResponsePort defaultResponsePort;

 } // anonymous namespace

 /**
- * Master port
+ * Request port
  */
-MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID  
_id)

-: Port(name, _id), _slavePort(), owner(*_owner)
+RequestPort::RequestPort(const std::string& name, SimObject* _owner,
+PortID _id) : Port(name, _id), _responsePort(),
+owner(*_owner)
 {
 }

-MasterPort::~MasterPort()
+RequestPort::~RequestPort()
 {
 }

 void
-MasterPort::bind(Port )
+RequestPort::bind(Port )
 {
-auto *slave_port = dynamic_cast();
-fatal_if(!slave_port, "Can't bind port %s to non-slave port %s.",
+auto *response_port = dynamic_cast();
+fatal_if(!response_port, "Can't bind port %s to non-response port %s.",
  name(), peer.name());
-// master port keeps track of the slave port
-_slavePort = slave_port;
+// request port keeps track of the response port
+_responsePort = response_port;
 Port::bind(peer);
-// slave port also keeps track of master port
-_slavePort->slaveBind(*this);
+// response port also keeps track of request port
+_responsePort->slaveBind(*this);
 }

 void
-MasterPort::unbind()
+RequestPort::unbind()
 {
-panic_if(!isConnected(), "Can't unbind master port %s which is not  
bound.",

- name());
-_slavePort->slaveUnbind();
-_slavePort = 
+panic_if(!isConnected(), "Can't unbind request port %s which is "
+"not bound.", name());
+_responsePort->slaveUnbind();
+_responsePort = 
 Port::unbind();
 }

 AddrRangeList
-MasterPort::getAddrRanges() const
+RequestPort::getAddrRanges() const
 {
-return _slavePort->getAddrRanges();
+return _responsePort->getAddrRanges();
 }

 void
-MasterPort::printAddr(Addr a)
+RequestPort::printAddr(Addr a)
 {
 auto req = std::make_shared(
 a, 1, 0, Request::funcMasterId);
@@ -165,32 +166,32 @@
 /**
  * Slave port
  */
-SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
-: Port(name, id), _masterPort(),
+ResponsePort::ResponsePort(const std::string& name, SimObject* _owner,
+PortID id) : Port(name, id), _requestPort(),
 defaultBackdoorWarned(false), owner(*_owner)
 {
 }

-SlavePort::~SlavePort()
+ResponsePort::~ResponsePort()
 {
 }

 void
-SlavePort::slaveUnbind()
+ResponsePort::slaveUnbind()
 {
-_masterPort = 
+_requestPort = 
 Port::unbind();
 }

 void
-SlavePort::slaveBind(MasterPort& master_port)
+ResponsePort::slaveBind(RequestPort& request_port)
 {
-_masterPort = _port;
-Port::bind(master_port);
+_requestPort = _port;
+Port::bind(request_port);
 }

 Tick
-SlavePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )
+ResponsePort::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )
 {
 if 

[gem5-dev] Change in gem5/gem5[develop]: systemc,sim: Update port terminology

[Shivani Parekh (Gerrit) via gem5-dev]

Shivani Parekh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32316 )



Change subject: systemc,sim: Update port terminology
..

systemc,sim: Update port terminology

Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
---
M src/sim/System.py
M src/sim/system.hh
M src/systemc/tlm_bridge/TlmBridge.py
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.hh
5 files changed, 10 insertions(+), 10 deletions(-)



diff --git a/src/sim/System.py b/src/sim/System.py
index e028f48..dcef74b 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -51,7 +51,7 @@
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
-system_port = MasterPort("System port")
+system_port = RequestPort("System port")

 cxx_exports = [
 PyBindMethod("getMemoryMode"),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821..8e2c472 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -79,7 +79,7 @@
  * master for debug access and for non-structural entities that do
  * not have a port of their own.
  */
-class SystemPort : public MasterPort
+class SystemPort : public RequestPort
 {
   public:

@@ -87,7 +87,7 @@
  * Create a system port with a name and an owner.
  */
 SystemPort(const std::string &_name, SimObject *_owner)
-: MasterPort(_name, _owner)
+: RequestPort(_name, _owner)
 { }
 bool recvTimingResp(PacketPtr pkt) override
 { panic("SystemPort does not receive timing!\n"); return false; }
@@ -237,7 +237,7 @@
  *
  * @return a reference to the system port we own
  */
-MasterPort& getSystemPort() { return _systemPort; }
+RequestPort& getSystemPort() { return _systemPort; }

 /**
  * Additional function to return the Port of a memory object.
diff --git a/src/systemc/tlm_bridge/TlmBridge.py  
b/src/systemc/tlm_bridge/TlmBridge.py

index 6218153..1851464 100644
--- a/src/systemc/tlm_bridge/TlmBridge.py
+++ b/src/systemc/tlm_bridge/TlmBridge.py
@@ -37,7 +37,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = SlavePort('gem5 slave port')
+gem5 = ResponsePort('gem5 slave port')
 addr_ranges = VectorParam.AddrRange([],
 'Addresses served by this port\'s TLM side')

@@ -49,7 +49,7 @@

 system = Param.System(Parent.any, "system")

-gem5 = MasterPort('gem5 master port')
+gem5 = RequestPort('gem5 master port')


 class Gem5ToTlmBridge32(Gem5ToTlmBridgeBase):
diff --git a/src/systemc/tlm_bridge/gem5_to_tlm.hh  
b/src/systemc/tlm_bridge/gem5_to_tlm.hh

index afc8ad9..7e69e3c 100644
--- a/src/systemc/tlm_bridge/gem5_to_tlm.hh
+++ b/src/systemc/tlm_bridge/gem5_to_tlm.hh
@@ -85,7 +85,7 @@
 class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
 {
   private:
-class BridgeSlavePort : public SlavePort
+class BridgeSlavePort : public ResponsePort
 {
   protected:
 Gem5ToTlmBridge 
@@ -130,7 +130,7 @@
   public:
 BridgeSlavePort(const std::string _,
 Gem5ToTlmBridge _) :
-SlavePort(name_, nullptr), bridge(bridge_)
+ResponsePort(name_, nullptr), bridge(bridge_)
 {}
 };

diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.hh  
b/src/systemc/tlm_bridge/tlm_to_gem5.hh

index 03bac29..e2e7540 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.hh
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.hh
@@ -89,7 +89,7 @@
 TlmSenderState(tlm::tlm_generic_payload ) : trans(trans) {}
 };

-class BridgeMasterPort : public MasterPort
+class BridgeMasterPort : public RequestPort
 {
   protected:
 TlmToGem5Bridge 
@@ -105,7 +105,7 @@
   public:
 BridgeMasterPort(const std::string _,
  TlmToGem5Bridge _) :
-MasterPort(name_, nullptr), bridge(bridge_)
+RequestPort(name_, nullptr), bridge(bridge_)
 {}
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Gerrit-Change-Number: 32316
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Updated port classes & refs to remove slaveBind()/UnBind()

[Shivani Parekh (Gerrit) via gem5-dev]

Hello Emily Brickey,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32309

to review the following change.


Change subject: misc: Updated port classes & refs to remove  
slaveBind()/UnBind()

..

misc: Updated port classes & refs to remove slaveBind()/UnBind()

Change-Id: I9106397b8816d8148dd916510bbcf65ed499d303
---
M src/mem/port.cc
M src/mem/port.hh
M src/mem/token_port.cc
3 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 6460b59..b901571 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -131,7 +131,7 @@
 _responsePort = response_port;
 Port::bind(peer);
 // response port also keeps track of request port
-_responsePort->slaveBind(*this);
+_responsePort->responderBind(*this);
 }

 void
@@ -139,7 +139,7 @@
 {
 panic_if(!isConnected(), "Can't unbind request port %s which is "
 "not bound.", name());
-_responsePort->slaveUnbind();
+_responsePort->responderUnbind();
 _responsePort = 
 Port::unbind();
 }
@@ -164,7 +164,7 @@
 }

 /**
- * Slave port
+ * Response port
  */
 ResponsePort::ResponsePort(const std::string& name, SimObject* _owner,
 PortID id) : Port(name, id), _requestPort(),
@@ -177,14 +177,14 @@
 }

 void
-ResponsePort::slaveUnbind()
+ResponsePort::responderUnbind()
 {
 _requestPort = 
 Port::unbind();
 }

 void
-ResponsePort::slaveBind(RequestPort& request_port)
+ResponsePort::responderBind(RequestPort& request_port)
 {
 _requestPort = _port;
 Port::bind(request_port);
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 16ca5d7..17f8596 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -422,13 +422,13 @@
  * Called by the requestor port to unbind. Should never be called
  * directly.
  */
-void slaveUnbind();
+void responderUnbind();

 /**
  * Called by the requestor port to bind. Should never be called
  * directly.
  */
-void slaveBind(RequestPort& request_port);
+void responderBind(RequestPort& request_port);

 /**
  * Default implementations.
diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
index 1a8439d..46d9116 100644
--- a/src/mem/token_port.cc
+++ b/src/mem/token_port.cc
@@ -109,7 +109,7 @@
 void
 TokenSlavePort::unbind()
 {
-SlavePort::slaveUnbind();
+SlavePort::responderUnbind();
 tokenMasterPort = nullptr;
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9106397b8816d8148dd916510bbcf65ed499d303
Gerrit-Change-Number: 32309
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh 
Gerrit-Reviewer: Emily Brickey 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Implement GDB XML target description for PowerPC

[Boris Shingarov (Gerrit) via gem5-dev]

Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31114 )


Change subject: arch-power: Implement GDB XML target description for PowerPC
..

arch-power: Implement GDB XML target description for PowerPC

Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31114
Reviewed-by: Ciro Santilli 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A ext/gdb-xml/power.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
4 files changed, 118 insertions(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, but someone else must approve
  Ciro Santilli: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
new file mode 100644
index 000..da5a07c
--- /dev/null
+++ b/ext/gdb-xml/power.xml
@@ -0,0 +1,92 @@
+
+
+
+
+
+  powerpc
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index a91b5d9..1187acf 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -1,6 +1,7 @@
 # -*- mode:python -*-

 # Copyright (c) 2009 The University of Edinburgh
+# Copyright (c) 2020 LabWare
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -56,3 +57,5 @@
 DebugFlag('Power')

 ISADesc('isa/main.isa')
+
+GdbXml('power.xml', 'gdb_xml_power')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index ccee0b1..661c431 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,6 +136,7 @@

 #include 

+#include "blobs/gdb_xml_power.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
@@ -213,3 +214,19 @@
 return 
 }

+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string  
)

+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_power),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 1b673bb..3bb726e 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -76,6 +76,12 @@
   public:
 RemoteGDB(System *_system, ThreadContext *tc, int _port);
 BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string  
);

 };

 } // namespace PowerISA

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Gerrit-Change-Number: 31114
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: Nightly #27

[Jason Lowe-Power via gem5-dev]

Cool! The nightly builds are "working"! (At least in the sense that they
let us know when something failed :D)

It looks like the change that caused this issue is
https://gem5-review.googlesource.com/c/public/gem5/+/29403.

@Bobby Bruce , it might be nice if this message could
give us links to the commits. If we can't get links to the gerrit easily,
at least links to gem5.googlesource.com would be useful.

Cheers,
Jason

On Thu, Aug 6, 2020 at 1:51 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See  >
>
> Changes:
>
> [gabeblack] scons: Remove the plumbing for running regression tests from
> scons.
>
> [gabeblack] tests: Get rid of the tests/tests.py script.
>
> [gabeblack] tests: Get rid of the tests/testing python package.
>
> [gabeblack] tests: Get rid of the now unused diff-out script.
>
> [gabeblack] util: Delete the util/regress script.
>
> [Bobby R. Bruce] utils,tests: Enable passing of build args to
> compiler-tests.sh
>
> [gabeblack] scons: Remove explicitly set defaults in calls to AddOption.
>
> [gabeblack] scons: Delete the now unused --update-ref option.
>
> [gabeblack] sim: Convert stat functions to use VPtr.
>
> [gabeblack] arch: Use VPtr for uname.
>
> [gabeblack] scons: Make src/systemc/tests/SConscript python 3 compatible.
>
> [gabeblack] scons,fastmodel: Limit how many instances of simgen can run at
> once.
>
> [gabeblack] systemc: Filter a pydot warning message out when checking test
> output.
>
> [gabeblack] systemc: Adjust some type names in a couple tests.
>
> [gabeblack] cpu: Remove the "profile" parameter and plumbing.
>
>
> --
> [...truncated 40.75 KB...]
>  [VER TAGS]  -> MIPS/sim/tags.cc
>  [ CXX] MIPS/sim/debug.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/MachineType.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/L1Cache_Wakeup.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/Directory_Transitions.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/Directory_Wakeup.cc -> .o
>  [LINK]  -> MIPS/cpu/simple/probes/lib.o.partial
>  [ CXX] MIPS/mem/ruby/protocol/DMA_Controller.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/DMA_Transitions.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/DMA_Wakeup.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/L1Cache_Controller.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/L1Cache_Transitions.cc -> .o
>  [ CXX] MIPS/mem/ruby/protocol/Directory_Controller.cc -> .o
>  [ CXX] MIPS/sim/kernel_workload.cc -> .o
>  [ CXX] MIPS/sim/stat_control.cc -> .o
>  [ CXX] MIPS/sim/system.cc -> .o
>  [ CXX] MIPS/sim/faults.cc -> .o
>  [LINK]  -> MIPS/mem/ruby/protocol/lib.o.partial
>  [ CXX] MIPS/sim/process.cc -> .o
>  [ CXX] MIPS/sim/mem_state.cc -> .o
>  [SO PARAM] BaseCPU -> MIPS/params/BaseCPU.hh
>  [ CXX] MIPS/sim/pseudo_inst.cc -> .o
>  [ CXX] MIPS/sim/syscall_emul.cc -> .o
>  [ CXX] MIPS/sim/syscall_desc.cc -> .o
>  [ CXX] MIPS/cpu/testers/directedtest/DirectedGenerator.cc -> .o
>  [ CXX] MIPS/cpu/o3/probe/simple_trace.cc -> .o
>  [ CXX] MIPS/cpu/o3/probe/elastic_trace.cc -> .o
>  [ CXX] MIPS/cpu/testers/traffic_gen/base.cc -> .o
>  [LINK]  -> MIPS/sim/lib.o.partial
>  [ CXX] MIPS/cpu/testers/traffic_gen/base_gen.cc -> .o
>  [ CXX] MIPS/cpu/testers/traffic_gen/traffic_gen.cc -> .o
>  [ CXX] MIPS/python/_m5/param_AtomicSimpleCPU.cc -> .o
>  [SO PyBind] BaseCPU -> MIPS/python/_m5/param_BaseCPU.cc
>  [ CXX] MIPS/python/_m5/param_BaseCPU.cc -> .o
>  [LINK]  -> MIPS/cpu/o3/probe/lib.o.partial
>  [ CXX] MIPS/python/_m5/param_BaseCache.cc -> .o
>  [LINK]  -> MIPS/cpu/testers/traffic_gen/lib.o.partial
>  [ CXX] MIPS/python/_m5/param_BasePrefetcher.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BaseSetAssoc.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BaseSimpleCPU.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BaseTags.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BaseTrafficGen.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BiModeBP.cc -> .o
>  [ CXX] MIPS/python/_m5/param_BranchPredictor.cc -> .o
>  [ CXX] MIPS/python/_m5/param_Cache.cc -> .o
>  [ CXX] MIPS/python/_m5/param_CheckerCPU.cc -> .o
>  [ CXX] MIPS/python/_m5/param_CoherentXBar.cc -> .o
>  [ CXX] MIPS/python/_m5/param_CommMonitor.cc -> .o
>  [ CXX] MIPS/python/_m5/param_CopyEngine.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DMA_Controller.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DRAMCtrl.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DerivO3CPU.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DirectedGenerator.cc -> .o
>  [ CXX] MIPS/python/_m5/param_Directory_Controller.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DmaDevice.cc -> .o
>  [ CXX] MIPS/python/_m5/param_DummyChecker.cc -> .o
>  [ CXX] MIPS/python/_m5/param_ElasticTrace.cc -> .o
>  [ CXX] MIPS/python/_m5/param_EtherDevBase.cc -> .o
>  [ CXX] MIPS/python/_m5/param_EtherDevice.cc -> .o
> 

[gem5-dev] Build failed in Jenkins: Nightly #27

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[gabeblack] scons: Remove the plumbing for running regression tests from scons.

[gabeblack] tests: Get rid of the tests/tests.py script.

[gabeblack] tests: Get rid of the tests/testing python package.

[gabeblack] tests: Get rid of the now unused diff-out script.

[gabeblack] util: Delete the util/regress script.

[Bobby R. Bruce] utils,tests: Enable passing of build args to compiler-tests.sh

[gabeblack] scons: Remove explicitly set defaults in calls to AddOption.

[gabeblack] scons: Delete the now unused --update-ref option.

[gabeblack] sim: Convert stat functions to use VPtr.

[gabeblack] arch: Use VPtr for uname.

[gabeblack] scons: Make src/systemc/tests/SConscript python 3 compatible.

[gabeblack] scons,fastmodel: Limit how many instances of simgen can run at once.

[gabeblack] systemc: Filter a pydot warning message out when checking test 
output.

[gabeblack] systemc: Adjust some type names in a couple tests.

[gabeblack] cpu: Remove the "profile" parameter and plumbing.


--
[...truncated 40.75 KB...]
 [VER TAGS]  -> MIPS/sim/tags.cc
 [ CXX] MIPS/sim/debug.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MachineType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Wakeup.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Wakeup.cc -> .o
 [LINK]  -> MIPS/cpu/simple/probes/lib.o.partial
 [ CXX] MIPS/mem/ruby/protocol/DMA_Controller.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_Wakeup.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Controller.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Controller.cc -> .o
 [ CXX] MIPS/sim/kernel_workload.cc -> .o
 [ CXX] MIPS/sim/stat_control.cc -> .o
 [ CXX] MIPS/sim/system.cc -> .o
 [ CXX] MIPS/sim/faults.cc -> .o
 [LINK]  -> MIPS/mem/ruby/protocol/lib.o.partial
 [ CXX] MIPS/sim/process.cc -> .o
 [ CXX] MIPS/sim/mem_state.cc -> .o
 [SO PARAM] BaseCPU -> MIPS/params/BaseCPU.hh
 [ CXX] MIPS/sim/pseudo_inst.cc -> .o
 [ CXX] MIPS/sim/syscall_emul.cc -> .o
 [ CXX] MIPS/sim/syscall_desc.cc -> .o
 [ CXX] MIPS/cpu/testers/directedtest/DirectedGenerator.cc -> .o
 [ CXX] MIPS/cpu/o3/probe/simple_trace.cc -> .o
 [ CXX] MIPS/cpu/o3/probe/elastic_trace.cc -> .o
 [ CXX] MIPS/cpu/testers/traffic_gen/base.cc -> .o
 [LINK]  -> MIPS/sim/lib.o.partial
 [ CXX] MIPS/cpu/testers/traffic_gen/base_gen.cc -> .o
 [ CXX] MIPS/cpu/testers/traffic_gen/traffic_gen.cc -> .o
 [ CXX] MIPS/python/_m5/param_AtomicSimpleCPU.cc -> .o
 [SO PyBind] BaseCPU -> MIPS/python/_m5/param_BaseCPU.cc
 [ CXX] MIPS/python/_m5/param_BaseCPU.cc -> .o
 [LINK]  -> MIPS/cpu/o3/probe/lib.o.partial
 [ CXX] MIPS/python/_m5/param_BaseCache.cc -> .o
 [LINK]  -> MIPS/cpu/testers/traffic_gen/lib.o.partial
 [ CXX] MIPS/python/_m5/param_BasePrefetcher.cc -> .o
 [ CXX] MIPS/python/_m5/param_BaseSetAssoc.cc -> .o
 [ CXX] MIPS/python/_m5/param_BaseSimpleCPU.cc -> .o
 [ CXX] MIPS/python/_m5/param_BaseTags.cc -> .o
 [ CXX] MIPS/python/_m5/param_BaseTrafficGen.cc -> .o
 [ CXX] MIPS/python/_m5/param_BiModeBP.cc -> .o
 [ CXX] MIPS/python/_m5/param_BranchPredictor.cc -> .o
 [ CXX] MIPS/python/_m5/param_Cache.cc -> .o
 [ CXX] MIPS/python/_m5/param_CheckerCPU.cc -> .o
 [ CXX] MIPS/python/_m5/param_CoherentXBar.cc -> .o
 [ CXX] MIPS/python/_m5/param_CommMonitor.cc -> .o
 [ CXX] MIPS/python/_m5/param_CopyEngine.cc -> .o
 [ CXX] MIPS/python/_m5/param_DMA_Controller.cc -> .o
 [ CXX] MIPS/python/_m5/param_DRAMCtrl.cc -> .o
 [ CXX] MIPS/python/_m5/param_DerivO3CPU.cc -> .o
 [ CXX] MIPS/python/_m5/param_DirectedGenerator.cc -> .o
 [ CXX] MIPS/python/_m5/param_Directory_Controller.cc -> .o
 [ CXX] MIPS/python/_m5/param_DmaDevice.cc -> .o
 [ CXX] MIPS/python/_m5/param_DummyChecker.cc -> .o
 [ CXX] MIPS/python/_m5/param_ElasticTrace.cc -> .o
 [ CXX] MIPS/python/_m5/param_EtherDevBase.cc -> .o
 [ CXX] MIPS/python/_m5/param_EtherDevice.cc -> .o
 [ CXX] MIPS/python/_m5/param_ExeTracer.cc -> .o
 [ CXX] MIPS/python/_m5/param_ExternalMaster.cc -> .o
 [ CXX] MIPS/python/_m5/param_GarnetSyntheticTraffic.cc -> .o
 [ CXX] MIPS/python/_m5/param_Gem5ToTlmBridge32.cc -> .o
 [ CXX] MIPS/python/_m5/param_Gem5ToTlmBridge64.cc -> .o
 [ CXX] MIPS/python/_m5/param_Gem5ToTlmBridgeBase.cc -> .o
 [ CXX] MIPS/python/_m5/param_IGbE.cc -> .o
 [ CXX] MIPS/python/_m5/param_IdeController.cc -> .o
 [ CXX] MIPS/python/_m5/param_IdeDisk.cc -> .o
 [ CXX] MIPS/python/_m5/param_InstPBTrace.cc -> .o
 [ CXX] MIPS/python/_m5/param_InstTracer.cc -> .o
 [ CXX] MIPS/python/_m5/param_IntelTrace.cc -> .o
 [ CXX] 

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-ruby: make simplenetwork compatible with garnet3.0 topologies

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Hello John Alsop,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32306

to review the following change.


Change subject: mem-ruby: make simplenetwork compatible with garnet3.0  
topologies

..

mem-ruby: make simplenetwork compatible with garnet3.0 topologies

1) To support controllers with multiple outgoing links (added
in garnet 3.0), only connect a message buffer to a controller
if the vnet in that message buffer matches the
vnets assigned to the link. This is needed to support controllers
with multiple outgoing links (added in garnet 3.0).

Similarly, a separate routing table must be managed for each vnet
at each simple network router.

2) Dummy parameters must be added for garnet-specific members
in network base classes to prevent errors.

Change-Id: I78cfce99edf73cd647c05ef7a3a619218493d9de
---
M src/mem/ruby/network/BasicLink.py
M src/mem/ruby/network/garnet2.0/GarnetLink.py
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/SimpleNetwork.py
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
8 files changed, 63 insertions(+), 30 deletions(-)



diff --git a/src/mem/ruby/network/BasicLink.py  
b/src/mem/ruby/network/BasicLink.py

index 2718aa6..b9ded1f 100644
--- a/src/mem/ruby/network/BasicLink.py
+++ b/src/mem/ruby/network/BasicLink.py
@@ -39,6 +39,16 @@
 weight = Param.Int(1, "used to restrict routing in shortest path  
analysis")
 supported_vnets = VectorParam.Int([-1], "Vnets supported  
Default:All(-1)")


+# dummy variables for compatibility with garnet topology
+ext_cdc = Param.Bool(False, "Dummy")
+int_cdc = Param.Bool(False, "Dummy")
+ext_serdes = Param.Bool(False, "Dummy")
+int_serdes = Param.Bool(False, "Dummy")
+src_serdes = Param.Bool(False, "Dummy")
+dst_serdes = Param.Bool(False, "Dummy")
+width = Param.UInt32(0, "Dummy")
+vcs_per_vnet = Param.Int(0, "Dummy")
+
 class BasicExtLink(BasicLink):
 type = 'BasicExtLink'
 cxx_header = "mem/ruby/network/BasicLink.hh"
@@ -46,6 +56,12 @@
 int_node = Param.BasicRouter("ID of internal node")
 bandwidth_factor = 16 # only used by simple network

+# only used by Garnet.
+ext_cdc = Param.Bool(False, "Enable CDC")
+int_cdc = Param.Bool(False, "Enable CDC")
+ext_serdes = Param.Bool(False, "Enable CDC")
+int_serdes = Param.Bool(False, "Enable CDC")
+
 class BasicIntLink(BasicLink):
 type = 'BasicIntLink'
 cxx_header = "mem/ruby/network/BasicLink.hh"
@@ -55,6 +71,10 @@
 # only used by Garnet.
 src_outport = Param.String("", "Outport direction at src router")
 dst_inport = Param.String("", "Inport direction at dst router")
+src_cdc = Param.Bool(False, "Enable CDC")
+dst_cdc = Param.Bool(False, "Enable CDC")
+src_serdes = Param.Bool(False, "Enable CDC")
+dst_serdes = Param.Bool(False, "Enable CDC")

 # only used by simple network
 bandwidth_factor = 16
diff --git a/src/mem/ruby/network/garnet2.0/GarnetLink.py  
b/src/mem/ruby/network/garnet2.0/GarnetLink.py

index 769680c..f356d97 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetLink.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetLink.py
@@ -64,17 +64,11 @@
 network_link = Param.NetworkLink(NetworkLink(), "forward link")
 credit_link  = Param.CreditLink(CreditLink(), "backward flow-control  
link")


-src_cdc = Param.Bool(False, "Enable CDC")
-dst_cdc = Param.Bool(False, "Enable CDC")
-
 src_net_bridge = Param.NetworkBridge("Network CDC at source")
 dst_net_bridge = Param.NetworkBridge("Network CDC at dest")
 src_cred_bridge = Param.NetworkBridge("Credit CDC at source")
 dst_cred_bridge = Param.NetworkBridge("Credit CDC at dest")

-src_serdes = Param.Bool(False, "Enable CDC")
-dst_serdes = Param.Bool(False, "Enable CDC")
-
 width = Param.UInt32(Parent.ni_flit_size,
   "bit width supported by the router")

@@ -100,16 +94,10 @@
 _cls.append(CreditLink());
 credit_links = VectorParam.CreditLink(_cls, "backward flow-control  
links")


-ext_cdc = Param.Bool(False, "Enable CDC")
-int_cdc = Param.Bool(False, "Enable CDC")
-
 ext_net_bridge = VectorParam.NetworkBridge("CDC to reach the  
consumers")
 ext_cred_bridge = VectorParam.NetworkBridge("CDC to reach the  
consumers")
 int_net_bridge = VectorParam.NetworkBridge("CDC to reach the  
consumers")
 int_cred_bridge = VectorParam.NetworkBridge("CDC to reach the  
consumers")


-ext_serdes = Param.Bool(False, "Enable CDC")
-int_serdes = Param.Bool(False, "Enable CDC")
-
 width = Param.UInt32(Parent.ni_flit_size,
   "bit width supported by the router")
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc  

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Fix scheduling of links in case of multiple physical links

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32304 )



Change subject: mem-garnet: Fix scheduling of links in case of multiple  
physical links

..

mem-garnet: Fix scheduling of links in case of multiple physical links

Network Interface must be able to schedule flits in all physical
links in every cycle. Earlier implementation did not allow it.
This patch fixes to let NI schedule a flit for every link.
Each output port maintains its own round robin arbiter.

Change-Id: Ie41a2d03b0115f081d2cc5a5f9f1865eda88576e
---
M src/mem/ruby/network/garnet2.0/NetworkInterface.cc
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
2 files changed, 59 insertions(+), 38 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc  
b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc

index 85a161c..5cb61d3 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
@@ -48,7 +48,6 @@
   : ClockedObject(p), Consumer(this), m_id(p->id),
 m_virtual_networks(p->virt_nets), m_vc_per_vnet(0),
 m_vc_allocator(m_virtual_networks, 0),
-m_vc_round_robin(0),
 m_deadlock_threshold(p->garnet_deadlock_threshold),
 vc_busy_counter(m_virtual_networks, 0)
 {
@@ -485,51 +484,59 @@
 void
 NetworkInterface::scheduleOutputLink()
 {
-int vc = m_vc_round_robin;
+// Schedule each output link
+for (auto : outPorts) {
+int vc = oPort->vcRoundRobin();

-for (int i = 0; i < niOutVcs.size(); i++) {
-vc++;
-if (vc == niOutVcs.size())
-vc = 0;
+for (int i = 0; i < m_num_vcs; i++) {
+vc++;
+if (vc == m_num_vcs)
+vc = 0;

-// model buffer backpressure
-if (niOutVcs[vc].isReady(curTick()) &&
-outVcState[vc].has_credit()) {
-
-bool is_candidate_vc = true;
 int t_vnet = get_vnet(vc);
-int vc_base = t_vnet * m_vc_per_vnet;
+if (oPort->isVnetSupported(t_vnet)) {
+// model buffer backpressure
+if (m_ni_out_vcs[vc]->isReady(curTick()) &&
+m_out_vc_state[vc]->has_credit()) {

-if (m_net_ptr->isVNetOrdered(t_vnet)) {
-for (int vc_offset = 0; vc_offset < m_vc_per_vnet;
- vc_offset++) {
-int t_vc = vc_base + vc_offset;
-if (niOutVcs[t_vc].isReady(curTick())) {
-if (m_ni_out_vcs_enqueue_time[t_vc] <
-m_ni_out_vcs_enqueue_time[vc]) {
-is_candidate_vc = false;
-break;
+bool is_candidate_vc = true;
+int vc_base = t_vnet * m_vc_per_vnet;
+
+if (m_net_ptr->isVNetOrdered(t_vnet)) {
+for (int vc_offset = 0; vc_offset < m_vc_per_vnet;
+ vc_offset++) {
+int t_vc = vc_base + vc_offset;
+if (niOutVcs[t_vc].isReady(curTick())) {
+if (m_ni_out_vcs_enqueue_time[t_vc] <
+m_ni_out_vcs_enqueue_time[vc]) {
+is_candidate_vc = false;
+break;
+}
+}
 }
 }
+if (!is_candidate_vc)
+continue;
+
+// Update the round robin arbiter
+oPort->vcRoundRobin(vc);
+
+outVcState[vc].decrement_credit();
+// Just removing the flit
+flit *t_flit = m_ni_out_vcs[vc]->getTopFlit();
+t_flit->set_time(clockEdge(Cycles(1)));
+scheduleFlit(t_flit);
+
+if (t_flit->get_type() == TAIL_ ||
+   t_flit->get_type() == HEAD_TAIL_) {
+m_ni_out_vcs_enqueue_time[vc] = Tick(INFINITE_);
+}
+goto donePort;
 }
 }
-if (!is_candidate_vc)
-continue;
-
-m_vc_round_robin = vc;
-
-outVcState[vc].decrement_credit();
-// Just removing the flit
-flit *t_flit = niOutVcs[vc].getTopFlit();
-t_flit->set_time(clockEdge(Cycles(1)));
-scheduleFlit(t_flit);
-
-if (t_flit->get_type() == TAIL_ ||
-   t_flit->get_type() == HEAD_TAIL_) {
-m_ni_out_vcs_enqueue_time[vc] = Tick(INFINITE_);
-}
-return;
 }
+donePort:
+continue;
 }
 }

diff --git a/src/mem/ruby/network/garnet2.0/NetworkInterface.hh  

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-ruby: Check number of vnets when creating links

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32307 )



Change subject: mem-ruby: Check number of vnets when creating links
..

mem-ruby: Check number of vnets when creating links

Added error checking to ensure that the system has sufficient virtual
networks when setting latency and weight values.

Change-Id: I1b28144bbe9fefab0c0a6227f1fdf4ea10403061
---
M src/mem/ruby/network/Topology.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/network/Topology.cc  
b/src/mem/ruby/network/Topology.cc

index b267db1..c45dd9d 100644
--- a/src/mem/ruby/network/Topology.cc
+++ b/src/mem/ruby/network/Topology.cc
@@ -165,6 +165,8 @@
 } else {
 for (int v = 0; v < link->mVnets.size(); v++) {
 int vnet = link->mVnets[v];
+fatal_if(vnet >= m_vnets, "Not enough virtual  
networks "
+ "(setting latency and weight for vnet %d)",  
vnet);

 // Two links connecting same src and destination
 // cannot carry same vnets.
 fatal_if(vnet_done[vnet], "Two links connecting same  
src"


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32307
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: I1b28144bbe9fefab0c0a6227f1fdf4ea10403061
Gerrit-Change-Number: 32307
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Add a check to see if router is already scheduled

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32302 )



Change subject: mem-garnet: Add a check to see if router is already  
scheduled

..

mem-garnet: Add a check to see if router is already scheduled

Currently the Switch Allocator takes up most of the simulation
wall clock time. This function checks for all VCs to see if it
should wakeup next. The input units which are simulated before
the switch allocator could have scheduled it already. This patch
adds a check for it.

Change-Id: I8609d4e7f925aa5e97198f6cd07466530f6fcf4c
---
M src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
1 file changed, 4 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc  
b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc

index 144f208..3241343 100644
--- a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
+++ b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
@@ -350,6 +350,10 @@
 {
 Tick nextCycle = m_router->clockEdge(Cycles(1));

+if (m_router->alreadyScheduled(nextCycle)) {
+return;
+}
+
 for (int i = 0; i < m_num_inports; i++) {
 for (int j = 0; j < m_num_vcs; j++) {
 if (m_router->getInputUnit(i)->need_stage(j, SA_, nextCycle)) {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/32302
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: I8609d4e7f925aa5e97198f6cd07466530f6fcf4c
Gerrit-Change-Number: 32302
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Separable allocator in Garnet not fair enough.

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32303 )



Change subject: mem-garnet: Separable allocator in Garnet not fair enough.
..

mem-garnet: Separable allocator in Garnet not fair enough.

Currently there are independent round robin arbiter at each
input port and output port. Every time a VC is selected for
output allocation round robin is incremented irrespective of
if it is selected by its output port or not. This leads to
unfair arbitration at input port and is well known[1]. This
patch fixes it to increment only if the output port also
selects it.

[1] D. U. Becker and W. J. Dally, "Allocator implementations
for network-on-chip routers," Proceedings of the Conference
on High Performance Computing Networking, Storage and
Analysis, Portland, OR, 2009, pp. 1-12

Change-Id: I65963fb8082c51c0e3c6e031a8b87b4f5c3626e1
---
M src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
1 file changed, 9 insertions(+), 5 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc  
b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc

index 3241343..1ed6de1 100644
--- a/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
+++ b/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
@@ -130,11 +130,6 @@
 m_port_requests[outport][inport] = true;
 m_vc_winners[outport][inport]= invc;

-// Update Round Robin pointer to the next VC
-m_round_robin_invc[inport] = invc + 1;
-if (m_round_robin_invc[inport] >= m_num_vcs)
-m_round_robin_invc[inport] = 0;
-
 break; // got one vc winner for this port
 }
 }
@@ -248,6 +243,15 @@
 if (m_round_robin_inport[outport] >= m_num_inports)
 m_round_robin_inport[outport] = 0;

+// Update Round Robin pointer to the next VC
+// We do it here to keep it fair.
+// Only the VC which got switch traversal
+// is updated.
+m_round_robin_invc[inport] = invc + 1;
+if (m_round_robin_invc[inport] >= m_num_vcs)
+m_round_robin_invc[inport] = 0;
+
+
 break; // got a input winner for this outport
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: I65963fb8082c51c0e3c6e031a8b87b4f5c3626e1
Gerrit-Change-Number: 32303
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Allow simulataneous enqueue in case of multiple links

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32305 )



Change subject: mem-garnet: Allow simulataneous enqueue in case of multiple  
links

..

mem-garnet: Allow simulataneous enqueue in case of multiple links

HeteroGarnet allows multiple links connected to controllers.
But we did not support multiple enqueue leading to bottlenecks
after the flit reaches Network Interface. We should allow multiple
enqueue for disjoint links.

Change-Id: Id2bc56eada85c620d3eed9b3cc05af5ab5c33903
---
M src/mem/ruby/network/garnet2.0/NetworkInterface.cc
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
2 files changed, 45 insertions(+), 43 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc  
b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc

index 5cb61d3..190aabe 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
@@ -219,7 +219,7 @@

 // Check if there are flits stalling a virtual channel. Track if a
 // message is enqueued to restrict ejection to one message per cycle.
-bool messageEnqueuedThisCycle = checkStallQueue();
+checkStallQueue();

 /*** Check the incoming flit link **/
 DPRINTF(RubyNetwork, "Number of input ports: %d\n", inPorts.size());
@@ -238,7 +238,7 @@
 // credits.
 if (t_flit->get_type() == TAIL_ ||
 t_flit->get_type() == HEAD_TAIL_) {
-if (!messageEnqueuedThisCycle &&
+if (!iPort->messageEnqueuedThisCycle &&
 outNode_ptr[vnet]->areNSlotsAvailable(1, curTime)) {
 // Space is available. Enqueue to protocol buffer.
 outNode_ptr[vnet]->enqueue(t_flit->get_msg_ptr(),  
curTime,

@@ -257,7 +257,7 @@
 // set up a callback for when protocol buffer is  
dequeued.
 // Stat update and flit pointer deletion will occur  
upon

 // unstall.
-m_stall_queue.push_back(t_flit);
+iPort->m_stall_queue.push_back(t_flit);
 m_stall_count[vnet]++;

 auto cb = std::bind(::dequeueCallback,
@@ -311,55 +311,56 @@
 checkReschedule();
 }

-bool
+void
 NetworkInterface::checkStallQueue()
 {
-bool messageEnqueuedThisCycle = false;
-Tick curTime = clockEdge();
+// Check all stall queues.
+// There is one stall queue for each input link
+for (auto : inPorts) {
+iPort->messageEnqueuedThisCycle = false;
+Tick curTime = clockEdge();

-if (!m_stall_queue.empty()) {
-for (auto stallIter = m_stall_queue.begin();
- stallIter != m_stall_queue.end(); ) {
-flit *stallFlit = *stallIter;
-int vnet = stallFlit->get_vnet();
+if (!iPort->m_stall_queue.empty()) {
+for (auto stallIter = iPort->m_stall_queue.begin();
+ stallIter != iPort->m_stall_queue.end(); ) {
+flit *stallFlit = *stallIter;
+int vnet = stallFlit->get_vnet();

-// If we can now eject to the protocol buffer, send back  
credits

-if (outNode_ptr[vnet]->areNSlotsAvailable(1, curTime)) {
-outNode_ptr[vnet]->enqueue(stallFlit->get_msg_ptr(),  
curTime,

-   cyclesToTicks(Cycles(1)));
+// If we can now eject to the protocol buffer,
+// send back credits
+if (outNode_ptr[vnet]->areNSlotsAvailable(1,
+curTime)) {
+outNode_ptr[vnet]->enqueue(stallFlit->get_msg_ptr(),
+curTime, cyclesToTicks(Cycles(1)));

-// Send back a credit with free signal now that the VC is  
no

-// longer stalled.
-Credit *cFlit = new Credit(stallFlit->get_vc(), true,
-   curTick());
-InputPort *iPort = getInportForVnet(vnet);
-assert(iPort);
+// Send back a credit with free signal now that the
+// VC is no longer stalled.
+Credit *cFlit = new Credit(stallFlit->get_vc(), true,
+   curTick());
+iPort->sendCredit(cFlit);

-iPort->sendCredit(cFlit);
+// Update Stats
+incrementStats(stallFlit);

-// Update Stats
-incrementStats(stallFlit);
+// Flit can now safely be deleted and removed from  
stall

+// queue
+delete stallFlit;
+iPort->m_stall_queue.erase(stallIter);
+m_stall_count[vnet]--;

-// 

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Improve debug messages within Garnet

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32300 )



Change subject: mem-garnet: Improve debug messages within Garnet
..

mem-garnet: Improve debug messages within Garnet

This patch clears up some redundant debug messages and adds
some more clarity in existing logs.

Change-Id: I5d351e5a1d64234cc3880b59b1d5992f91b579f2
---
M src/mem/ruby/network/garnet2.0/NetworkInterface.cc
M src/mem/ruby/network/garnet2.0/NetworkLink.cc
M src/mem/ruby/network/garnet2.0/Router.cc
3 files changed, 5 insertions(+), 16 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc  
b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc

index 81c062f..85a161c 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
@@ -223,11 +223,9 @@
 bool messageEnqueuedThisCycle = checkStallQueue();

 /*** Check the incoming flit link **/
-DPRINTF(RubyNetwork, "Number of iPorts: %d\n", inPorts.size());
+DPRINTF(RubyNetwork, "Number of input ports: %d\n", inPorts.size());
 for (auto : inPorts) {
 NetworkLink *inNetLink = iPort->inNetLink();
-DPRINTF(RubyNetwork, "Checking input port:%s with vnets %s\n",
-inNetLink->name(), iPort->printVnets());
 if (inNetLink->isReady(curTick())) {
 flit *t_flit = inNetLink->consumeLink();
 DPRINTF(RubyNetwork, "Recieved flit:%s\n", *t_flit);
@@ -286,8 +284,6 @@

 for (auto : outPorts) {
 CreditLink *inCreditLink = oPort->inCreditLink();
-DPRINTF(RubyNetwork, "Checking input port:%s with vnets %s\n",
-inCreditLink->name(), oPort->printVnets());
 if (inCreditLink->isReady(curTick())) {
 Credit *t_credit = (Credit*) inCreditLink->consumeLink();
 outVcState[t_credit->get_vc()].increment_credit();
@@ -306,7 +302,8 @@
 // back.
 for (auto : inPorts) {
 if (iPort->outCreditQueue()->getSize() > 0) {
-DPRINTF(RubyNetwork, "Sending a credit via %s at %ld\n",
+DPRINTF(RubyNetwork, "Sending a credit %s via %s at %ld\n",
+*(iPort->outCreditQueue()->peekTopFlit()),
 iPort->outCreditLink()->name(), clockEdge(Cycles(1)));
 iPort->outCreditLink()->
 scheduleEventAbsolute(clockEdge(Cycles(1)));
diff --git a/src/mem/ruby/network/garnet2.0/NetworkLink.cc  
b/src/mem/ruby/network/garnet2.0/NetworkLink.cc

index 11ac4cb..cb00943 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkLink.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkLink.cc
@@ -78,10 +78,10 @@
 assert(curTick() == clockEdge());
 if (link_srcQueue->isReady(curTick())) {
 flit *t_flit = link_srcQueue->getTopFlit();
+DPRINTF(RubyNetwork, "Transmission will finish at %ld :%s\n",
+clockEdge(m_latency), *t_flit);
 if (m_type != NUM_LINK_TYPES_) {
 // Only for assertions and debug messages
-DPRINTF(RubyNetwork, "Transmitting at %ld :%s\n",
-clockEdge(m_latency), *t_flit);
 assert(t_flit->m_width == bitWidth);
 assert((std::find(mVnets.begin(), mVnets.end(),
 t_flit->get_vnet()) != mVnets.end()) ||
diff --git a/src/mem/ruby/network/garnet2.0/Router.cc  
b/src/mem/ruby/network/garnet2.0/Router.cc

index 523680e..9802b69 100644
--- a/src/mem/ruby/network/garnet2.0/Router.cc
+++ b/src/mem/ruby/network/garnet2.0/Router.cc
@@ -93,9 +93,6 @@
 Router::addInPort(PortDirection inport_dirn,
   NetworkLink *in_link, CreditLink *credit_link)
 {
-DPRINTF(RubyNetwork, "%d == %d? %s\n", in_link->bitWidth,
-m_bit_width, in_link->name());
-
 fatal_if(in_link->bitWidth != m_bit_width, "Widths of link %s(%d)does"
 " not match that of Router%d(%d). Consider inserting SerDes "
 "Units.", in_link->name(), in_link->bitWidth, m_id,  
m_bit_width);

@@ -121,11 +118,6 @@
std::vector& routing_table_entry, int  
link_weight,

CreditLink *credit_link, uint32_t consumerVcs)
 {
-DPRINTF(RubyNetwork, "%d == %d? %s\n", out_link->bitWidth,
-m_bit_width, out_link->name());
-DPRINTF(RubyNetwork, "Consumer %s VC: %d\n", out_link->name(),
-consumerVcs);
-
 fatal_if(out_link->bitWidth != m_bit_width, "Widths of units do not  
match."

 " Consider inserting SerDes Units");


--
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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: I5d351e5a1d64234cc3880b59b1d5992f91b579f2
Gerrit-Change-Number: 32300
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-MessageType: 

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-ruby: fix compilation error of uninitialized 'vnet_done'

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Hello Xianwei Zhang,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32301

to review the following change.


Change subject: mem-ruby: fix compilation error of uninitialized 'vnet_done'
..

mem-ruby: fix compilation error of uninitialized 'vnet_done'

Encountered compilation error: variable-sized object 'vnet_done'
may not be initialized. To fix, this patch replaces the array
with a vector.

Change-Id: If72e52a023c75e2f6df871d339df0d0919dfe2d1
---
M src/mem/ruby/network/Topology.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/network/Topology.cc  
b/src/mem/ruby/network/Topology.cc

index e1622d8..b267db1 100644
--- a/src/mem/ruby/network/Topology.cc
+++ b/src/mem/ruby/network/Topology.cc
@@ -142,7 +142,7 @@
 for (LinkMap::const_iterator i = m_link_map.begin();
  i != m_link_map.end(); ++i) {
 std::pair src_dest = (*i).first;
-bool vnet_done[m_vnets] = { 0 };
+vector vnet_done(m_vnets, 0);
 int src = src_dest.first;
 int dst = src_dest.second;


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Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: If72e52a023c75e2f6df871d339df0d0919dfe2d1
Gerrit-Change-Number: 32301
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Xianwei Zhang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Flexible VCs per Vnet for each router

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32299 )



Change subject: mem-garnet: Flexible VCs per Vnet for each router
..

mem-garnet: Flexible VCs per Vnet for each router

This change allows configuring each router with a certain number
of VCs for each VNET. This is beneficial when dealing with
heterogenous link widths in a system. Configuring VCs
for each router allows one to ensure equal throuput
within the network while avoiding head-of-line blocking.
Changing a router's VCs number can be done in topology files
using the vcs_per_vnet value argument of router.

Change-Id: Icf4f510248128429a1a11f19f9802ee96f340611
---
M src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
M src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
M src/mem/ruby/network/garnet2.0/NetworkBridge.cc
M src/mem/ruby/network/garnet2.0/NetworkBridge.hh
M src/mem/ruby/network/garnet2.0/NetworkInterface.cc
M src/mem/ruby/network/garnet2.0/NetworkInterface.hh
M src/mem/ruby/network/garnet2.0/NetworkLink.cc
M src/mem/ruby/network/garnet2.0/NetworkLink.hh
M src/mem/ruby/network/garnet2.0/OutVcState.cc
M src/mem/ruby/network/garnet2.0/OutVcState.hh
M src/mem/ruby/network/garnet2.0/OutputUnit.cc
M src/mem/ruby/network/garnet2.0/OutputUnit.hh
M src/mem/ruby/network/garnet2.0/Router.cc
M src/mem/ruby/network/garnet2.0/Router.hh
14 files changed, 127 insertions(+), 54 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc  
b/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc

index ca9e26f..3e3852a 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
@@ -58,7 +58,7 @@
 {
 m_num_rows = p->num_rows;
 m_ni_flit_size = p->ni_flit_size;
-m_vcs_per_vnet = p->vcs_per_vnet;
+m_max_vcs_per_vnet = 0;
 m_buffers_per_data_vc = p->buffers_per_data_vc;
 m_buffers_per_ctrl_vc = p->buffers_per_ctrl_vc;
 m_routing_algorithm = p->routing_algorithm;
@@ -166,15 +166,19 @@

 PortDirection dst_inport_dirn = "Local";

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+   (uint32_t) m_routers[dest]->get_vc_per_vnet());
+
 if (garnet_link->extBridgeEn) {
 DPRINTF(RubyNetwork, "Enable external bridge for %s\n",
 garnet_link->name());
 m_nis[local_src]->
 addOutPort(garnet_link->extNetBridge[LinkDirection_In],
garnet_link->extCredBridge[LinkDirection_In],
-   dest);
+   dest, m_routers[dest]->get_vc_per_vnet());
 } else {
-m_nis[local_src]->addOutPort(net_link, credit_link, dest);
+m_nis[local_src]->addOutPort(net_link, credit_link, dest,
+m_routers[dest]->get_vc_per_vnet());
 }

 if (garnet_link->intBridgeEn) {
@@ -218,6 +222,9 @@

 PortDirection src_outport_dirn = "Local";

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+   (uint32_t) m_routers[src]->get_vc_per_vnet());
+
 if (garnet_link->extBridgeEn) {
 DPRINTF(RubyNetwork, "Enable external bridge for %s\n",
 garnet_link->name());
@@ -235,12 +242,14 @@
 addOutPort(src_outport_dirn,
garnet_link->intNetBridge[LinkDirection_Out],
routing_table_entry, link->m_weight,
-   garnet_link->intCredBridge[LinkDirection_Out]);
+   garnet_link->intCredBridge[LinkDirection_Out],
+   m_routers[src]->get_vc_per_vnet());
 } else {
 m_routers[src]->
 addOutPort(src_outport_dirn, net_link,
routing_table_entry,
-   link->m_weight, credit_link);
+   link->m_weight, credit_link,
+   m_routers[src]->get_vc_per_vnet());
 }
 }

@@ -265,6 +274,10 @@
 m_networklinks.push_back(net_link);
 m_creditlinks.push_back(credit_link);

+m_max_vcs_per_vnet = std::max(m_max_vcs_per_vnet,
+std::max((uint32_t) m_routers[dest]->get_vc_per_vnet(),
+(uint32_t) m_routers[src]->get_vc_per_vnet()));
+
 if (garnet_link->dstBridgeEn) {
 DPRINTF(RubyNetwork, "Enable destination bridge for %s\n",
 garnet_link->name());
@@ -280,11 +293,13 @@
 m_routers[src]->
 addOutPort(src_outport_dirn, garnet_link->srcNetBridge,
routing_table_entry,
-   link->m_weight, garnet_link->srcCredBridge);
+   link->m_weight, garnet_link->srcCredBridge,
+   m_routers[dest]->get_vc_per_vnet());
 } else {
 m_routers[src]->addOutPort(src_outport_dirn, net_link,
 routing_table_entry,
-link->m_weight, credit_link);
+link->m_weight, credit_link,
+

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet:Fix Serdes credit bug

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32295 )



Change subject: mem-garnet:Fix Serdes credit bug
..

mem-garnet:Fix Serdes credit bug

This patch fixes the way we convert flits for the
cases when message sizes are not multiples of link
width sizes.

Change-Id: I634ca8105d3025ba38b353da95dbd57389f2c0c9
---
M src/mem/ruby/network/garnet2.0/NetworkBridge.cc
M src/mem/ruby/network/garnet2.0/OutputUnit.cc
M src/mem/ruby/network/garnet2.0/Router.cc
M src/mem/ruby/network/garnet2.0/flit.cc
4 files changed, 34 insertions(+), 26 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc  
b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc

index 3c834d9..0073c65 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
@@ -113,15 +113,15 @@
 // Serialize-Deserialize only if it is enabled
 if (enSerDes) {
 // Calculate the target-width
-uint32_t target_width = bitWidth;
-uint32_t cur_width = nLink->bitWidth;
+int target_width = bitWidth;
+int cur_width = nLink->bitWidth;
 if (mType == TO_LINK_) {
 target_width = nLink->bitWidth;
 cur_width = bitWidth;
 }

-DPRINTF(RubyNetwork, "Target width: %d Current: %d Native: %d\n",
-target_width, cur_width, bitWidth);
+DPRINTF(RubyNetwork, "Target width: %d Current: %d\n",
+target_width, cur_width);
 assert(target_width != cur_width);

 int vc = t_flit->get_vc();
@@ -134,12 +134,17 @@
 int num_flits = 0;
 if (t_flit->get_type() == CREDIT_) {
 num_flits =  
(int)ceil((float)target_width/(float)cur_width);

+} else if (t_flit->get_type() == TAIL_ ||
+   t_flit->get_type() == HEAD_TAIL_) {
+num_flits = 1;
 } else {
-num_flits =  
(int)ceil((float)t_flit->msgSize/(float)cur_width);

+num_flits = (int)ceil((float)std::min(t_flit->msgSize,
+   target_width)/(float)cur_width);
 }
 assert(num_flits > 0);

-DPRINTF(RubyNetwork, "Deserialize :%d -> %d num:%d  
vc:%d\n",

+DPRINTF(RubyNetwork, "Deserialize :%d -> %d "
+"num-flits-needed:%d vc:%d\n",
 cur_width, target_width, num_flits, vc);

 // lenBuffer acts as the buffer for deserialization
@@ -154,6 +159,7 @@

 // Schedule only if we are done deserializing
 if (fl) {
+DPRINTF(RubyNetwork, "Scheduling a flit\n");
 lenBuffer[vc] = 0;
 scheduleFlit(fl, serDesLatency);
 }
@@ -161,8 +167,9 @@
 delete t_flit;
 } else {
 // Serialize
-DPRINTF(RubyNetwork, "Serialize :%d -> %d vc:%d\n",
-cur_width, target_width);
+DPRINTF(RubyNetwork, "Serializing flit :%d -> %d "
+"(vc:%d, Original Message Size: %d)\n",
+cur_width, target_width, vc, t_flit->msgSize);

 int num_parts = 0;
 if (t_flit->get_type() == CREDIT_) {
@@ -170,11 +177,12 @@
 num_parts = extraCredit[vc].front();
 extraCredit[vc].pop();
 } else {
-num_parts = (int)ceil((float)t_flit->msgSize/
+num_parts = (int)ceil((float)cur_width/
 (float)target_width);
 }
 assert(num_parts > 0);

+DPRINTF(RubyNetwork, "Serialized into %d parts\n", num_parts);
 // Schedule all the flits
 // num_flits could be zero for credits
 for (int i = 0; i < num_parts; i++) {
@@ -201,6 +209,7 @@

 if (link_srcQueue->isReady(curTick())) {
 t_flit = link_srcQueue->getTopFlit();
+DPRINTF(RubyNetwork, "Recieved flit %s\n", *t_flit);
 flitisizeAndSend(t_flit);
 return;
 }
diff --git a/src/mem/ruby/network/garnet2.0/OutputUnit.cc  
b/src/mem/ruby/network/garnet2.0/OutputUnit.cc

index 787514f..d342eb1 100644
--- a/src/mem/ruby/network/garnet2.0/OutputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/OutputUnit.cc
@@ -51,12 +51,11 @@
 void
 OutputUnit::decrement_credit(int out_vc)
 {
-DPRINTF(RubyNetwork, "Router %d OutputUnit %d decrementing credit:%d  
for "

-"outvc %d at time: %lld for %s\n",
-m_router->get_id(), m_id,
-outVcState[out_vc].get_credit_count(),
-out_vc, m_router->curCycle(),
-m_credit_link->name());
+DPRINTF(RubyNetwork, "Router %d OutputUnit %s decrementing credit:%d  
for "

+"outvc %d at time: %lld for %s\n", m_router->get_id(),
+

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Revamp SerDes execution.

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32298 )



Change subject: mem-garnet: Revamp SerDes execution.
..

mem-garnet: Revamp SerDes execution.

Earlier type of modelling creates problems when deserializing
to non-multiple ratios. This change upgrades serdes to serialize
and deserialize to exact message sizes. This commit also
fixes some debug messages within garnet.

Change-Id: I9606af75943f69fc97a768113f03e997cac92e0f
---
M src/mem/ruby/network/garnet2.0/Credit.cc
M src/mem/ruby/network/garnet2.0/Credit.hh
M src/mem/ruby/network/garnet2.0/NetworkBridge.cc
M src/mem/ruby/network/garnet2.0/NetworkBridge.hh
M src/mem/ruby/network/garnet2.0/flit.cc
M src/mem/ruby/network/garnet2.0/flit.hh
6 files changed, 102 insertions(+), 40 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/Credit.cc  
b/src/mem/ruby/network/garnet2.0/Credit.cc

index 7c293cf..7619079 100644
--- a/src/mem/ruby/network/garnet2.0/Credit.cc
+++ b/src/mem/ruby/network/garnet2.0/Credit.cc
@@ -63,10 +63,20 @@
 // So send a credit in any case
 return new Credit(m_vc, true, m_time);
 }
-if (des_id % num_flits) {
-return NULL;
-}

 return new Credit(m_vc, false, m_time);
 }

+void
+Credit::print(std::ostream& out) const
+{
+out << "[Credit:: ";
+out << "Type=" << m_type << " ";
+out << "VC=" << m_vc << " ";
+out << "FreeVC=" << m_is_free_signal << " ";
+out << "Set Time=" << m_time << " ";
+out << "]";
+}
+
+
+
diff --git a/src/mem/ruby/network/garnet2.0/Credit.hh  
b/src/mem/ruby/network/garnet2.0/Credit.hh

index ea5aee7..1f3c347 100644
--- a/src/mem/ruby/network/garnet2.0/Credit.hh
+++ b/src/mem/ruby/network/garnet2.0/Credit.hh
@@ -53,6 +53,7 @@
 // Functions used by SerDes
 flit* serialize(int ser_id, int parts, uint32_t bWidth);
 flit* deserialize(int des_id, int num_flits, uint32_t bWidth);
+void print(std::ostream& out) const;

 ~Credit() {};

diff --git a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc  
b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc

index 0073c65..1cf560f 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
@@ -50,6 +50,7 @@

 cdcLatency = p->cdc_latency;
 serDesLatency = p->serdes_latency;
+lastScheduledAt = 0;

 nLink = p->link;
 if (mType == FROM_LINK_) {
@@ -64,6 +65,8 @@
 }

 lenBuffer.resize(p->vcs_per_vnet * p->virt_nets);
+sizeSent.resize(p->vcs_per_vnet * p->virt_nets);
+flitsSent.resize(p->vcs_per_vnet * p->virt_nets);
 extraCredit.resize(p->vcs_per_vnet * p->virt_nets);
 }

@@ -96,9 +99,14 @@
 totLatency = latency + cdcLatency;
 }

-t_flit->set_time(link_consumer->getObject()->clockEdge(totLatency));
+Tick sendTime = link_consumer->getObject()->clockEdge(totLatency);
+Tick nextAvailTick = lastScheduledAt + link_consumer->getObject()->\
+cyclesToTicks(Cycles(1));
+sendTime = std::max(nextAvailTick, sendTime);
+t_flit->set_time(sendTime);
+lastScheduledAt = sendTime;
 linkBuffer.insert(t_flit);
-link_consumer->scheduleEvent(totLatency);
+link_consumer->scheduleEventAbsolute(sendTime);
 }

 void
@@ -130,29 +138,52 @@
 // Deserialize
 // This deserializer combines flits from the
 // same message together
-// TODO: Allow heterogenous flits
 int num_flits = 0;
+int flitPossible = 0;
 if (t_flit->get_type() == CREDIT_) {
-num_flits =  
(int)ceil((float)target_width/(float)cur_width);

+lenBuffer[vc]++;
+assert(extraCredit[vc].front());
+if (lenBuffer[vc] == extraCredit[vc].front()) {
+flitPossible = 1;
+extraCredit[vc].pop();
+lenBuffer[vc] = 0;
+}
 } else if (t_flit->get_type() == TAIL_ ||
t_flit->get_type() == HEAD_TAIL_) {
-num_flits = 1;
+// If its the end of packet, then send whatever
+// is available.
+int sizeAvail = (t_flit->msgSize - sizeSent[vc]);
+flitPossible = ceil((float)sizeAvail/(float)target_width);
+assert (flitPossible < 2);
+num_flits = (t_flit->get_id() + 1) - flitsSent[vc];
+// Stop tracking the packet.
+flitsSent[vc] = 0;
+sizeSent[vc] = 0;
 } else {
-num_flits = (int)ceil((float)std::min(t_flit->msgSize,
-   target_width)/(float)cur_width);
+// If we are yet to receive the complete packet
+// track the size recieved and flits deserialized.
+int sizeAvail =
+

[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Wakeup Router instead of input unit within router

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32297 )



Change subject: mem-garnet: Wakeup Router instead of input unit within  
router

..

mem-garnet: Wakeup Router instead of input unit within router

This fixes a wakeup call within router. Input Unit is not
supposed to wake up on its own. In case there is another
flit in the pipeline towards the input unit of a router,
it should wakeup the entire Router to process it in the
next possible cycle.

Change-Id: If0ad5c75379cd4ae513b32e27ea821db76eb49f6
---
M src/mem/ruby/network/garnet2.0/InputUnit.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/network/garnet2.0/InputUnit.cc  
b/src/mem/ruby/network/garnet2.0/InputUnit.cc

index 7df296c..db24aef 100644
--- a/src/mem/ruby/network/garnet2.0/InputUnit.cc
+++ b/src/mem/ruby/network/garnet2.0/InputUnit.cc
@@ -127,7 +127,7 @@
 }

 if (m_in_link->isReady(curTick())) {
-scheduleEvent(Cycles(1));
+m_router->schedule_wakeup(Cycles(1));
 }
 }
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: If0ad5c75379cd4ae513b32e27ea821db76eb49f6
Gerrit-Change-Number: 32297
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Fix scheduling time for CDC

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Srikant Bharadwaj has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32294 )



Change subject: mem-garnet: Fix scheduling time for CDC
..

mem-garnet: Fix scheduling time for CDC

CDC does not wakeup a consumer according to its time.
Instead it was waking up the consumer according to CDC's
clock domain which creates bugs when CDCs are at set at the
source. This patch fixes that problem.

Change-Id: Id186a518c76909a4111ca524d3b392048ff3a2be
---
M src/mem/ruby/common/Consumer.hh
M src/mem/ruby/network/garnet2.0/NetworkBridge.cc
2 files changed, 8 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/common/Consumer.hh  
b/src/mem/ruby/common/Consumer.hh

index 3688021..c4332cf 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -81,6 +81,13 @@
 return sem->name();
 }

+ClockedObject *
+getObject()
+{
+return em;
+}
+
+
 void scheduleEventAbsolute(Tick timeAbs);
 void scheduleEvent(Cycles timeDelta);

diff --git a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc  
b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc

index 7438dd9..3c834d9 100644
--- a/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
+++ b/src/mem/ruby/network/garnet2.0/NetworkBridge.cc
@@ -96,7 +96,7 @@
 totLatency = latency + cdcLatency;
 }

-t_flit->set_time(clockEdge(totLatency));
+t_flit->set_time(link_consumer->getObject()->clockEdge(totLatency));
 linkBuffer.insert(t_flit);
 link_consumer->scheduleEvent(totLatency);
 }

--
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Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: Id186a518c76909a4111ca524d3b392048ff3a2be
Gerrit-Change-Number: 32294
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Gerrit-Owner: Srikant Bharadwaj 
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[gem5-dev] Change in gem5/gem5[feature-heterogarnet]: mem-garnet: Initialize unused Credit members

[Srikant Bharadwaj (Gerrit) via gem5-dev]

Hello Michael LeBeane,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/32296

to review the following change.


Change subject: mem-garnet: Initialize unused Credit members
..

mem-garnet: Initialize unused Credit members

The Credit class doesn't initialize a number of its unused base class
fields.  This leads to non-determanistic traces when printing flits that
are Credits.  This patch initializes all unused fields to 0.

Change-Id: Ib73c652c71a10be57b24c0d6e1ac22eafa421e11
---
M src/mem/ruby/network/garnet2.0/CommonTypes.hh
M src/mem/ruby/network/garnet2.0/Credit.cc
2 files changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/network/garnet2.0/CommonTypes.hh  
b/src/mem/ruby/network/garnet2.0/CommonTypes.hh

index 72febed..bc80131 100644
--- a/src/mem/ruby/network/garnet2.0/CommonTypes.hh
+++ b/src/mem/ruby/network/garnet2.0/CommonTypes.hh
@@ -47,6 +47,11 @@

 struct RouteInfo
 {
+RouteInfo()
+: vnet(0), src_ni(0), src_router(0), dest_ni(0), dest_router(0),
+  hops_traversed(0)
+{}
+
 // destination format for table-based routing
 int vnet;
 NetDest net_dest;
diff --git a/src/mem/ruby/network/garnet2.0/Credit.cc  
b/src/mem/ruby/network/garnet2.0/Credit.cc

index 868f622..7c293cf 100644
--- a/src/mem/ruby/network/garnet2.0/Credit.cc
+++ b/src/mem/ruby/network/garnet2.0/Credit.cc
@@ -35,11 +35,9 @@
 // and m_is_free_signal (whether VC is free or not)

 Credit::Credit(int vc, bool is_free_signal, Tick curTime)
+: flit(0, vc, 0, RouteInfo(), 0, nullptr, 0, 0, curTime)
 {
-m_id = 0;
-m_vc = vc;
 m_is_free_signal = is_free_signal;
-m_time = curTime;
 m_type = CREDIT_;
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: feature-heterogarnet
Gerrit-Change-Id: Ib73c652c71a10be57b24c0d6e1ac22eafa421e11
Gerrit-Change-Number: 32296
Gerrit-PatchSet: 1
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Michael LeBeane 
Gerrit-MessageType: newchange
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