[gem5-dev] Build failed in Jenkins: Nightly #118

2020-11-03 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[gabe.black] arch: Clean up the __init__s in (Sub)OperandList.

[davide.basilio.bartolini] configs: Do not require default options for caches

[giacomo.travaglini] cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual 
methods

[giacomo.travaglini] arch-arm: Add el2Enabled cached variable

[giacomo.travaglini] arch-arm: Fix implementation of TLBI_VMALL instructions

[giacomo.travaglini] arch-arm: TlbEntry flush to be considered as functional 
lookup

[giacomo.travaglini] arch-arm: Do not use _flushMva for TLBI IPA

[yuhsingw] configs: Add dtb-gen to fs_bigLITTLE.py


--
[...truncated 68.77 KB...]
 [SO PARAM] DMA_Controller -> MIPS/params/DMA_Controller.hh
 [MAKE INC] MIPS/mem/ruby/common/BoolVec.hh -> protocol/BoolVec.hh
 [MAKE INC] MIPS/mem/ruby/structures/CacheMemory.hh -> protocol/CacheMemory.hh
 [MAKE INC] MIPS/mem/ruby/system/DMASequencer.hh -> protocol/DMASequencer.hh
 [MAKE INC] MIPS/mem/ruby/structures/DirectoryMemory.hh -> 
protocol/DirectoryMemory.hh
 [MAKE INC] MIPS/mem/ruby/system/HTMSequencer.hh -> protocol/HTMSequencer.hh
 [SO PARAM] RubyPrefetcher -> MIPS/params/RubyPrefetcher.hh
 [MAKE INC] MIPS/mem/ruby/structures/RubyPrefetcher.hh -> 
protocol/RubyPrefetcher.hh
 [MAKE INC] MIPS/mem/ruby/system/Sequencer.hh -> protocol/Sequencer.hh
 [MAKE INC] MIPS/mem/ruby/common/Set.hh -> protocol/Set.hh
 [MAKE INC] MIPS/mem/ruby/structures/TimerTable.hh -> protocol/TimerTable.hh
 [SO PARAM] RubyWireBuffer -> MIPS/params/RubyWireBuffer.hh
 [MAKE INC] MIPS/mem/ruby/structures/WireBuffer.hh -> protocol/WireBuffer.hh
 [MAKE INC] MIPS/mem/ruby/common/WriteMask.hh -> protocol/WriteMask.hh
 [MAKE INC] MIPS/mem/ruby/slicc_interface/AbstractCacheEntry.hh -> 
protocol/AbstractCacheEntry.hh
 [ CXX] MIPS/mem/ruby/protocol/DMA_Controller.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_Event.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_State.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_TBE.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DMA_Wakeup.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/DirectoryRequestType.cc -> .o
 [SO PARAM] Directory_Controller -> MIPS/params/Directory_Controller.hh
 [ CXX] MIPS/mem/ruby/protocol/Directory_Controller.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Entry.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Event.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_State.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_TBE.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/Directory_Wakeup.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/HtmCallbackMode.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/HtmFailedInCacheReason.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/InvalidateGeneratorStatus.cc -> .o
 [SO PARAM] L1Cache_Controller -> MIPS/params/L1Cache_Controller.hh
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Controller.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Entry.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Event.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_State.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_TBE.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Transitions.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/L1Cache_Wakeup.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/LinkDirection.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/LockStatus.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MachineType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MaskPredictorIndex.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MaskPredictorTraining.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MaskPredictorType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MemoryControlRequestType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MemoryMsg.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MemoryRequestType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/MessageSizeType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/PrefetchBit.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/RequestMsg.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/RequestStatus.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/ResponseMsg.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/RubyAccessMode.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/RubyRequestType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/SequencerMsg.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/SequencerRequestType.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/SequencerStatus.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/SeriesRequestGeneratorStatus.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/TesterStatus.cc -> .o
 [ CXX] MIPS/mem/ruby/protocol/TransitionResult.cc -> .o
 [ CXX] MIPS/arch/generic/htm.cc -> .o
 [SO PARAM] BaseMMU -> MIPS/params/BaseMMU.hh
 [SO PARAM] BaseTLB -> MIPS/params/BaseTLB.hh
 [ CXX] MIPS/arch/generic/mmu.cc -> .o
 [GENERATE] mips -> MIPS/arch/decoder.hh
 [ CXX]

[gem5-dev] Change in gem5/gem5[develop]: mips: Fix the build after the MMU changes.

2020-11-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36995 )



Change subject: mips: Fix the build after the MMU changes.
..

mips: Fix the build after the MMU changes.

Change-Id: I2bd1a6a8607fe1da056182ca840036db35b53c36
---
M src/arch/mips/isa/decoder.isa
M src/arch/mips/isa/includes.isa
2 files changed, 5 insertions(+), 4 deletions(-)



diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 3b2b015..e5613f5 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -738,7 +738,7 @@
 0x01: tlbr({{
 MipsISA::PTE *PTEntry =
 dynamic_cast(
-xc->tcBase()->getITBPtr())->
+xc->tcBase()->getMMUPtr()->itb)->
 getEntry(Index & 0x7FFF);
 if (PTEntry == NULL) {
 fatal("Invalid PTE Entry received on "
@@ -819,7 +819,7 @@
 (1 << newEntry.AddrShiftAmount) - 1;

 auto ptr = dynamic_cast(
-xc->tcBase()->getITBPtr());
+xc->tcBase()->getMMUPtr()->itb);
 Config3Reg config3 = Config3;
 PageGrainReg pageGrain = PageGrain;
 int SP = 0;
@@ -885,7 +885,7 @@
 (1 << newEntry.AddrShiftAmount) - 1;

 auto ptr = dynamic_cast(
-xc->tcBase()->getITBPtr());
+xc->tcBase()->getMMUPtr()->itb);
 Config3Reg config3 = Config3;
 PageGrainReg pageGrain = PageGrain;
 int SP = 0;
@@ -909,7 +909,7 @@
 vpn = ((EntryHi >> 11) & 0xFFFC);
 }
 tlbIndex = dynamic_cast(
-xc->tcBase()->getITBPtr())->
+xc->tcBase()->getMMUPtr()->itb)->
 probeEntry(vpn, entryHi.asid);
 // Check TLB for entry matching EntryHi
 if (tlbIndex != -1) {
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 53b1055..34922e4 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -76,6 +76,7 @@
 #include "arch/mips/dt_constants.hh"
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/mmu.hh"
 #include "arch/mips/mt.hh"
 #include "arch/mips/mt_constants.hh"
 #include "arch/mips/pagetable.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2bd1a6a8607fe1da056182ca840036db35b53c36
Gerrit-Change-Number: 36995
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arm: Get rid of some unused instruction templates.

2020-11-03 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36975 )



Change subject: arm: Get rid of some unused instruction templates.
..

arm: Get rid of some unused instruction templates.

These were defined but not used.

Change-Id: Ib81e86c8b8640e2f47ff7ad84d287367462e04a5
---
M src/arch/arm/isa/templates/branch.isa
M src/arch/arm/isa/templates/macromem.isa
2 files changed, 0 insertions(+), 95 deletions(-)



diff --git a/src/arch/arm/isa/templates/branch.isa  
b/src/arch/arm/isa/templates/branch.isa

index f8f1c6a..cccd67f 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -35,34 +35,6 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-def template BranchImmDeclare {{
-class %(class_name)s : public %(base_class)s
-{
-public:
-// Constructor
-%(class_name)s(ExtMachInst machInst, int32_t _imm);
-Fault execute(ExecContext *, Trace::InstRecord *) const override;
-};
-}};
-
-def template BranchImmConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst,
-  int32_t _imm)
-: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
-{
-%(constructor)s;
-if (!(condCode == COND_AL || condCode == COND_UC)) {
-for (int x = 0; x < _numDestRegs; x++) {
-setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
-}
-flags[IsCondControl] = true;
-} else {
-flags[IsUncondControl] = true;
-}
-
-}
-}};
-
 def template BranchImmCondDeclare {{
 class %(class_name)s : public %(base_class)s
 {
@@ -98,35 +70,6 @@
 }
 }};

-def template BranchRegDeclare {{
-class %(class_name)s : public %(base_class)s
-{
-public:
-// Constructor
-%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
-Fault execute(ExecContext *, Trace::InstRecord *) const override;
-};
-}};
-
-def template BranchRegConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst,
-  IntRegIndex _op1)
-: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
-{
-%(constructor)s;
-if (!(condCode == COND_AL || condCode == COND_UC)) {
-for (int x = 0; x < _numDestRegs; x++) {
-setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
-}
-flags[IsCondControl] = true;
-} else {
-flags[IsUncondControl] = true;
-}
-if (%(is_ras_pop)s)
-flags[IsReturn] = true;
-}
-}};
-
 def template BranchRegCondDeclare {{
 class %(class_name)s : public %(base_class)s
 {
@@ -159,17 +102,6 @@
 }
 }};

-def template BranchRegRegDeclare {{
-class %(class_name)s : public %(base_class)s
-{
-public:
-// Constructor
-%(class_name)s(ExtMachInst machInst,
-   IntRegIndex _op1, IntRegIndex _op2);
-Fault execute(ExecContext *, Trace::InstRecord *) const override;
-};
-}};
-
 def template BranchTableDeclare {{
 class %(class_name)s : public %(base_class)s
 {
diff --git a/src/arch/arm/isa/templates/macromem.isa  
b/src/arch/arm/isa/templates/macromem.isa

index 6cd25d8..0eb918e 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -183,33 +183,6 @@
 // Integer = Integer op Integer microops
 //

-def template MicroIntDeclare {{
-class %(class_name)s : public %(base_class)s
-{
-  public:
-%(class_name)s(ExtMachInst machInst,
-   RegIndex _ura, RegIndex _urb, RegIndex _urc);
-Fault execute(ExecContext *, Trace::InstRecord *) const override;
-};
-}};
-
-def template MicroIntConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst,
-   RegIndex _ura,
-   RegIndex _urb,
-   RegIndex _urc)
-: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- _ura, _urb, _urc)
-{
-%(constructor)s;
-if (!(condCode == COND_AL || condCode == COND_UC)) {
-for (int x = 0; x < _numDestRegs; x++) {
-setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
-}
-}
-}
-}};
-
 def template MicroNeonMemExecDeclare {{
 template
 Fault %(class_name)s<%(targs)s>::execute(

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib81e86c8b8640e2f47ff7ad84d287367462e04a5
Gerrit-Change-Number: 36975
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black

[gem5-dev] Change in gem5/gem5[develop]: configs: Add dtb-gen to fs_bigLITTLE.py

2020-11-03 Thread Yu-hsin Wang (Gerrit) via gem5-dev 
Yu-hsin Wang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36955 )


Change subject: configs: Add dtb-gen to fs_bigLITTLE.py
..

configs: Add dtb-gen to fs_bigLITTLE.py

Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36955
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 29f5c6b..76de0eb 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -213,6 +213,8 @@
  "only parameters of its children.")
 parser.add_argument("--vio-9p", action="store_true",
 help=Options.vio_9p_help)
+parser.add_argument("--dtb-gen", action="store_true",
+help="Doesn't run simulation, it generates a DTB  
only")

 return parser

 def build(options):
@@ -367,6 +369,10 @@
 sys.exit(event.getCode())


+def generateDtb(root):
+root.system.generateDtb(os.path.join(m5.options.outdir, "system.dtb"))
+
+
 def main():
 parser = argparse.ArgumentParser(
 description="Generic ARM big.LITTLE configuration")
@@ -375,7 +381,10 @@
 root = build(options)
 root.apply_config(options.param)
 instantiate(options)
-run()
+if options.dtb_gen:
+  generateDtb(root)
+else:
+  run()


 if __name__ == "__m5_main__":

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
Gerrit-Change-Number: 36955
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Yu-hsin Wang 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] PCID feature in x86

2020-11-03 Thread Gabe Black via gem5-dev 
Hi folks. I have seen a couple series of changes adding support for the
PCID feature in x86, as far as I can tell a new feature in the ISA (within
the last year?) which lets you set a context ID for mappings.

While I don't think there's anything wrong with adding support for this
feature, I'd like to know if we're doing that just to support it (which is
valid), or if there's some mechanical problem in gem5 it's supposed to
solve. I ask because I remember seeing something talking about how this was
necessary for having multiple processes or SMT in x86, and I don't think
that's true. This will make those cases perhaps perform better since the
TLB won't have to be flushed as aggressively if processes are moved around
between contexts (which doesn't usually happen in SE mode), but the CR3 for
each (the root page table pointer) should be different since each should
have its own set of page tables, and so everybody should see their own view
of virtual memory without any extra help.

Please fill in any extra context so that we can be sure we're fixing the
right problem, and not just side stepping a deeper issue with this. To be
clear, having this feature for its own sake is fine, I just want to make
sure we know we're doing that if we are!

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: misc: Update maintainers file

2020-11-03 Thread Jason Lowe-Power (Gerrit) via gem5-dev 
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36886 )



Change subject: misc: Update maintainers file
..

misc: Update maintainers file

Change-Id: I19810801f0acd5a35dde59a70166339e00b97eca
Signed-off-by: Jason Lowe-Power 
---
M MAINTAINERS
1 file changed, 51 insertions(+), 22 deletions(-)



diff --git a/MAINTAINERS b/MAINTAINERS
index 913daaf..61488fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6,15 +6,18 @@
 when you upload the patch to Gerrit (https://gem5-review.googlesource.com).
 These keywords mostly follow the directory structure.

-Individuals on the project management committee are maintainers for all of  
the

-gem5 components (i.e., they can review any patch as the maintainer). These
-individuals are required to review any patches to components without  
explicit

-maintainers.
+Maintainers have the following responsibilities:
+1. That at least one maintainer of each subsystem reviews all changes to  
that

+   subsystem (they will be automatically tagged and emailed on each new
+   change).
+2. They will complete your reviews in a timely manner (within a few  
business

+   days).
+3. They pledge to uphold gem5's community standards and its code of  
conduct by
+   being polite and professional in their code reviews. See  
CODE-OF-CONDUCT.md.


 PMC Members (general maintainers):
-  Ali Saidi 
   Andreas Sandberg 
-  Brad Beckmann 
+  Brad Beckmann 
   David Wood 
   Gabe Black 
   Giacomo Travaglini 
@@ -31,63 +34,86 @@
 arch-gcn3:
   Tony Gutierrez 
 arch-mips:
+  UNSUPPORTED
 arch-power:
+  Boris Shingarov 
 arch-riscv:
-  Alec Roelke 
+  UNSUPPORTED
 arch-sparc:
   Gabe Black 
 arch-x86:
   Gabe Black 

 base:
+  Bobby Bruce 

 configs:
   Jason Lowe-Power 

-cpu: General changes to all CPU models (e.g., BaseCPU)
+cpu: General changes to all CPU models (e.g., BzaseCPU)
+  Gabe Black 
+  Jason Lowe-Power 
 cpu-kvm:
   Andreas Sandberg 
 cpu-minor:
+  Zhengrong Wang 
 cpu-o3:
+  UNSUPPORTED
 cpu-simple:
+  Jason Lowe-Power 
+  Gabe Black 

 dev:
+  Gabe Black 
 dev-hsa:
-  Tony Gutierrez 
+  UNSUPPORTED
 dev-virtio:
   Andreas Sandberg 
-
 dev-arm:
   Andreas Sandberg 
   Giacomo Travaglini 

+doc:
+  Bobby Bruce 
+
 ext: Components external to gem5
+  Bobby Bruce 
+  Jason Lowe-Power 
+ext-testlib:
+  Bobby Bruce 
+  Hoa Nguyen 

 fastmodel: Changes relating to ARM Fast Models
   Gabe Black 

 gpu-compute:
-  Tony Gutierrez 
   Matt Poremba 

-learning-gem5: The code and configs for the Learning gem5 book (see
-   learning.gem5.com)
+learning-gem5: The code and configs for the Learning gem5 book
   Jason Lowe-Power 

 mem: General memory system (e.g., XBar, Packet)
   Nikos Nikoleris 
 mem-cache: Classic caches and coherence
   Nikos Nikoleris 
+mem-dram:
+  Nikos Nikoleris 
 mem-garnet: Garnet subcomponent of Ruby
-  Tushar Krishna 
+  Srikant Bharadwaj 
 mem-ruby: Ruby structures and protocols
-  Brad Beckmann 
   Jason Lowe-Power 

 misc: Anything outside of the other categories
+  Bobby Bruce 
+  Jason Lowe-Power 

 python: Python SimObject wrapping and infrastructure
   Andreas Sandberg 
+  Jason Lowe-Power 
+
+resources: The gem5-resources repo with auxiliary resources for simulation
+  Bobby Bruce 
+  Jason Lowe-Power 

 scons: Build system
   Gabe Black 
@@ -95,13 +121,8 @@
 sim: General simulation components
   Jason Lowe-Power 
 sim-se: Syscall emulation
-  Brandon Potter 
-sim-power: Power modeling
-  Andreas Sandberg 
+  UNSUPPORTED

-stats: Updates to statistics for regressions
-
-system: System boot code and related components
 system-arm:
   Andreas Sandberg 
   Giacomo Travaglini 
@@ -109,8 +130,16 @@
 systemc: Code for the gem5 SystemC implementation and interface
   Gabe Black 

-tests: testing changes (not stats updates for tests. See stats:)
+tests: testing changes
   Bobby Bruce 

 util:
   Gabe Black 
+util-docker:
+  Bobby Bruce 
+util-m5:
+  Gabe Black 
+
+website: The gem5-website repo which contains the gem5.org site
+  Bobby Bruce 
+  Hoa Nguyen 

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Gerrit-Branch: develop
Gerrit-Change-Id: I19810801f0acd5a35dde59a70166339e00b97eca
Gerrit-Change-Number: 36886
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Gerrit-Owner: Jason Lowe-Power 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add parent SimObject to constructor of SMMUv3 classes

2020-11-03 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36885 )



Change subject: dev-arm: Add parent SimObject to constructor of SMMUv3  
classes

..

dev-arm: Add parent SimObject to constructor of SMMUv3 classes

SMMUv3BaseCache and the derived classes and SMMUv3DeviceInterface
constructors need the reference to the corresponding parent
SimObject to bind the stats of the cache to the parent's stats.

Change-Id: I7a99f7288d39b0ce0b4548c1bfebcd4b522f2772
Signed-off-by: Hoa Nguyen 
---
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_caches.hh
M src/dev/arm/smmu_v3_deviceifc.cc
M src/dev/arm/smmu_v3_deviceifc.hh
4 files changed, 22 insertions(+), 17 deletions(-)



diff --git a/src/dev/arm/smmu_v3_caches.cc b/src/dev/arm/smmu_v3_caches.cc
index a56b8a3..fd103a7 100644
--- a/src/dev/arm/smmu_v3_caches.cc
+++ b/src/dev/arm/smmu_v3_caches.cc
@@ -58,7 +58,8 @@
  * TODO: move more code into this base class to reduce duplication.
  */

-SMMUv3BaseCache::SMMUv3BaseCache(const std::string _name, uint32_t  
seed) :
+SMMUv3BaseCache::SMMUv3BaseCache(const std::string _name, uint32_t  
seed,

+ SimObject *parent) :
 replacementPolicy(decodePolicyName(policy_name)),
 nextToReplace(0),
 random(seed),
@@ -144,9 +145,9 @@
  */

 SMMUTLB::SMMUTLB(unsigned numEntries, unsigned _associativity,
- const std::string )
+ const std::string , SimObject *parent)
 :
-SMMUv3BaseCache(policy, SMMUTLB_SEED),
+SMMUv3BaseCache(policy, SMMUTLB_SEED, parent),
 associativity(_associativity)
 {
 if (associativity == 0)
@@ -424,9 +425,9 @@
  */

 ARMArchTLB::ARMArchTLB(unsigned numEntries, unsigned _associativity,
-   const std::string )
+   const std::string , SimObject *parent)
 :
-SMMUv3BaseCache(policy, ARMARCHTLB_SEED),
+SMMUv3BaseCache(policy, ARMARCHTLB_SEED, parent),
 associativity(_associativity)
 {
 if (associativity == 0)
@@ -623,9 +624,9 @@
  */

 IPACache::IPACache(unsigned numEntries, unsigned _associativity,
-   const std::string )
+   const std::string , SimObject *parent)
 :
-SMMUv3BaseCache(policy, IPACACHE_SEED),
+SMMUv3BaseCache(policy, IPACACHE_SEED, parent),
 associativity(_associativity)
 {
 if (associativity == 0)
@@ -967,8 +968,9 @@
  */

 WalkCache::WalkCache(const std::array  
&_sizes,

- unsigned _associativity, const std::string ) :
-SMMUv3BaseCache(policy, WALKCACHE_SEED),
+ unsigned _associativity, const std::string ,
+ SimObject *parent) :
+SMMUv3BaseCache(policy, WALKCACHE_SEED, parent),
 associativity(_associativity),
 sizes()
 {
diff --git a/src/dev/arm/smmu_v3_caches.hh b/src/dev/arm/smmu_v3_caches.hh
index 0dfab72..a2bdf73 100644
--- a/src/dev/arm/smmu_v3_caches.hh
+++ b/src/dev/arm/smmu_v3_caches.hh
@@ -81,7 +81,8 @@
 static int decodePolicyName(const std::string _name);

   public:
-SMMUv3BaseCache(const std::string _name, uint32_t seed);
+SMMUv3BaseCache(const std::string _name, uint32_t seed,
+SimObject *parent);
 virtual ~SMMUv3BaseCache() {}

 virtual void regStats(const std::string );
@@ -118,7 +119,7 @@
 };

 SMMUTLB(unsigned numEntries, unsigned _associativity,
-const std::string );
+const std::string , SimObject *parent);
 SMMUTLB(const SMMUTLB& tlb) = delete;
 virtual ~SMMUTLB() {}

@@ -167,7 +168,7 @@
 };

 ARMArchTLB(unsigned numEntries, unsigned _associativity,
-   const std::string );
+   const std::string , SimObject *parent);
 virtual ~ARMArchTLB() {}

 const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid,
@@ -210,7 +211,7 @@
 };

 IPACache(unsigned numEntries, unsigned _associativity,
- const std::string );
+ const std::string , SimObject *parent);
 virtual ~IPACache() {}

 const Entry *lookup(Addr ipa, uint16_t vmid, bool updStats=true);
@@ -258,7 +259,7 @@
 };

 ConfigCache(unsigned numEntries, unsigned _associativity,
-const std::string );
+const std::string , SimObject *parent);
 virtual ~ConfigCache() {}

 const Entry *lookup(uint32_t sid, uint32_t ssid, bool updStats=true);
@@ -301,7 +302,8 @@
 };

 WalkCache(const std::array &_sizes,
-  unsigned _associativity, const std::string );
+  unsigned _associativity, const std::string ,
+  SimObject *parent);
 virtual ~WalkCache() {}

 const Entry *lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid,
diff --git a/src/dev/arm/smmu_v3_deviceifc.cc  
b/src/dev/arm/smmu_v3_deviceifc.cc

index 985ca17..035bd52 100644
--- a/src/dev/arm/smmu_v3_deviceifc.cc
+++

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Do not use _flushMva for TLBI IPA

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35246 )


Change subject: arch-arm: Do not use _flushMva for TLBI IPA
..

arch-arm: Do not use _flushMva for TLBI IPA

This is just a cosmetic change

Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35246
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.hh
2 files changed, 10 insertions(+), 2 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 04b5cd4..5d2ed90 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -463,8 +463,9 @@
 TLB::flush(const TLBIIPA _op)
 {
 assert(!isStage2);
-stage2Tlb->_flushMva(tlbi_op.addr, 0xbeef, tlbi_op.secureLookup,
-true, tlbi_op.targetEL, false);
+
+// Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
+stage2Tlb->flush(tlbi_op.makeStage2());
 }

 void
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index cab0e52..ce72dfb 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -292,6 +292,13 @@

 void operator()(ThreadContext* tc) override;

+/** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
+TLBIMVAA
+makeStage2() const
+{
+return TLBIMVAA(EL1, secureLookup, addr);
+}
+
 Addr addr;
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Gerrit-Change-Number: 35246
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add el2Enabled cached variable

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35242 )


Change subject: arch-arm: Add el2Enabled cached variable
..

arch-arm: Add el2Enabled cached variable

Several TLB invalidation instructions rely on VMID matching.  This is
only applicable is EL2 is implemented and enabled in the current state.

The code prior to this patch was making the now invalid assumption that
we shouldn't consider the VMID if we are doing a secure lookup. This is
because in the past if we were in secure mode we were sure EL2 was not
enabled.
This is fishy and not valid anymore anyway after the introduction of
secure EL2.

Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35242
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
4 files changed, 15 insertions(+), 6 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 3607c29..1866319 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1803,7 +1803,6 @@
   // VAEx(IS) and VALEx(IS) are the same because TLBs
   // only store entries
   // from the last level of translation table walks
-  // @todo: handle VMID to enable Virtualization
   // AArch64 TLB Invalidate by VA, EL3
   case MISCREG_TLBI_VAE3_Xt:
   case MISCREG_TLBI_VALE3_Xt:
@@ -1895,7 +1894,6 @@
 return;
 }
   // AArch64 TLB Invalidate by ASID, EL1
-  // @todo: handle VMID to enable Virtualization
   case MISCREG_TLBI_ASIDE1_Xt:
 {
 assert64();
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 0e61186..38aa38e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -281,7 +281,7 @@
 const bool el_match = te->checkELMatch(
 tlbi_op.targetEL, tlbi_op.inHost);
 if (te->valid && tlbi_op.secureLookup == !te->nstid &&
-(te->vmid == vmid || tlbi_op.secureLookup) && el_match) {
+(te->vmid == vmid || tlbi_op.el2Enabled) && el_match) {

 DPRINTF(TLB, " -  %s\n", te->print());
 te->valid = false;
@@ -383,7 +383,7 @@
 te = [x];
 if (te->valid && te->asid == tlbi_op.asid &&
 tlbi_op.secureLookup == !te->nstid &&
-(te->vmid == vmid || tlbi_op.secureLookup) &&
+(te->vmid == vmid || tlbi_op.el2Enabled) &&
 te->checkELMatch(tlbi_op.targetEL, tlbi_op.inHost)) {

 te->valid = false;
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index be7a78b..bb5153d 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -47,6 +47,8 @@
 {
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
+el2Enabled = EL2Enabled(tc);
+
 getMMUPtr(tc)->flush(*this);

 // If CheckerCPU is connected, need to notify it of a flush
@@ -59,12 +61,14 @@
 void
 ITLBIALL::operator()(ThreadContext* tc)
 {
+el2Enabled = EL2Enabled(tc);
 getMMUPtr(tc)->iflush(*this);
 }

 void
 DTLBIALL::operator()(ThreadContext* tc)
 {
+el2Enabled = EL2Enabled(tc);
 getMMUPtr(tc)->dflush(*this);
 }

@@ -87,6 +91,8 @@
 {
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 inHost = (hcr.tge == 1 && hcr.e2h == 1);
+el2Enabled = EL2Enabled(tc);
+
 getMMUPtr(tc)->flush(*this);
 CheckerCPU *checker = tc->getCheckerCpuPtr();
 if (checker) {
@@ -97,12 +103,14 @@
 void
 ITLBIASID::operator()(ThreadContext* tc)
 {
+el2Enabled = EL2Enabled(tc);
 getMMUPtr(tc)->iflush(*this);
 }

 void
 DTLBIASID::operator()(ThreadContext* tc)
 {
+el2Enabled = EL2Enabled(tc);
 getMMUPtr(tc)->dflush(*this);
 }

diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 8b40587..888cd99 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -81,7 +81,7 @@
 {
   public:
 TLBIALL(ExceptionLevel _targetEL, bool _secure)
-  : TLBIOp(_targetEL, _secure), inHost(false)
+  : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false)
 {}

 void operator()(ThreadContext* tc) override;
@@ -93,6 +93,7 @@
 }

 bool inHost;
+bool el2Enabled;
 };

 /** Instruction TLB Invalidate All */
@@ -145,13 +146,15 @@
 {
   public:
 TLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
-  : TLBIOp(_targetEL, _secure), asid(_asid), inHost(false)
+  : TLBIOp(_targetEL, _secure), asid(_asid), inHost(false),
+el2Enabled(false)
 {}

 void operator()(ThreadContext* tc) override;

 uint16_t asid;
 bool inHost;
+bool el2Enabled;
 };

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix implementation of TLBI_VMALL instructions

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35243 )


Change subject: arch-arm: Fix implementation of TLBI_VMALL instructions
..

arch-arm: Fix implementation of TLBI_VMALL instructions

Same as 73dfc5f89b81e622a2330b1b52e055cafcc9178b: there's a difference
on how AArch64 and AArch32 treat stage2 invalidation.

Change-Id: I6fede4d9cb82e4bae9163326d38db9351d2a3880
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35243
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
5 files changed, 77 insertions(+), 8 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 1866319..217f432 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1755,17 +1755,15 @@
 return;
 }
   case MISCREG_TLBI_VMALLS12E1:
-// @todo: handle VMID and stage 2 to enable Virtualization
 {
 assert64();
 scr = readMiscReg(MISCREG_SCR);

-TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
 tlbiOp(tc);
 return;
 }
   case MISCREG_TLBI_VMALLE1:
-// @todo: handle VMID and stage 2 to enable Virtualization
 {
 assert64();
 scr = readMiscReg(MISCREG_SCR);
@@ -1773,22 +1771,20 @@
 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
 bool is_host = (hcr.tge && hcr.e2h);
 ExceptionLevel target_el = is_host ?  EL2 : EL1;
-TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
+TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns,  
false);

 tlbiOp(tc);
 return;
 }
   case MISCREG_TLBI_VMALLS12E1IS:
-// @todo: handle VMID and stage 2 to enable Virtualization
 {
 assert64();
 scr = readMiscReg(MISCREG_SCR);

-TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
+TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
 tlbiOp.broadcast(tc);
 return;
 }
   case MISCREG_TLBI_VMALLE1IS:
-// @todo: handle VMID and stage 2 to enable Virtualization
 {
 assert64();
 scr = readMiscReg(MISCREG_SCR);
@@ -1796,7 +1792,7 @@
 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
 bool is_host = (hcr.tge && hcr.e2h);
 ExceptionLevel target_el = is_host ?  EL2 : EL1;
-TLBIALL tlbiOp(target_el, haveSecurity && !scr.ns);
+TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns,  
false);

 tlbiOp.broadcast(tc);
 return;
 }
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 38aa38e..bad16d8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -330,6 +330,36 @@
 }

 void
+TLB::flush(const TLBIVMALL _op)
+{
+DPRINTF(TLB, "Flushing all TLB entries (%s lookup)\n",
+(tlbi_op.secureLookup ? "secure" : "non-secure"));
+int x = 0;
+TlbEntry *te;
+while (x < size) {
+te = [x];
+const bool el_match = te->checkELMatch(
+tlbi_op.targetEL, tlbi_op.inHost);
+if (te->valid && tlbi_op.secureLookup == !te->nstid &&
+(te->vmid == vmid || !tlbi_op.el2Enabled) && el_match) {
+
+DPRINTF(TLB, " -  %s\n", te->print());
+te->valid = false;
+stats.flushedEntries++;
+}
+++x;
+}
+
+stats.flushTlb++;
+
+// If there's a second stage TLB (and we're not it) then flush it as  
well

+// if we're currently in hyp mode
+if (!isStage2 && tlbi_op.stage2) {
+stage2Tlb->flush(tlbi_op.makeStage2());
+}
+}
+
+void
 TLB::flush(const TLBIALLN _op)
 {
 bool hyp = tlbi_op.targetEL == EL2;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index b05c9ba..c157a26 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -63,6 +63,7 @@

 class TLBIALL;
 class TLBIALLEL;
+class TLBIVMALL;
 class TLBIALLN;
 class TLBIMVA;
 class TLBIASID;
@@ -269,6 +270,11 @@
  */
 void flush(const TLBIALLEL _op);

+/** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS)
+ * instructions
+ */
+void flush(const TLBIVMALL _op);
+
 /** Remove all entries in the non secure world, depending on whether  
they

  *  were allocated in hyp mode or not
  */
diff --git

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: TlbEntry flush to be considered as functional lookup

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35244 )


Change subject: arch-arm: TlbEntry flush to be considered as functional  
lookup

..

arch-arm: TlbEntry flush to be considered as functional lookup

Otherwise we are unnecessarily shifting the TLB entry to the
MRU position before invalidating it

Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35244
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/tlb.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bad16d8..04b5cd4 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -446,7 +446,7 @@

 bool hyp = target_el == EL2;

-te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
+te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
 target_el, in_host);
 while (te != NULL) {
 if (secure_lookup == !te->nstid) {
@@ -454,7 +454,7 @@
 te->valid = false;
 stats.flushedEntries++;
 }
-te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
+te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
 target_el, in_host);
 }
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Gerrit-Change-Number: 35244
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual methods

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34984 )


Change subject: cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual  
methods

..

cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual methods

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I6c6cdeaa3ae1433624e4e5b30b031d49e822f0e0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34984
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Anthony Gutierrez 
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 0 insertions(+), 31 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 5e5d783..b7ea0b5 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -191,16 +191,6 @@
 int contextId() const override { return _contextId; }
 void setContextId(int id) override { _contextId = id; }

-BaseTLB *
-getITBPtr() override
-{
-return _itb;
-}
-BaseTLB *
-getDTBPtr() override
-{
-return _dtb;
-}
 BaseMMU *
 getMMUPtr() override
 {
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5213026..7eabe57 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -152,9 +152,6 @@
 // Primary thread being run.
 SimpleThread *thread;

-BaseTLB* getITBPtr() { return mmu->itb; }
-BaseTLB* getDTBPtr() { return mmu->dtb; }
-
 BaseMMU* getMMUPtr() { return mmu; }

 virtual Counter totalInsts() const override
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 5a68be4..b9442e8 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -127,10 +127,6 @@
 actualTC->setThreadId(id);
 }

-BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
-
-BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
-
 BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }

 CheckerCPU *
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index d4353d1..11de927 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -98,12 +98,6 @@
 /** Pointer to the thread state that this TC corrseponds to. */
 O3ThreadState *thread;

-/** Returns a pointer to the ITB. */
-BaseTLB *getITBPtr() override { return cpu->mmu->itb; }
-
-/** Returns a pointer to the DTB. */
-BaseTLB *getDTBPtr() override { return cpu->mmu->dtb; }
-
 /** Returns a pointer to the MMU. */
 BaseMMU *getMMUPtr() override { return cpu->mmu; }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e2f8070..b17f29a 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -206,10 +206,6 @@
 ContextID contextId() const override { return  
ThreadState::contextId(); }
 void setContextId(ContextID id) override {  
ThreadState::setContextId(id); }


-BaseTLB *getITBPtr() override { return mmu->itb; }
-
-BaseTLB *getDTBPtr() override { return mmu->dtb; }
-
 BaseMMU *getMMUPtr() override { return mmu; }

 CheckerCPU *getCheckerCpuPtr() override { return NULL; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9bd5cf5..c50eb26 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -130,10 +130,6 @@

 virtual void setContextId(ContextID id) = 0;

-virtual BaseTLB *getITBPtr() = 0;
-
-virtual BaseTLB *getDTBPtr() = 0;
-
 virtual BaseMMU *getMMUPtr() = 0;

 virtual CheckerCPU *getCheckerCpuPtr() = 0;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c6cdeaa3ae1433624e4e5b30b031d49e822f0e0
Gerrit-Change-Number: 34984
Gerrit-PatchSet: 17
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Matt Sinclair 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Do not require default options for caches

2020-11-03 Thread Davide Basilio Bartolini (Gerrit) via gem5-dev 
Davide Basilio Bartolini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36776 )


Change subject: configs: Do not require default options for caches
..

configs: Do not require default options for caches

This change is useful when using custom simulation scripts that do not
rely on configs/common/Options.py.
Without this change, the custom script always needed to provide some
value for cache sizes and HW prefetchers configuration; with this change
it is possible to provide no value and use what is defined in the core
configuration as default.

Change-Id: Id0e807c3fa224180d682f366c7307941bab8ce59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36776
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/CacheConfig.py
1 file changed, 27 insertions(+), 32 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 05c38e0..bd80c1a 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -48,6 +48,30 @@
 from common.Caches import *
 from common import ObjectList

+def _get_hwp(hwp_option):
+if hwp_option == None:
+return NULL
+
+hwpClass = ObjectList.hwp_list.get(hwp_option)
+return hwpClass()
+
+def _get_cache_opts(level, options):
+opts = {}
+
+size_attr = '{}_size'.format(level)
+if hasattr(options, size_attr):
+opts['size'] = getattr(options, size_attr)
+
+assoc_attr = '{}_assoc'.format(level)
+if hasattr(options, assoc_attr):
+opts['assoc'] = getattr(options, assoc_attr)
+
+prefetcher_attr = '{}_hwp_type'.format(level)
+if hasattr(options, prefetcher_attr):
+opts['prefetcher'] = _get_hwp(getattr(options, prefetcher_attr))
+
+return opts
+
 def config_cache(options, system):
 if options.external_memory_system and (options.caches or  
options.l2cache):
 print("External caches and internal caches are exclusive  
options.\n")

@@ -98,30 +122,19 @@
 # are not connected using addTwoLevelCacheHierarchy. Use the
 # same clock as the CPUs.
 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
-   size=options.l2_size,
-   assoc=options.l2_assoc)
+   **_get_cache_opts('l2', options))

 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
 system.l2.cpu_side = system.tol2bus.master
 system.l2.mem_side = system.membus.slave
-if options.l2_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l2_hwp_type)
-if system.l2.prefetcher != "Null":
-print("Warning: l2-hwp-type is set (", hwpClass, "), but",
-  "the current l2 has a default Hardware Prefetcher",
-  "of type", type(system.l2.prefetcher), ", using the",
-  "specified by the flag option.")
-system.l2.prefetcher = hwpClass()

 if options.memchecker:
 system.memchecker = MemChecker()

 for i in range(options.num_cpus):
 if options.caches:
-icache = icache_class(size=options.l1i_size,
-  assoc=options.l1i_assoc)
-dcache = dcache_class(size=options.l1d_size,
-  assoc=options.l1d_assoc)
+icache = icache_class(**_get_cache_opts('l1i', options))
+dcache = dcache_class(**_get_cache_opts('l1d', options))

 # If we have a walker cache specified, instantiate two
 # instances here
@@ -147,24 +160,6 @@
 # Let CPU connect to monitors
 dcache = dcache_mon

-if options.l1d_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l1d_hwp_type)
-if dcache.prefetcher != m5.params.NULL:
-print("Warning: l1d-hwp-type is set (", hwpClass, "),  
but",
-  "the current l1d has a default Hardware  
Prefetcher",
-  "of type", type(dcache.prefetcher), ", using  
the",

-  "specified by the flag option.")
-dcache.prefetcher = hwpClass()
-
-if options.l1i_hwp_type:
-hwpClass = ObjectList.hwp_list.get(options.l1i_hwp_type)
-if icache.prefetcher != m5.params.NULL:
-print("Warning: l1i-hwp-type is set (", hwpClass, "),  
but",
-  "the current l1i has a default Hardware  
Prefetcher",
-  "of type", type(icache.prefetcher), ", using  
the",

-