from:"Alec Roelke \(Gerrit\)"

[gem5-dev] Change in public/gem5[master]: riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4041 )


Change subject: riscv: Fix bugs with RISC-V decoder and detailed CPUs
..

riscv: Fix bugs with RISC-V decoder and detailed CPUs

This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen.  The rest of these
assertions will be changed in a later patch.

[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]

Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power 
Maintainer: Alec Roelke 
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/utility.hh
7 files changed, 90 insertions(+), 28 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index 36504f4..020c5e3 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -37,29 +37,45 @@
 namespace RiscvISA
 {

+static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1;
+static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4;
+
+void Decoder::reset()
+{
+aligned = true;
+mid = false;
+more = true;
+emi = NoopMachInst;
+instDone = false;
+}
+
 void
 Decoder::moreBytes(const PCState , Addr fetchPC, MachInst inst)
 {
-DPRINTF(Decode, "Getting bytes 0x%08x from address %#x\n",
-inst, pc.pc());
+DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
+fetchPC);

 bool aligned = pc.pc() % sizeof(MachInst) == 0;
-if (mid) {
-assert(!aligned);
-emi |= (inst & 0x) << 16;
+if (aligned) {
+emi = inst;
+if (compressed(emi))
+emi &= LowerBitMask;
+more = !compressed(emi);
 instDone = true;
 } else {
-MachInst instChunk = aligned ? inst & 0x :
-  (inst & 0x) >> 16;
-if (aligned) {
-emi = (inst & 0x3) < 0x3 ? instChunk : inst;
+if (mid) {
+assert((emi & UpperBitMask) == 0);
+emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
+mid = false;
+more = false;
 instDone = true;
 } else {
-emi = instChunk;
-instDone = (instChunk & 0x3) < 0x3;
+emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
+mid = !compressed(emi);
+more = true;
+instDone = compressed(emi);
 }
 }
-mid = !instDone;
 }

 StaticInstPtr
@@ -83,12 +99,10 @@
 return nullptr;
 instDone = false;

-if ((emi & 0x3) < 0x3) {
-nextPC.compressed(true);
-nextPC.npc(nextPC.pc() + sizeof(MachInst)/2);
+if (compressed(emi)) {
+nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2);
 } else {
-nextPC.compressed(false);
-nextPC.npc(nextPC.pc() + sizeof(MachInst));
+nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
 }

 return decode(emi, nextPC.instAddr());
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index ef644fa..c1d68bf 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -49,7 +49,9 @@
 {
   private:
 DecodeCache::InstMap instMap;
+bool aligned;
 bool mid;
+bool more;

   protected:
 //The extended machine instruction being generated
@@ -57,18 +59,18 @@
 bool instDone;

   public:
-Decoder(ISA* isa=nullptr)
-: mid(false), emi(NoopMachInst), instDone(false)
-{}
+Decoder(ISA* isa=nullptr) { reset(); }

 void process() {}
-void reset() { instDone = false; }
+void reset();
+
+inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; }

 //Use this to give data to the decoder. This should be used
 //when there is control flow.
 void moreBytes(const PCState , Addr fetchPC, MachInst inst);

-bool needMoreBytes() { return true; }
+bool needMoreBytes() { return more; }
 bool instReady() { return instDone; }
 void takeOverFrom(Decoder *old) {}

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 58baa4e..4e44d43 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -64,6 +64,13 @@
 }

 void
+IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr )
+{
+panic("Illegal instruction

[gem5-dev] Change in public/gem5[master]: riscv: Add unused attribute to some registers.hh constants

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4040 )


Change subject: riscv: Add unused attribute to some registers.hh constants
..

riscv: Add unused attribute to some registers.hh constants

Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.

Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Reviewed-on: https://gem5-review.googlesource.com/4040
Reviewed-by: Jason Lowe-Power 
Maintainer: Alec Roelke 
---
M src/arch/riscv/registers.hh
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e2b04ab..114d7e9 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,7 +93,7 @@
 const int ThreadPointerReg = 4;
 const int FramePointerReg = 8;
 const std::vector ReturnValueRegs = {10, 11};
-const int ReturnValueReg = ReturnValueRegs[0];
+const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0];
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

@@ -118,10 +118,10 @@
 "ft8", "ft9", "ft10", "ft11"
 };

-const int SyscallNumReg = ArgumentRegs[7];
+const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7];
 const std::vector SyscallArgumentRegs = {ArgumentRegs[0],  
ArgumentRegs[1],

 ArgumentRegs[2], ArgumentRegs[3]};
-const int SyscallPseudoReturnReg = ReturnValueRegs[0];
+const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0];

 enum MiscRegIndex {
 MISCREG_USTATUS = 0x000,

--
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To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Gerrit-Change-Number: 4040
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/4041 )


Change subject: riscv: Fix bugs with RISC-V decoder and detailed CPUs
..

riscv: Fix bugs with RISC-V decoder and detailed CPUs

This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen.  The rest of these
assertions will be changed in a later patch.

[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]

Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/utility.hh
7 files changed, 90 insertions(+), 28 deletions(-)


--
To view, visit https://gem5-review.googlesource.com/4041
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Gerrit-Change-Number: 4041
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-CC: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests: Upate RISC-V binaries and results

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/4042



Change subject: tests: Upate RISC-V binaries and results
..

tests: Upate RISC-V binaries and results

This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.

Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
---
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt
A tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini
A tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json
A tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr
A tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout
A tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/stats.txt
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt
M  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini
M  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json

M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout
M  
tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt

M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout
M tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.ini
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/config.json
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simerr
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/simout
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/minor-timing/stats.txt
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.ini
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/config.json
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simerr
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/simout
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/o3-timing/stats.txt
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.ini
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/config.json
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simerr
A tests/quick/se/02.insttest/ref/riscv/linux-rv64c/simple-atomic/simout
A

[gem5-dev] Change in public/gem5[master]: riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/4041



Change subject: riscv: Fix bugs with RISC-V decoder and detailed CPUs
..

riscv: Fix bugs with RISC-V decoder and detailed CPUs

This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen.  The rest of these
assertions will be changed in a later patch.

Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/utility.hh
7 files changed, 82 insertions(+), 28 deletions(-)



diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index 36504f4..5794f88 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -37,29 +37,46 @@
 namespace RiscvISA
 {

+static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1;
+static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4;
+
+void Decoder::reset()
+{
+//DPRINTF(Decode, "reset");
+aligned = true;
+mid = false;
+more = true;
+emi = NoopMachInst;
+instDone = false;
+}
+
 void
 Decoder::moreBytes(const PCState , Addr fetchPC, MachInst inst)
 {
-DPRINTF(Decode, "Getting bytes 0x%08x from address %#x\n",
-inst, pc.pc());
+DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
+fetchPC);

 bool aligned = pc.pc() % sizeof(MachInst) == 0;
-if (mid) {
-assert(!aligned);
-emi |= (inst & 0x) << 16;
+if (aligned) {
+emi = inst;
+if (compressed(emi))
+emi &= LowerBitMask;
+more = !compressed(emi);
 instDone = true;
 } else {
-MachInst instChunk = aligned ? inst & 0x :
-  (inst & 0x) >> 16;
-if (aligned) {
-emi = (inst & 0x3) < 0x3 ? instChunk : inst;
+if (mid) {
+assert((emi & UpperBitMask) == 0);
+emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
+mid = false;
+more = false;
 instDone = true;
 } else {
-emi = instChunk;
-instDone = (instChunk & 0x3) < 0x3;
+emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
+mid = !compressed(emi);
+more = true;
+instDone = compressed(emi);
 }
 }
-mid = !instDone;
 }

 StaticInstPtr
@@ -83,12 +100,10 @@
 return nullptr;
 instDone = false;

-if ((emi & 0x3) < 0x3) {
-nextPC.compressed(true);
-nextPC.npc(nextPC.pc() + sizeof(MachInst)/2);
+if (compressed(emi)) {
+nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2);
 } else {
-nextPC.compressed(false);
-nextPC.npc(nextPC.pc() + sizeof(MachInst));
+nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
 }

 return decode(emi, nextPC.instAddr());
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index ef644fa..c1d68bf 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -49,7 +49,9 @@
 {
   private:
 DecodeCache::InstMap instMap;
+bool aligned;
 bool mid;
+bool more;

   protected:
 //The extended machine instruction being generated
@@ -57,18 +59,18 @@
 bool instDone;

   public:
-Decoder(ISA* isa=nullptr)
-: mid(false), emi(NoopMachInst), instDone(false)
-{}
+Decoder(ISA* isa=nullptr) { reset(); }

 void process() {}
-void reset() { instDone = false; }
+void reset();
+
+inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; }

 //Use this to give data to the decoder. This should be used
 //when there is control flow.
 void moreBytes(const PCState , Addr fetchPC, MachInst inst);

-bool needMoreBytes() { return true; }
+bool needMoreBytes() { return more; }
 bool instReady() { return instDone; }
 void takeOverFrom(Decoder *old) {}

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 58baa4e..4e44d43 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -64,6 +64,13 @@
 }

 void
+IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr )
+{
+panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst,
+tc->pcState().pc(), reason.c_str());
+}
+
+void
 UnimplementedFault::invoke_se(ThreadContext *tc,
 const StaticInstPtr )
 {
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d0d7988..1e33b64 100644
--- a/src/arch/riscv/faults.hh
+++

[gem5-dev] Change in public/gem5[master]: riscv: Add unused attribute to some registers.hh constants

2017-07-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/4040



Change subject: riscv: Add unused attribute to some registers.hh constants
..

riscv: Add unused attribute to some registers.hh constants

Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.

Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
---
M src/arch/riscv/registers.hh
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e2b04ab..114d7e9 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -93,7 +93,7 @@
 const int ThreadPointerReg = 4;
 const int FramePointerReg = 8;
 const std::vector ReturnValueRegs = {10, 11};
-const int ReturnValueReg = ReturnValueRegs[0];
+const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0];
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

@@ -118,10 +118,10 @@
 "ft8", "ft9", "ft10", "ft11"
 };

-const int SyscallNumReg = ArgumentRegs[7];
+const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7];
 const std::vector SyscallArgumentRegs = {ArgumentRegs[0],  
ArgumentRegs[1],

 ArgumentRegs[2], ArgumentRegs[3]};
-const int SyscallPseudoReturnReg = ReturnValueRegs[0];
+const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0];

 enum MiscRegIndex {
 MISCREG_USTATUS = 0x000,

--
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To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Gerrit-Change-Number: 4040
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv, tests: Add insttests for RV64C

2017-07-10 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3862 )


Change subject: arch-riscv,tests: Add insttests for RV64C
..

arch-riscv,tests: Add insttests for RV64C

This patch adds instruction tests for the RV64C extension
implementation.  It also updates existing executables for the latest
riscv-tools now that they are compatible.

[Update for changes to parents.]

Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
Reviewed-on: https://gem5-review.googlesource.com/3862
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M tests/test-progs/insttest/src/riscv/Makefile
M tests/test-progs/insttest/src/riscv/insttest.h
A tests/test-progs/insttest/src/riscv/rv64c.cpp
A tests/test-progs/insttest/src/riscv/rv64c.h
4 files changed, 527 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/tests/test-progs/insttest/src/riscv/Makefile  
b/tests/test-progs/insttest/src/riscv/Makefile

index c493b40..921e372 100644
--- a/tests/test-progs/insttest/src/riscv/Makefile
+++ b/tests/test-progs/insttest/src/riscv/Makefile
@@ -27,9 +27,9 @@
 # Authors: Alec Roelke

 CXX=riscv64-unknown-linux-gnu-g++
-CFLAGS=--std=c++11 -O3 -static
+CFLAGS=-std=gnu++11 -O3 -static -march=rv64gc

-TARGETS=rv64i rv64m rv64a rv64f rv64d
+TARGETS=rv64i rv64m rv64a rv64f rv64d rv64c
 PREFIX=../../bin/riscv/linux
 BIN=insttest

@@ -44,6 +44,7 @@
 rv64a: rv64a.cpp
 rv64f: rv64f.cpp
 rv64d: rv64d.cpp
+rv64c: rv64c.cpp

 clean:
-rm $(PREFIX)-*/$(BIN)
diff --git a/tests/test-progs/insttest/src/riscv/insttest.h  
b/tests/test-progs/insttest/src/riscv/insttest.h

index 59b6986..be1b86e 100644
--- a/tests/test-progs/insttest/src/riscv/insttest.h
+++ b/tests/test-progs/insttest/src/riscv/insttest.h
@@ -72,7 +72,6 @@
 } else {
 cout << "\033[1;31mFAIL\033[0m (expected " << expected << ";  
found " <<

 result << ")" << endl;
-exit(1);
 }
 }

diff --git a/tests/test-progs/insttest/src/riscv/rv64c.cpp  
b/tests/test-progs/insttest/src/riscv/rv64c.cpp

new file mode 100644
index 000..869784d
--- /dev/null
+++ b/tests/test-progs/insttest/src/riscv/rv64c.cpp
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#include 
+
+#include "insttest.h"
+#include "rv64c.h"
+#include "rv64d.h"
+
+int main()
+{
+using namespace insttest;
+using namespace std;
+
+// C.LWSP
+expect(true, []{
+uint64_t lw = 0, lwsp = -1;
+int64_t i = 16;
+asm volatile("lw %0,%2(sp);"
+ "c.lwsp %1,%2(sp);"
+ : "=r" (lw), "=r" (lwsp)
+ : "i" (i));
+return lw == lwsp;
+}, "c.lwsp");
+
+// C.LDSP
+expect(true, []{
+uint64_t ld = 0, ldsp = -1;
+int64_t i = 8;
+asm volatile("ld %0,%2(sp);"
+ "c.ldsp %1,%2(sp);"
+ : "=r" (ld), "=r" (ldsp)
+ : "i" (i));
+return ld == ldsp;
+}, "c.ldsp");
+
+// C.FLDSP
+expect(true, []{
+double fld = 0.0, fldsp = -1.0;
+int64_t i = 32;
+asm volatile("fld %0,%2(sp);"
+ "c.fldsp %1,%2(sp);"
+ : "=f" (fld), "=f" (fldsp)
+

[gem5-dev] Change in public/gem5[master]: arch-riscv: Add support for compressed extension RV64C

2017-07-10 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#3). (  
https://gem5-review.googlesource.com/3860 )


Change subject: arch-riscv: Add support for compressed extension RV64C
..

arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
A src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/types.hh
10 files changed, 1,908 insertions(+), 1,404 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Gerrit-Change-Number: 3860
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv, tests: Add insttests for RV64C

2017-07-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3862 )


Change subject: arch-riscv,tests: Add insttests for RV64C
..

arch-riscv,tests: Add insttests for RV64C

This patch adds instruction tests for the RV64C extension
implementation.  It also updates existing executables for the latest
riscv-tools now that they are compatible.

[Update for changes to parents.]

Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
---
M tests/test-progs/insttest/src/riscv/Makefile
M tests/test-progs/insttest/src/riscv/insttest.h
A tests/test-progs/insttest/src/riscv/rv64c.cpp
A tests/test-progs/insttest/src/riscv/rv64c.h
4 files changed, 527 insertions(+), 3 deletions(-)


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
Gerrit-Change-Number: 3862
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Add support for compressed extension RV64C

2017-07-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3860 )


Change subject: arch-riscv: Add support for compressed extension RV64C
..

arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
---
M src/arch/riscv/decoder.cc
M src/arch/riscv/decoder.hh
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
A src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/isa/operands.isa
M src/arch/riscv/types.hh
10 files changed, 1,908 insertions(+), 1,404 deletions(-)


--
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Gerrit-Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Gerrit-Change-Number: 3860
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Restructure ISA description

2017-07-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#4). (  
https://gem5-review.googlesource.com/3800 )


Change subject: arch-riscv: Restructure ISA description
..

arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/base.isa
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
A src/arch/riscv/isa/formats/standard.isa
D src/arch/riscv/isa/formats/type.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/registers.hh
M src/arch/riscv/utility.hh
15 files changed, 738 insertions(+), 684 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
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Gerrit-Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Gerrit-Change-Number: 3800
Gerrit-PatchSet: 4
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-CC: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Restructure ISA description

2017-07-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#3). (  
https://gem5-review.googlesource.com/3800 )


Change subject: arch-riscv: Restructure ISA description
..

arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/base.isa
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
A src/arch/riscv/isa/formats/standard.isa
D src/arch/riscv/isa/formats/type.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/registers.hh
14 files changed, 723 insertions(+), 681 deletions(-)


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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Gerrit-Change-Number: 3800
Gerrit-PatchSet: 3
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Gerrit-Reviewer: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: arch-riscv, tests: Add insttests for RV64C

2017-06-23 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/3862



Change subject: arch-riscv,tests: Add insttests for RV64C
..

arch-riscv,tests: Add insttests for RV64C

This patch adds instruction tests for the RV64C extension
implementation.  It also updates existing executables for the latest
riscv-tools now that they are compatible.

Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
---
A tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
A tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest
A tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
A tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
A tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest
A tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
M tests/test-progs/insttest/src/riscv/Makefile
M tests/test-progs/insttest/src/riscv/insttest.h
A tests/test-progs/insttest/src/riscv/rv64c.cpp
A tests/test-progs/insttest/src/riscv/rv64c.h
10 files changed, 528 insertions(+), 4 deletions(-)



diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest

new file mode 100755
index 000..73dc9d0
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest

new file mode 100755
index 000..d655ceb
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest

new file mode 100755
index 000..724eeac
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest

new file mode 100755
index 000..6bd4b37
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest

new file mode 100755
index 000..a6e5d02
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest  
b/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest

new file mode 100755
index 000..dce8766
--- /dev/null
+++ b/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
Binary files differ
diff --git a/tests/test-progs/insttest/src/riscv/Makefile  
b/tests/test-progs/insttest/src/riscv/Makefile

index c493b40..f98fcd0 100644
--- a/tests/test-progs/insttest/src/riscv/Makefile
+++ b/tests/test-progs/insttest/src/riscv/Makefile
@@ -26,10 +26,10 @@
 #
 # Authors: Alec Roelke

-CXX=riscv64-unknown-linux-gnu-g++
-CFLAGS=--std=c++11 -O3 -static
+CXX=$(HOME)/.temp/riscv/bin/riscv64-unknown-linux-gnu-g++
+CFLAGS=-std=gnu++11 -O3 -static -march=rv64gc

-TARGETS=rv64i rv64m rv64a rv64f rv64d
+TARGETS=rv64i rv64m rv64a rv64f rv64d rv64c
 PREFIX=../../bin/riscv/linux
 BIN=insttest

@@ -44,6 +44,7 @@
 rv64a: rv64a.cpp
 rv64f: rv64f.cpp
 rv64d: rv64d.cpp
+rv64c: rv64c.cpp

 clean:
-rm $(PREFIX)-*/$(BIN)
diff --git a/tests/test-progs/insttest/src/riscv/insttest.h  
b/tests/test-progs/insttest/src/riscv/insttest.h

index 59b6986..be1b86e 100644
--- a/tests/test-progs/insttest/src/riscv/insttest.h
+++ b/tests/test-progs/insttest/src/riscv/insttest.h
@@ -72,7 +72,6 @@
 } else {
 cout << "\033[1;31mFAIL\033[0m (expected " << expected << ";  
found " <<

 result << ")" << endl;
-exit(1);
 }
 }

diff --git a/tests/test-progs/insttest/src/riscv/rv64c.cpp  
b/tests/test-progs/insttest/src/riscv/rv64c.cpp

new file mode 100644
index 000..869784d
--- /dev/null
+++ b/tests/test-progs/insttest/src/riscv/rv64c.cpp
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND

[gem5-dev] Change in public/gem5[master]: arch-riscv: Restructure ISA description

2017-06-16 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/3800 )


Change subject: arch-riscv: Restructure ISA description
..

arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/base.isa
M src/arch/riscv/isa/bitfields.isa
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/mem.isa
A src/arch/riscv/isa/formats/standard.isa
D src/arch/riscv/isa/formats/type.isa
M src/arch/riscv/isa/includes.isa
M src/arch/riscv/registers.hh
14 files changed, 723 insertions(+), 681 deletions(-)


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[gem5-dev] Change in public/gem5[master]: tests: Update RISC-V hello test and stats

2017-06-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3560 )


Change subject: tests: Update RISC-V hello test and stats
..

tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt
M tests/test-progs/hello/bin/riscv/linux/hello
26 files changed, 3,281 insertions(+), 3,134 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




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Gerrit-MessageType: merged
Gerrit-Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Gerrit-Change-Number: 3560
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: tests: Update RISC-V hello test and stats

2017-05-31 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/3560



Change subject: tests: Update RISC-V hello test and stats
..

tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
---
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout
M tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt
M tests/test-progs/hello/bin/riscv/linux/hello
26 files changed, 3,281 insertions(+), 3,134 deletions(-)




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[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix bad stack initialization

2017-05-23 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/3401 )


Change subject: arch-riscv: Fix bad stack initialization
..

arch-riscv: Fix bad stack initialization

This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.

Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Reviewed-on: https://gem5-review.googlesource.com/3401
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Brandon Potter 
Maintainer: Alec Roelke 
---
M src/arch/riscv/process.cc
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Brandon Potter: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 13038c1..eeea5ee 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -88,6 +88,7 @@

 // Determine stack size and populate auxv
 Addr stack_top = memState->getStackMin();
+stack_top -= elfObject->programHeaderSize();
 for (const string& arg: argv)
 stack_top -= arg.size() + 1;
 for (const string& env: envp)
@@ -113,6 +114,16 @@
 allocateMem(roundDown(stack_top, pageSize),
 roundUp(memState->getStackSize(), pageSize));

+// Copy program headers to stack
+memState->setStackMin(memState->getStackMin() -
+elfObject->programHeaderSize());
+uint8_t* phdr = new uint8_t[elfObject->programHeaderSize()];
+initVirtMem.readBlob(elfObject->programHeaderTable(), phdr,
+elfObject->programHeaderSize());
+initVirtMem.writeBlob(memState->getStackMin(), phdr,
+elfObject->programHeaderSize());
+delete phdr;
+
 // Copy argv to stack
 vector argPointers;
 for (const string& arg: argv) {

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Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Gerrit-Change-Number: 3401
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Fix bad stack initialization

2017-05-16 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/3401



Change subject: arch-riscv: Fix bad stack initialization
..

arch-riscv: Fix bad stack initialization

This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.

Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
---
M src/arch/riscv/process.cc
1 file changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 13038c1..eeea5ee 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -88,6 +88,7 @@

 // Determine stack size and populate auxv
 Addr stack_top = memState->getStackMin();
+stack_top -= elfObject->programHeaderSize();
 for (const string& arg: argv)
 stack_top -= arg.size() + 1;
 for (const string& env: envp)
@@ -113,6 +114,16 @@
 allocateMem(roundDown(stack_top, pageSize),
 roundUp(memState->getStackSize(), pageSize));

+// Copy program headers to stack
+memState->setStackMin(memState->getStackMin() -
+elfObject->programHeaderSize());
+uint8_t* phdr = new uint8_t[elfObject->programHeaderSize()];
+initVirtMem.readBlob(elfObject->programHeaderTable(), phdr,
+elfObject->programHeaderSize());
+initVirtMem.writeBlob(memState->getStackMin(), phdr,
+elfObject->programHeaderSize());
+delete phdr;
+
 // Copy argv to stack
 vector argPointers;
 for (const string& arg: argv) {

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[gem5-dev] Change in public/gem5[master]: cpu: fix problem with forwarding and locked load

2017-04-18 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#3). (  
https://gem5-review.googlesource.com/2400 )


Change subject: cpu: fix problem with forwarding and locked load
..

cpu: fix problem with forwarding and locked load

If a (regular) store is followed closely enough by a locked load that
overlaps, the LSQ will forward the store's data to the locked load and
never tell the cache about the locked load.  As a result, the cache will
not lock the address and all future store-conditional requests on that
address will fail.  This patch fixes that by preventing forwarding if
the memory request is a locked load and adding another case to the LSQ
forwarding logic that delays the locked load request if a store in the
LSQ contains all or part of the data that is requested.

[Merge second and last if blocks because their bodies are the same.]

Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 14 insertions(+), 6 deletions(-)


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Gerrit-Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
Gerrit-Change-Number: 2400
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Emilio Castillo 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: riscv: Fix crashes with large or frequent mmaps

2017-04-11 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2680 )


Change subject: riscv: Fix crashes with large or frequent mmaps
..

riscv: Fix crashes with large or frequent mmaps

This patch fixes a bug where increasing the mmap region too much causes
it to run into already-allocated memory, which causes gem5 to fail an
assertion.  Previously, the stack was incorrectly set up such that the
end of the mmap region and the top of the stack were the same address
and both would grow downward.  With this patch, the top of the stack has
been separated from the end of mmap and moved up, and the mmap region
now grows upward instead of downward.

[Rebase to master branch and remove dependencies.]

Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
Reviewed-on: https://gem5-review.googlesource.com/2680
Maintainer: Alec Roelke 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
2 files changed, 6 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index b962372..13038c1 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -60,13 +60,12 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-const Addr mem_base = 0x8000;
-const Addr stack_base = mem_base;
+const Addr stack_base = 0x7FFFL;
 const Addr max_stack_size = PageBytes * 64;
 const Addr next_thread_stack_base = stack_base - max_stack_size;
 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
 PageBytes);
-const Addr mmap_end = mem_base;
+const Addr mmap_end = 0x4000L;
 memState = make_shared(brk_point, stack_base, max_stack_size,
 next_thread_stack_base, mmap_end);
 }
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 8275a11..f732a44 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2017 The University of Virginia
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  *
  * Authors: Gabe Black
  *  Ali Saidi
+ *  Alec Roelke
  */

 #ifndef __RISCV_PROCESS_HH__
@@ -57,6 +59,8 @@
 using Process::getSyscallArg;
 void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+
+virtual bool mmapGrowsDown() const override { return false; }
 };

 /* No architectural page table defined for this ISA */

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Gerrit-Change-Number: 2680
Gerrit-PatchSet: 3
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Gerrit-Reviewer: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: riscv: Fix crashes with large or frequent mmaps

2017-04-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/2680 )


Change subject: riscv: Fix crashes with large or frequent mmaps
..

riscv: Fix crashes with large or frequent mmaps

This patch fixes a bug where increasing the mmap region too much causes
it to run into already-allocated memory, which causes gem5 to fail an
assertion.  Previously, the stack was incorrectly set up such that the
end of the mmap region and the top of the stack were the same address
and both would grow downward.  With this patch, the top of the stack has
been separated from the end of mmap and moved up, and the mmap region
now grows upward instead of downward.

[Rebase to master branch and remove dependencies.]

Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
2 files changed, 6 insertions(+), 3 deletions(-)


--
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Gerrit-PatchSet: 2
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[gem5-dev] Change in public/gem5[master]: riscv: fix Linux problems with LR and SC ops

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2340 )


Change subject: riscv: fix Linux problems with LR and SC ops
..

riscv: fix Linux problems with LR and SC ops

Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain.  This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.

Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/SConscript
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/mem.isa
A src/arch/riscv/locked_mem.cc
M src/arch/riscv/locked_mem.hh
M tests/test-progs/insttest/src/riscv/rv64a.cpp
7 files changed, 325 insertions(+), 100 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index dcb670a..5aaac6b 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -50,6 +50,7 @@
 Source('faults.cc')
 Source('isa.cc')
 Source('interrupts.cc')
+Source('locked_mem.cc')
 Source('process.cc')
 Source('pagetable.cc')
 Source('remote_gdb.cc')
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index eac0652..2b23c1f 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -170,12 +170,12 @@
 0x2: decode AMOFUNCT {
 0x2: LoadReserved::lr_w({{
 Rd_sd = Mem_sw;
-}}, mem_flags=LLSC, aq=AQ, rl=RL);
+}}, mem_flags=LLSC);
 0x3: StoreCond::sc_w({{
 Mem_uw = Rs2_uw;
 }}, {{
 Rd = result;
-}}, inst_flags=IsStoreConditional, mem_flags=LLSC, aq=AQ,  
rl=RL);

+}}, inst_flags=IsStoreConditional, mem_flags=LLSC);
 format AtomicMemOp {
 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{
 Mem_sw = Rs2_sw + Rt_sd;
@@ -218,12 +218,12 @@
 0x3: decode AMOFUNCT {
 0x2: LoadReserved::lr_d({{
 Rd_sd = Mem_sd;
-}}, mem_flags=LLSC, aq=AQ, rl=RL);
+}}, mem_flags=LLSC);
 0x3: StoreCond::sc_d({{
 Mem = Rs2;
 }}, {{
 Rd = result;
-}}, mem_flags=LLSC, inst_flags=IsStoreConditional, aq=AQ,  
rl=RL);

+}}, mem_flags=LLSC, inst_flags=IsStoreConditional);
 format AtomicMemOp {
 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
 Mem_sd = Rs2_sd + Rt_sd;
diff --git a/src/arch/riscv/isa/formats/amo.isa  
b/src/arch/riscv/isa/formats/amo.isa

index b837cc9..d60c4e0 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -34,6 +34,33 @@
 // Atomic memory operation instructions
 //
 output header {{
+class LoadReserved : public RiscvStaticInst
+{
+  protected:
+Request::Flags memAccessFlags;
+
+LoadReserved(const char *mnem, ExtMachInst _machInst,
+OpClass __opClass)
+: RiscvStaticInst(mnem, _machInst, __opClass)
+{}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class StoreCond : public RiscvStaticInst
+{
+  protected:
+Request::Flags memAccessFlags;
+
+StoreCond(const char* mnem, ExtMachInst _machInst, OpClass  
__opClass)

+: RiscvStaticInst(mnem, _machInst, __opClass)
+{}
+
+std::string
+generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class AtomicMemOp : public RiscvMacroInst
 {
 protected:
@@ -65,11 +92,29 @@
 }};

 output decoder {{
+std::string LoadReserved::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", ("
+<< regName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
+std::string StoreCond::generateDisassembly(Addr pc,
+const SymbolTable *symtab) const
+{
+std::stringstream ss;
+ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", "
+<< regName(_srcRegIdx[1]) << ", ("
+<< regName(_srcRegIdx[0]) << ')';
+return ss.str();
+}
+
 std::string AtomicMemOp::generateDisassembly(Addr pc,
 const SymbolTable *symtab) const
 {
 std::stringstream ss;
-ss << csprintf("0x%08x", machInst) << ' ';
 ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", "

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2305 )


Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
Reviewed-on: https://gem5-review.googlesource.com/2305
Maintainer: Alec Roelke 
Reviewed-by: Brandon Potter 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 115 insertions(+), 140 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Brandon Potter: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index f50fb31..b962372 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,23 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-Addr stack_base = 0x7FFF;
-
-Addr max_stack_size = 8 * 1024 * 1024;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-Addr next_thread_stack_base = stack_base - max_stack_size;
-
-// Set up break point (Top of Heap)
-Addr brk_point = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-Addr mmap_end = brk_point + 0x4000L;
-
+const Addr mem_base = 0x8000;
+const Addr stack_base = mem_base;
+const Addr max_stack_size = PageBytes * 64;
+const Addr next_thread_stack_base = stack_base - max_stack_size;
+const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
+const Addr mmap_end = mem_base;
 memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,145 +83,122 @@
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->setStackMin(memState->getStackBase());

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate

[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2304 )


Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
Reviewed-on: https://gem5-review.googlesource.com/2304
Maintainer: Alec Roelke 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 370 insertions(+), 150 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+

[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2345 )


Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Reviewed-on: https://gem5-review.googlesource.com/2345
Maintainer: Alec Roelke 
Reviewed-by: Brandon Potter 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/tlb.cc
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..c47260e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,17 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+// In the O3 CPU model, sometimes a memory access will be speculatively
+// executed along a branch that will end up not being taken where the
+// address is invalid.  In that case, return a fault rather than trying
+// to translate it (which will cause a panic).  Since RISC-V allows
+// unaligned memory accesses, this should only happen if the request's
+// length is long enough to wrap around from the end of the memory to  
the

+// start.
+assert(req->getSize() > 0);
+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
To view, visit https://gem5-review.googlesource.com/2345
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 7
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: riscv: enable unaligned memory accesses

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2341 )


Change subject: riscv: enable unaligned memory accesses
..

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Reviewed-on: https://gem5-review.googlesource.com/2341
Maintainer: Alec Roelke 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/riscv/isa_traits.hh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c87..327d644 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@

 const ExtMachInst NoopMachInst = 0x0013;

-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory  
accesses)

+const bool HasUnalignedMemAcc = true;

 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Gerrit-Change-Number: 2341
Gerrit-PatchSet: 7
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: riscv: Fix crashes with large or frequent mmaps

2017-04-05 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2680



Change subject: riscv: Fix crashes with large or frequent mmaps
..

riscv: Fix crashes with large or frequent mmaps

This patch fixes a bug where increasing the mmap region too much causes
it to run into already-allocated memory, which causes gem5 to fail an
assertion.  Previously, the stack was incorrectly set up such that the
end of the mmap region and the top of the stack were the same address
and both would grow downward.  With this patch, the top of the stack has
been separated from the end of mmap and moved up, and the mmap region
now grows upward instead of downward.

Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
2 files changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index b962372..13038c1 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -60,13 +60,12 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-const Addr mem_base = 0x8000;
-const Addr stack_base = mem_base;
+const Addr stack_base = 0x7FFFL;
 const Addr max_stack_size = PageBytes * 64;
 const Addr next_thread_stack_base = stack_base - max_stack_size;
 const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
 PageBytes);
-const Addr mmap_end = mem_base;
+const Addr mmap_end = 0x4000L;
 memState = make_shared(brk_point, stack_base, max_stack_size,
 next_thread_stack_base, mmap_end);
 }
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 8275a11..f732a44 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2017 The University of Virginia
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  *
  * Authors: Gabe Black
  *  Ali Saidi
+ *  Alec Roelke
  */

 #ifndef __RISCV_PROCESS_HH__
@@ -57,6 +59,8 @@
 using Process::getSyscallArg;
 void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
 void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+
+virtual bool mmapGrowsDown() const override { return false; }
 };

 /* No architectural page table defined for this ISA */

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520
Gerrit-Change-Number: 2680
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-03-21 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#7). (  
https://gem5-review.googlesource.com/2304 )


Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 370 insertions(+), 150 deletions(-)




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+{MISCREG_MVENDORID, "mvendorid"},
+{MISCREG_MARCHID, "marchid"},
+{MISCREG_MIMPID, "mimpid"},
+{MISCREG_MHARTID, "mhartid"},
+{MISCREG_MSTATUS, "mstatus"},
+{MISCREG_MISA, "misa"},
+{MISCREG_MEDELEG,

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-21 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#9). (  
https://gem5-review.googlesource.com/2305 )


Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 115 insertions(+), 140 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index f50fb31..b962372 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,23 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-Addr stack_base = 0x7FFF;
-
-Addr max_stack_size = 8 * 1024 * 1024;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-Addr next_thread_stack_base = stack_base - max_stack_size;
-
-// Set up break point (Top of Heap)
-Addr brk_point = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-Addr mmap_end = brk_point + 0x4000L;
-
+const Addr mem_base = 0x8000;
+const Addr stack_base = mem_base;
+const Addr max_stack_size = PageBytes * 64;
+const Addr next_thread_stack_base = stack_base - max_stack_size;
+const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
+const Addr mmap_end = mem_base;
 memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,145 +83,122 @@
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->setStackMin(memState->getStackBase());

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stack_top = memState->getStackMin();
+for (const string& arg: argv)
+stack_top -= arg.size() + 1;
+for (const string& env: envp)
+stack_top -= env.size() + 1;
+stack_top &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
+

[gem5-dev] Change in public/gem5[master]: riscv: enable unaligned memory accesses

2017-03-21 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#6). (  
https://gem5-review.googlesource.com/2341 )


Change subject: riscv: enable unaligned memory accesses
..

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
---
M src/arch/riscv/isa_traits.hh
1 file changed, 2 insertions(+), 2 deletions(-)




diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c87..327d644 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@

 const ExtMachInst NoopMachInst = 0x0013;

-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory  
accesses)

+const bool HasUnalignedMemAcc = true;

 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;

--
To view, visit https://gem5-review.googlesource.com/2341
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Gerrit-Change-Number: 2341
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-21 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#6). (  
https://gem5-review.googlesource.com/2345 )


Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 11 insertions(+), 0 deletions(-)




diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..c47260e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,17 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+// In the O3 CPU model, sometimes a memory access will be speculatively
+// executed along a branch that will end up not being taken where the
+// address is invalid.  In that case, return a fault rather than trying
+// to translate it (which will cause a panic).  Since RISC-V allows
+// unaligned memory accesses, this should only happen if the request's
+// length is long enough to wrap around from the end of the memory to  
the

+// start.
+assert(req->getSize() > 0);
+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
To view, visit https://gem5-review.googlesource.com/2345
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-20 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#8). (  
https://gem5-review.googlesource.com/2305 )


Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 115 insertions(+), 140 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index f50fb31..b962372 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,23 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-Addr stack_base = 0x7FFF;
-
-Addr max_stack_size = 8 * 1024 * 1024;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-Addr next_thread_stack_base = stack_base - max_stack_size;
-
-// Set up break point (Top of Heap)
-Addr brk_point = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-Addr mmap_end = brk_point + 0x4000L;
-
+const Addr mem_base = 0x8000;
+const Addr stack_base = mem_base;
+const Addr max_stack_size = PageBytes * 64;
+const Addr next_thread_stack_base = stack_base - max_stack_size;
+const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
+const Addr mmap_end = mem_base;
 memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,145 +83,122 @@
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->setStackMin(memState->getStackBase());

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stack_top = memState->getStackMin();
+for (const string& arg: argv)
+stack_top -= arg.size() + 1;
+for (const string& env: envp)
+stack_top -= env.size() + 1;
+stack_top &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
+

[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-03-20 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#6). (  
https://gem5-review.googlesource.com/2304 )


Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 370 insertions(+), 150 deletions(-)




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+{MISCREG_MVENDORID, "mvendorid"},
+{MISCREG_MARCHID, "marchid"},
+{MISCREG_MIMPID, "mimpid"},
+{MISCREG_MHARTID, "mhartid"},
+{MISCREG_MSTATUS, "mstatus"},
+{MISCREG_MISA, "misa"},
+{MISCREG_MEDELEG,

[gem5-dev] Change in public/gem5[master]: riscv: enable unaligned memory accesses

2017-03-20 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#5). (  
https://gem5-review.googlesource.com/2341 )


Change subject: riscv: enable unaligned memory accesses
..

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
---
M src/arch/riscv/isa_traits.hh
1 file changed, 2 insertions(+), 2 deletions(-)




diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c87..327d644 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@

 const ExtMachInst NoopMachInst = 0x0013;

-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory  
accesses)

+const bool HasUnalignedMemAcc = true;

 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;

--
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Gerrit-Branch: master
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Gerrit-Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Gerrit-Change-Number: 2341
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[gem5-dev] Change in public/gem5[master]: cpu: fix problem with forwarding and locked load

2017-03-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/2400 )


Change subject: cpu: fix problem with forwarding and locked load
..

cpu: fix problem with forwarding and locked load

If a (regular) store is followed closely enough by a locked load that
overlaps, the LSQ will forward the store's data to the locked load and
never tell the cache about the locked load.  As a result, the cache will
not lock the address and all future store-conditional requests on that
address will fail.  This patch fixes that by preventing forwarding if
the memory request is a locked load and adding another case to the LSQ
forwarding logic that delays the locked load request if a store in the
LSQ contains all or part of the data that is requested.

Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 47 insertions(+), 5 deletions(-)




diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 10d4966..bd2f4ff 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -671,8 +671,10 @@
 (req->getVaddr() + req->getSize()) >
 storeQueue[store_idx].inst->effAddr;

-// If the store's data has all of the data needed, we can forward.
-if ((store_has_lower_limit && store_has_upper_limit)) {
+// If the store's data has all of the data needed and the load  
isn't

+// LLSC, we can forward.
+if ((store_has_lower_limit && store_has_upper_limit &&
+!req->isLLSC())) {
 // Get shift amount for offset into the store's data.
 int shift_amt = req->getVaddr() -  
storeQueue[store_idx].inst->effAddr;


@@ -707,11 +709,12 @@

 ++lsqForwLoads;
 return NoFault;
-} else if ((store_has_lower_limit && lower_load_has_store_part) ||
+} else if (((store_has_lower_limit && lower_load_has_store_part) ||
(store_has_upper_limit && upper_load_has_store_part) ||
-   (lower_load_has_store_part &&  
upper_load_has_store_part)) {
+   (lower_load_has_store_part &&  
upper_load_has_store_part)) &&

+   !req->isLLSC()) {
 // This is the partial store-load forwarding case where a store
-// has only part of the load's data.
+// has only part of the load's data and the load isn't LLSC

 // If it's already been written back, then don't worry about
 // stalling on it.
@@ -753,6 +756,45 @@
 }

 return NoFault;
+} else if (req->isLLSC() &&
+((store_has_lower_limit || upper_load_has_store_part) &&
+ (store_has_upper_limit || lower_load_has_store_part))) {
+// This is the case where the load is LLSC and the store has  
all

+// or part of the load's data
+
+// Must stall load and force it to retry, so long as it's the
+// oldest load that needs to do so.
+if (!stalled ||
+(stalled &&
+ load_inst->seqNum <
+ loadQueue[stallingLoadIdx]->seqNum)) {
+stalled = true;
+stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
+stallingLoadIdx = load_idx;
+}
+
+// Tell IQ/mem dep unit that this instruction will need to be
+// rescheduled eventually
+iewStage->rescheduleMemInst(load_inst);
+load_inst->clearIssued();
+++lsqRescheduledLoads;
+
+// Do not generate a writeback event as this instruction is not
+// complete.
+DPRINTF(LSQUnit, "Locked load to incomplete store. "
+"Store idx %i to load addr %#x\n",
+store_idx, req->getVaddr());
+
+// Must delete request now that it wasn't handed off to
+// memory.  This is quite ugly.  @todo: Figure out the
+// proper place to really handle request deletes.
+delete req;
+if (TheISA::HasUnalignedMemAcc && sreqLow) {
+delete sreqLow;
+delete sreqHigh;
+}
+
+return NoFault;
 }
 }


--
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Gerrit-Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#5). (  
https://gem5-review.googlesource.com/2345 )


Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 11 insertions(+), 0 deletions(-)




diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..c47260e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,17 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+// In the O3 CPU model, sometimes a memory access will be speculatively
+// executed along a branch that will end up not being taken where the
+// address is invalid.  In that case, return a fault rather than trying
+// to translate it (which will cause a panic).  Since RISC-V allows
+// unaligned memory accesses, this should only happen if the request's
+// length is long enough to wrap around from the end of the memory to  
the

+// start.
+assert(req->getSize() > 0);
+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
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Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 5
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#4). (  
https://gem5-review.googlesource.com/2345 )


Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)




diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..379bf5f 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,9 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
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Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
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[gem5-dev] Change in public/gem5[master]: cpu: fix problem with forwarding and locked load

2017-03-14 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2400



Change subject: cpu: fix problem with forwarding and locked load
..

cpu: fix problem with forwarding and locked load

If a (regular) store is followed closely enough by a locked load that
overlaps, the LSQ will forward the store's data to the locked load and
never tell the cache about the locked load.  As a result, the cache will
not lock the address and all future store-conditional requests on that
address will fail.  This patch fixes that by preventing forwarding if
the memory request is a locked load and adding another case to the LSQ
forwarding logic that delays the locked load request if a store in the
LSQ contains all or part of the data that is requested.

Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 46 insertions(+), 4 deletions(-)



diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 10d4966..1850e2a 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -671,8 +671,10 @@
 (req->getVaddr() + req->getSize()) >
 storeQueue[store_idx].inst->effAddr;

-// If the store's data has all of the data needed, we can forward.
-if ((store_has_lower_limit && store_has_upper_limit)) {
+// If the store's data has all of the data needed and the load  
isn't

+// LLSC, we can forward.
+if ((store_has_lower_limit && store_has_upper_limit &&
+!req->isLLSC())) {
 // Get shift amount for offset into the store's data.
 int shift_amt = req->getVaddr() -  
storeQueue[store_idx].inst->effAddr;


@@ -709,9 +711,10 @@
 return NoFault;
 } else if ((store_has_lower_limit && lower_load_has_store_part) ||
(store_has_upper_limit && upper_load_has_store_part) ||
-   (lower_load_has_store_part &&  
upper_load_has_store_part)) {
+   (lower_load_has_store_part &&  
upper_load_has_store_part) ||

+   !req->isLLSC()) {
 // This is the partial store-load forwarding case where a store
-// has only part of the load's data.
+// has only part of the load's data and the load isn't LLSC

 // If it's already been written back, then don't worry about
 // stalling on it.
@@ -753,6 +756,45 @@
 }

 return NoFault;
+} else if (req->isLLSC() &&
+((store_has_lower_limit || upper_load_has_store_part) &&
+ (store_has_upper_limit || lower_load_has_store_part))) {
+// This is the case where the load is LLSC and the store has  
all

+// or part of the load's data
+
+// Must stall load and force it to retry, so long as it's the
+// oldest load that needs to do so.
+if (!stalled ||
+(stalled &&
+ load_inst->seqNum <
+ loadQueue[stallingLoadIdx]->seqNum)) {
+stalled = true;
+stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
+stallingLoadIdx = load_idx;
+}
+
+// Tell IQ/mem dep unit that this instruction will need to be
+// rescheduled eventually
+iewStage->rescheduleMemInst(load_inst);
+load_inst->clearIssued();
+++lsqRescheduledLoads;
+
+// Do not generate a writeback event as this instruction is not
+// complete.
+DPRINTF(LSQUnit, "Locked load to incomplete store. "
+"Store idx %i to load addr %#x\n",
+store_idx, req->getVaddr());
+
+// Must delete request now that it wasn't handed off to
+// memory.  This is quite ugly.  @todo: Figure out the
+// proper place to really handle request deletes.
+delete req;
+if (TheISA::HasUnalignedMemAcc && sreqLow) {
+delete sreqLow;
+delete sreqHigh;
+}
+
+return NoFault;
 }
 }


--
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-13 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2345

to look at the new patch set (#3).

Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 11 insertions(+), 0 deletions(-)




diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..c8c458f 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,17 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+// In the O3 CPU model, sometimes a memory access will be speculatively
+// executed along a branch that will end up not being taken where the
+// address is invalid.  In that case, return a fault rather than trying
+// to translate it (which will cause a panic).  Since RISC-V allows
+// unaligned memory accesses, this should only happen if the request's
+// length is long enough to wrap around from the end of the memory to  
the

+// beginning.
+assert(req->getSize() > 0);
+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-13 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2345

to look at the new patch set (#2).

Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

[Update creation of page table fault to use make_shared.]

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)




diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..379bf5f 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,9 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return make_shared(req->getVaddr());
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
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Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: riscv: don't quit insttest after failing a test

2017-03-13 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2346



Change subject: riscv: don't quit insttest after failing a test
..

riscv: don't quit insttest after failing a test

Change-Id: I8768ee367c29568d350146255ca7d589e479c271
---
M tests/test-progs/insttest/src/riscv/insttest.h
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/tests/test-progs/insttest/src/riscv/insttest.h  
b/tests/test-progs/insttest/src/riscv/insttest.h

index 59b6986..be1b86e 100644
--- a/tests/test-progs/insttest/src/riscv/insttest.h
+++ b/tests/test-progs/insttest/src/riscv/insttest.h
@@ -72,7 +72,6 @@
 } else {
 cout << "\033[1;31mFAIL\033[0m (expected " << expected << ";  
found " <<

 result << ")" << endl;
-exit(1);
 }
 }


--
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[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

2017-03-13 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2345



Change subject: riscv: fix error on memory op address overflow
..

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0x), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..52d7740 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,9 @@
 if (FullSystem)
 panic("translateData not implemented in RISC-V.\n");

+if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+return Fault(new GenericPageTableFault(req->getVaddr()));
+
 Process * p = tc->getProcessPtr();

 Fault fault = p->pTable->translate(req);

--
To view, visit https://gem5-review.googlesource.com/2345
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
___
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[gem5-dev] Change in public/gem5[master]: riscv: enable unaligned memory accesses

2017-03-10 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2341



Change subject: riscv: enable unaligned memory accesses
..

riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
---
M src/arch/riscv/isa_traits.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c87..327d644 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@

 const ExtMachInst NoopMachInst = 0x0013;

-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory  
accesses)

+const bool HasUnalignedMemAcc = true;

 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;

--
To view, visit https://gem5-review.googlesource.com/2341
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Gerrit-Change-Number: 2341
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
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[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-10 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2305

to look at the new patch set (#5).

Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 115 insertions(+), 140 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index f50fb31..b962372 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,23 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-Addr stack_base = 0x7FFF;
-
-Addr max_stack_size = 8 * 1024 * 1024;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-Addr next_thread_stack_base = stack_base - max_stack_size;
-
-// Set up break point (Top of Heap)
-Addr brk_point = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-Addr mmap_end = brk_point + 0x4000L;
-
+const Addr mem_base = 0x8000;
+const Addr stack_base = mem_base;
+const Addr max_stack_size = PageBytes * 64;
+const Addr next_thread_stack_base = stack_base - max_stack_size;
+const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
+const Addr mmap_end = mem_base;
 memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,145 +83,122 @@
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->setStackMin(memState->getStackBase());

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stack_top = memState->getStackMin();
+for (const string& arg: argv)
+stack_top -= arg.size() + 1;
+for (const string& env: envp)
+stack_top -= env.size() + 1;
+stack_top &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-10 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2305

to look at the new patch set (#4).

Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 115 insertions(+), 140 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index f50fb31..b962372 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,23 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-Addr stack_base = 0x7FFF;
-
-Addr max_stack_size = 8 * 1024 * 1024;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-Addr next_thread_stack_base = stack_base - max_stack_size;
-
-// Set up break point (Top of Heap)
-Addr brk_point = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-Addr mmap_end = brk_point + 0x4000L;
-
+const Addr mem_base = 0x8000;
+const Addr stack_base = mem_base;
+const Addr max_stack_size = PageBytes * 64;
+const Addr next_thread_stack_base = stack_base - max_stack_size;
+const Addr brk_point = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
+const Addr mmap_end = mem_base;
 memState = make_shared(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
+next_thread_stack_base, mmap_end);
 }

 void
@@ -85,145 +83,122 @@
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->setStackMin(memState->getStackBase());

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stack_top = memState->getStackMin();
+for (const string& arg: argv)
+stack_top -= arg.size() + 1;
+for (const string& env: envp)
+stack_top -= env.size() + 1;
+stack_top &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+auxv.push_back({M5_AT_ENTRY, objFile->entryPoint()});
+auxv.push_back({M5_AT_PHNUM,

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-09 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2305

to look at the new patch set (#3).

Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M tests/test-progs/insttest/src/riscv/Makefile
2 files changed, 114 insertions(+), 130 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 8b168cb..edafd1d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,18 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-memState->stackBase = (Addr)0x7FFF;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-memState->nextThreadStackBase = memState->stackBase - (8 * 1024 *  
1024);

-
-// Set up break point (Top of Heap)
-memState->brkPoint = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-memState->mmapEnd = memState->brkPoint + 0x4000L;
+// The process for initializing memory and the stack was based on the  
code

+// for RISC-V's proxy kernel, which can be found at:
+// https://github.com/riscv/riscv-pk
+const Addr memBase = 0x8000;
+memState->stackBase = memBase;
+memState->nextThreadStackBase = memState->stackBase + PageBytes * 64;
+memState->mmapEnd = memBase;
+memState->brkPoint = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
 }

 void
@@ -79,141 +82,122 @@
 template void
 RiscvProcess::argsInit(int pageSize)
 {
+const auto pushOntoStack =
+[this](Addr& sp, const uint8_t* data, const size_t size) {
+initVirtMem.writeBlob(sp, data, size);
+sp += size;
+};
+
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->stackMin = memState->stackBase;

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stackTop = memState->stackMin;
+for (const string& arg: argv)
+stackTop -= arg.size() + 1;
+for (const string& env: envp)
+stackTop -= env.size() + 1;
+stackTop &= -sizeof(Addr);
+
+vector auxv;
+if

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-09 Thread Alec Roelke (Gerrit)


Hello Jason Lowe-Power, Brandon Potter,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/2305

to look at the new patch set (#2).

Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M tests/test-progs/insttest/src/riscv/Makefile
3 files changed, 117 insertions(+), 130 deletions(-)




diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 8b168cb..edafd1d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,18 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-memState->stackBase = (Addr)0x7FFF;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-memState->nextThreadStackBase = memState->stackBase - (8 * 1024 *  
1024);

-
-// Set up break point (Top of Heap)
-memState->brkPoint = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-memState->mmapEnd = memState->brkPoint + 0x4000L;
+// The process for initializing memory and the stack was based on the  
code

+// for RISC-V's proxy kernel, which can be found at:
+// https://github.com/riscv/riscv-pk
+const Addr memBase = 0x8000;
+memState->stackBase = memBase;
+memState->nextThreadStackBase = memState->stackBase + PageBytes * 64;
+memState->mmapEnd = memBase;
+memState->brkPoint = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
 }

 void
@@ -79,141 +82,122 @@
 template void
 RiscvProcess::argsInit(int pageSize)
 {
+const auto pushOntoStack =
+[this](Addr& sp, const uint8_t* data, const size_t size) {
+initVirtMem.writeBlob(sp, data, size);
+sp += size;
+};
+
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->stackMin = memState->stackBase;

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stackTop = memState->stackMin;
+for (const string& arg: argv)
+stackTop -= arg.size() + 1;
+for (const string& env: envp)
+stackTop -= env.size() + 1;
+stackTop &= -sizeof(Addr);
+
+

[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-03-09 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/2304 )


Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 370 insertions(+), 150 deletions(-)




diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+{MISCREG_MVENDORID, "mvendorid"},
+{MISCREG_MARCHID, "marchid"},
+{MISCREG_MIMPID, "mimpid"},
+{MISCREG_MHARTID, "mhartid"},
+{MISCREG_MSTATUS, "mstatus"},
+{MISCREG_MISA, "misa"},
+{MISCREG_MEDELEG,

[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-03-07 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2304



Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. At the
moment, all you can do is connect a remote GDB and pause and continue
execution; viewing debugging information and controlling execution do
not work properly.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 370 insertions(+), 150 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+{MISCREG_MVENDORID, "mvendorid"},
+{MISCREG_MARCHID, "marchid"},
+{MISCREG_MIMPID, "mimpid"},
+{MISCREG_MHARTID, "mhartid"},
+{MISCREG_MSTATUS, "mstatus"},
+{MISCREG_MISA, "misa"},
+{MISCREG_MEDELEG, "medeleg"},
+{MISCREG_MIDELEG,

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-07 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2305



Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M tests/test-progs/insttest/src/riscv/Makefile
3 files changed, 121 insertions(+), 130 deletions(-)



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 8b168cb..5349b00 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,18 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-memState->stackBase = (Addr)0x7FFF;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-memState->nextThreadStackBase = memState->stackBase - (8 * 1024 *  
1024);

-
-// Set up break point (Top of Heap)
-memState->brkPoint = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-memState->mmapEnd = memState->brkPoint + 0x4000L;
+// The process for initializing memory and the stack was based on the  
code

+// for RISC-V's proxy kernel, which can be found at:
+// https://github.com/riscv/riscv-pk
+const Addr memBase = 0x8000;
+memState->stackBase = memBase;
+memState->nextThreadStackBase = memState->stackBase + PageBytes * 64;
+memState->mmapEnd = memBase;
+memState->brkPoint = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
 }

 void
@@ -76,144 +79,126 @@
 argsInit(PageBytes);
 }

+void
+RiscvProcess::pushOntoStack(Addr& sp, const uint8_t* data, size_t size)  
const

+{
+initVirtMem.writeBlob(sp, data, size);
+sp += size;
+}
+
 template void
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->stackMin = memState->stackBase;

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stackTop = memState->stackMin;
+for (const string& arg: argv)
+stackTop -= arg.size() + 1;
+for (const string& env: envp)
+stackTop -= env.size() + 1;
+stackTop &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+

[gem5-dev] Change in public/gem5[master]: riscv: fix compatibility with Linux toolchain

2017-03-07 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2303



Change subject: riscv: fix compatibility with Linux toolchain
..

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode.  This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it.  Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

Change-Id: I444b4ce8493fdae57b69696c3d14d914996c09f7
---
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M tests/test-progs/insttest/src/riscv/Makefile
3 files changed, 121 insertions(+), 130 deletions(-)



diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 8b168cb..5349b00 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -33,6 +33,11 @@
  */
 #include "arch/riscv/process.hh"

+#include 
+#include 
+#include 
+#include 
+#include 
 #include 

 #include "arch/riscv/isa_traits.hh"
@@ -40,8 +45,9 @@
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
+#include "debug/Stack.hh"
 #include "mem/page_table.hh"
+#include "params/Process.hh"
 #include "sim/aux_vector.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
@@ -54,18 +60,15 @@
 RiscvProcess::RiscvProcess(ProcessParams * params,
 ObjectFile *objFile) : Process(params, objFile)
 {
-// Set up stack. On RISC-V, stack starts at the top of kuseg
-// user address space. RISC-V stack grows down from here
-memState->stackBase = (Addr)0x7FFF;
-
-// Set pointer for next thread stack.  Reserve 8M for main stack.
-memState->nextThreadStackBase = memState->stackBase - (8 * 1024 *  
1024);

-
-// Set up break point (Top of Heap)
-memState->brkPoint = objFile->bssBase() + objFile->bssSize();
-
-// Set up region for mmaps.  Start it 1GB above the top of the heap.
-memState->mmapEnd = memState->brkPoint + 0x4000L;
+// The process for initializing memory and the stack was based on the  
code

+// for RISC-V's proxy kernel, which can be found at:
+// https://github.com/riscv/riscv-pk
+const Addr memBase = 0x8000;
+memState->stackBase = memBase;
+memState->nextThreadStackBase = memState->stackBase + PageBytes * 64;
+memState->mmapEnd = memBase;
+memState->brkPoint = roundUp(objFile->bssBase() + objFile->bssSize(),
+PageBytes);
 }

 void
@@ -76,144 +79,126 @@
 argsInit(PageBytes);
 }

+void
+RiscvProcess::pushOntoStack(Addr& sp, const uint8_t* data, size_t size)  
const

+{
+initVirtMem.writeBlob(sp, data, size);
+sp += size;
+}
+
 template void
 RiscvProcess::argsInit(int pageSize)
 {
 updateBias();
-
-// load object file into target memory
 objFile->loadSections(initVirtMem);
+ElfObject* elfObject = dynamic_cast(objFile);
+memState->stackMin = memState->stackBase;

-typedef AuxVector auxv_t;
-vector auxv;
-ElfObject * elfObject = dynamic_cast(objFile);
-if (elfObject) {
-// Set the system page size
-auxv.push_back(auxv_t(M5_AT_PAGESZ, RiscvISA::PageBytes));
-// Set the frequency at which time() increments
-auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
-// For statically linked executables, this is the virtual
-// address of the program header tables if they appear in the
-// executable image.
-auxv.push_back(auxv_t(M5_AT_PHDR,  
elfObject->programHeaderTable()));

-DPRINTF(Loader, "auxv at PHDR %08p\n",
-elfObject->programHeaderTable());
-// This is the size of a program header entry from the elf file.
-auxv.push_back(auxv_t(M5_AT_PHENT,  
elfObject->programHeaderSize()));
-// This is the number of program headers from the original elf  
file.
-auxv.push_back(auxv_t(M5_AT_PHNUM,  
elfObject->programHeaderCount()));

-auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
-//The entry point to the program
-auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
-//Different user and group IDs
-auxv.push_back(auxv_t(M5_AT_UID, uid()));
-auxv.push_back(auxv_t(M5_AT_EUID, euid()));
-auxv.push_back(auxv_t(M5_AT_GID, gid()));
-auxv.push_back(auxv_t(M5_AT_EGID, egid()));
+// Determine stack size and populate auxv
+Addr stackTop = memState->stackMin;
+for (const string& arg: argv)
+stackTop -= arg.size() + 1;
+for (const string& env: envp)
+stackTop -= env.size() + 1;
+stackTop &= -sizeof(Addr);
+
+vector auxv;
+if (elfObject != nullptr) {
+

[gem5-dev] Change in public/gem5[master]: riscv: add remote gdb support

2017-03-06 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2300



Change subject: riscv: add remote gdb support
..

riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. At the
moment, all you can do is connect a remote GDB and pause and continue
execution; viewing debugging information and controlling execution do
not work properly.

Change-Id: I3fd48d4263bc0d9a290fc0f6f0939c7286ab93e5
---
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
2 files changed, 182 insertions(+), 43 deletions(-)



diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 64735d0..548b53c 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -1,8 +1,20 @@
 /*
+ * Copyright 2015 LabWare
+ * Copyright 2014 Google, Inc.
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2017 The University of Virginia
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * Copyright (c) 2015 Sven Karlsson
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,43 +41,152 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Nathan Binkert
- *  Stephen Hines
- *  Timothy M. Jones
- *  Sven Karlsson
+ *  William Wang
+ *  Deyuan Guo
+ *  Boris Shingarov
+ *  Alec Roelke
  */

- #include "base/remote_gdb.hh"
- #include "arch/riscv/remote_gdb.hh"
- #include "sim/system.hh"
+/*
+ * Copyright (c) 1990, 1993 The Regents of the University of California
+ * All rights reserved
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ *  This product includes software developed by the University of
+ *  California, Lawrence Berkeley Laboratories.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *must display the following acknowledgement:
+ *  This product includes software developed by the University of
+ *  California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *may be used to endorse or promote products derived from this software
+ *without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR  
PURPOSE

+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR  
CONSEQUENTIAL

+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,  
STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY  
WAY

+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *  @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
+ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the

[gem5-dev] Change in public/gem5[master]: riscv: add debugging via remote gdb

2017-03-06 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2301



Change subject: riscv: add debugging via remote gdb
..

riscv: add debugging via remote gdb

Change-Id: Ia4162a62ccb6d5a3989b9ca069e18af722488c76
---
M src/arch/riscv/remote_gdb.cc
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 548b53c..96a6a9f 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -142,6 +142,7 @@
 #include "arch/riscv/registers.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
+#include "mem/page_table.hh"
 #include "sim/full_system.hh"

 using namespace std;

--
To view, visit https://gem5-review.googlesource.com/2301
To unsubscribe, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia4162a62ccb6d5a3989b9ca069e18af722488c76
Gerrit-Change-Number: 2301
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
___
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[gem5-dev] Change in public/gem5[master]: riscv: Add support for remote debugging via gdb

2017-03-06 Thread Alec Roelke (Gerrit)

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2302



Change subject: riscv: Add support for remote debugging via gdb
..

riscv: Add support for remote debugging via gdb

This patch adds support for remote debugging via GDB to RISC-V.  GDB is
included along with the rest of the RISC-V GCC toolchain found at
http://github.com/ucb-bar/riscv-tools.  Currently only the Newlib
toolchain (riscv64-unknown-elf-*) is supported.

Change-Id: I16b9951bcd90ffdcdd3f237803ae76b1f9cd63bc
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
5 files changed, 195 insertions(+), 115 deletions(-)



diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5..d99954b 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@

 #include 
 #include 
+#include 

 #include "arch/riscv/registers.hh"
 #include "base/bitfield.hh"
@@ -44,79 +45,114 @@
 namespace RiscvISA
 {

-std::map ISA::miscRegNames = {
-{MISCREG_FFLAGS, "fflags"},
-{MISCREG_FRM, "frm"},
-{MISCREG_FCSR, "fcsr"},
-{MISCREG_CYCLE, "cycle"},
-{MISCREG_TIME, "time"},
-{MISCREG_INSTRET, "instret"},
-{MISCREG_CYCLEH, "cycleh"},
-{MISCREG_TIMEH, "timeh"},
-{MISCREG_INSTRETH, "instreth"},
-
-{MISCREG_SSTATUS, "sstatus"},
-{MISCREG_STVEC, "stvec"},
-{MISCREG_SIE, "sie"},
-{MISCREG_STIMECMP, "stimecmp"},
-{MISCREG_STIME, "stime"},
-{MISCREG_STIMEH, "stimeh"},
-{MISCREG_SSCRATCH, "sscratch"},
-{MISCREG_SEPC, "sepc"},
-{MISCREG_SCAUSE, "scause"},
-{MISCREG_SBADADDR, "sbadaddr"},
-{MISCREG_SIP, "sip"},
-{MISCREG_SPTBR, "sptbr"},
-{MISCREG_SASID, "sasid"},
-{MISCREG_CYCLEW, "cyclew"},
-{MISCREG_TIMEW, "timew"},
-{MISCREG_INSTRETW, "instretw"},
-{MISCREG_CYCLEHW, "cyclehw"},
-{MISCREG_TIMEHW, "timehw"},
-{MISCREG_INSTRETHW, "instrethw"},
-
-{MISCREG_HSTATUS, "hstatus"},
-{MISCREG_HTVEC, "htvec"},
-{MISCREG_HTDELEG, "htdeleg"},
-{MISCREG_HTIMECMP, "htimecmp"},
-{MISCREG_HTIME, "htime"},
-{MISCREG_HTIMEH, "htimeh"},
-{MISCREG_HSCRATCH, "hscratch"},
-{MISCREG_HEPC, "hepc"},
-{MISCREG_HCAUSE, "hcause"},
-{MISCREG_HBADADDR, "hbadaddr"},
-{MISCREG_STIMEW, "stimew"},
-{MISCREG_STIMEHW, "stimehw"},
-
-{MISCREG_MCPUID, "mcpuid"},
-{MISCREG_MIMPID, "mimpid"},
-{MISCREG_MHARTID, "mhartid"},
-{MISCREG_MSTATUS, "mstatus"},
-{MISCREG_MTVEC, "mtvec"},
-{MISCREG_MTDELEG, "mtdeleg"},
-{MISCREG_MIE, "mie"},
-{MISCREG_MTIMECMP, "mtimecmp"},
-{MISCREG_MTIME, "mtime"},
-{MISCREG_MTIMEH, "mtimeh"},
-{MISCREG_MSCRATCH, "mscratch"},
-{MISCREG_MEPC, "mepc"},
-{MISCREG_MCAUSE, "mcause"},
-{MISCREG_MBADADDR, "mbadaddr"},
-{MISCREG_MIP, "mip"},
-{MISCREG_MBASE, "mbase"},
-{MISCREG_MBOUND, "mbound"},
-{MISCREG_MIBASE, "mibase"},
-{MISCREG_MIBOUND, "mibound"},
-{MISCREG_MDBASE, "mdbase"},
-{MISCREG_MDBOUND, "mdbound"},
-{MISCREG_HTIMEW, "htimew"},
-{MISCREG_HTIMEHW, "htimehw"},
-{MISCREG_MTOHOST, "mtohost"},
-{MISCREG_MFROMHOST, "mfromhost"}
-};
-
 ISA::ISA(Params *p) : SimObject(p)
 {
+miscRegNames = {
+{MISCREG_USTATUS, "ustatus"},
+{MISCREG_UIE, "uie"},
+{MISCREG_UTVEC, "utvec"},
+{MISCREG_USCRATCH, "uscratch"},
+{MISCREG_UEPC, "uepc"},
+{MISCREG_UCAUSE, "ucause"},
+{MISCREG_UBADADDR, "ubadaddr"},
+{MISCREG_UIP, "uip"},
+{MISCREG_FFLAGS, "fflags"},
+{MISCREG_FRM, "frm"},
+{MISCREG_FCSR, "fcsr"},
+{MISCREG_CYCLE, "cycle"},
+{MISCREG_TIME, "time"},
+{MISCREG_INSTRET, "instret"},
+{MISCREG_CYCLEH, "cycleh"},
+{MISCREG_TIMEH, "timeh"},
+{MISCREG_INSTRETH, "instreth"},
+
+{MISCREG_SSTATUS, "sstatus"},
+{MISCREG_SEDELEG, "sedeleg"},
+{MISCREG_SIDELEG, "sideleg"},
+{MISCREG_SIE, "sie"},
+{MISCREG_STVEC, "stvec"},
+{MISCREG_SSCRATCH, "sscratch"},
+{MISCREG_SEPC, "sepc"},
+{MISCREG_SCAUSE, "scause"},
+{MISCREG_SBADADDR, "sbadaddr"},
+{MISCREG_SIP, "sip"},
+{MISCREG_SPTBR, "sptbr"},
+
+{MISCREG_HSTATUS, "hstatus"},
+{MISCREG_HEDELEG, "hedeleg"},
+{MISCREG_HIDELEG, "hideleg"},
+{MISCREG_HIE, "hie"},
+{MISCREG_HTVEC, "htvec"},
+{MISCREG_HSCRATCH, "hscratch"},
+{MISCREG_HEPC, "hepc"},
+{MISCREG_HCAUSE, "hcause"},
+{MISCREG_HBADADDR, "hbadaddr"},
+{MISCREG_HIP, "hip"},
+
+{MISCREG_MVENDORID, "mvendorid"},
+{MISCREG_MARCHID, "marchid"},
+{MISCREG_MIMPID, "mimpid"},
+{MISCREG_MHARTID, "mhartid"},
+{MISCREG_MSTATUS, "mstatus"},
+{MISCREG_MISA, "misa"},
+

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