[gem5-dev] Change in gem5/gem5[develop]: python: Add simulator instantiation checks

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53923 )



Change subject: python: Add simulator instantiation checks
..

python: Add simulator instantiation checks

Check that m5.instantiate() has been called before m5.simulate() and
that m5.instantiate() is only called once.

Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/simulate.py
1 file changed, 27 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index b5b8c78..0e222cf 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -62,11 +62,19 @@

 _drain_manager = _m5.drain.DrainManager.instance()

-# The final hook to generate .ini files.  Called from the user script
-# once the config is built.
+_instantiated = False # Has m5.instantiate() been called?
+
+# The final call to instantiate the SimObject graph and initialize the
+# system.
 def instantiate(ckpt_dir=None):
+global _instantiated
 from m5 import options

+if _instantiated:
+fatal("m5.instantiate() called twice.")
+
+_instantiated = True
+
 root = objects.Root.getInstance()

 if not root:
@@ -148,6 +156,10 @@
 need_startup = True
 def simulate(*args, **kwargs):
 global need_startup
+global _instantiated
+
+if not _instantiated:
+fatal("m5.instantiate() must be called before m5.simulate().")

 if need_startup:
 root = objects.Root.getInstance()

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Gerrit-Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Gerrit-Change-Number: 53923
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary Python 2.x workaround

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50407 )


Change subject: python: Remove unnecessary Python 2.x workaround
..

python: Remove unnecessary Python 2.x workaround

We needed to explicitly cast the return value from getCode() to int to
avoid a Python 2.x issue where sys.exit() got confused by an
unexpected long argument. This isn't an issue in Python 3 since long
has been removed as a separate type.

Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50407
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/pybind11/event.cc
1 file changed, 0 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index 794b6e3..aefe50a 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -134,18 +134,7 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
 .def("getCause", ::getCause)
-#if PY_MAJOR_VERSION >= 3
 .def("getCode", ::getCode)
-#else
-// Workaround for an issue where PyBind11 converts the exit
-// code to a long. This is normally fine, but sys.exit treats
-// any non-int type as an error and exits with status 1 if it
-// is passed a long.
-.def("getCode", [](GlobalSimLoopExitEvent *e) {
-return py::reinterpret_steal(
-PyInt_FromLong(e->getCode()));
-})
-#endif
 ;

 // Event base class. These should never be returned directly to

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Gerrit-Change-Number: 50407
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Reinitialize threads on drainResume

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50409 )



Change subject: cpu-kvm: Reinitialize threads on drainResume
..

cpu-kvm: Reinitialize threads on drainResume

Event queue service threads may have been re-created while the
simulator was drained. We therefore need to initialize the new thread
by setting correct signal masks and re-attaching performance counters.

Change-Id: Ic0dab80543928327021cade037770c917e73a47f
Signed-off-by: Andreas Sandberg 
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
2 files changed, 21 insertions(+), 8 deletions(-)



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index c7c72a8..ea43595 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2012, 2015, 2017, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -154,9 +154,9 @@
 inform("KVM: Coalesced not supported by host OS\n");
 }

-Event *startupEvent(
-new EventFunctionWrapper([this]{ startupThread(); }, name(),  
true));

-schedule(startupEvent, curTick());
+schedule(new EventFunctionWrapper([this]{
+restartEqThread();
+}, name(), true), curTick());
 }

 BaseKvmCPU::Status
@@ -228,7 +228,7 @@
 }

 void
-BaseKvmCPU::startupThread()
+BaseKvmCPU::restartEqThread()
 {
 // Do thread-specific initialization. We need to setup signal
 // delivery for counters and timers from within the thread that
@@ -381,6 +381,13 @@
 {
 assert(!tickEvent.scheduled());

+/* The simulator may have terminated the threads servicing event
+ * queues. In that case, we need to re-initialize the new
+ * threads. */
+schedule(new EventFunctionWrapper([this]{
+restartEqThread();
+}, name(), true), curTick());
+
 // We might have been switched out. In that case, we don't need to
 // do anything.
 if (switchedOut())
@@ -1275,6 +1282,11 @@
 .samplePeriod(42);
 }

+// We might be re-attaching counters due threads being
+// re-initialised after fork.
+if (hwCycles.attached())
+hwCycles.detach();
+
 hwCycles.attach(cfgCycles,
 0); // TID (0 => currentThread)

diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index e5b047e..4f40064 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -682,11 +682,12 @@
  * example, when setting up timers, we need to know the TID of the
  * thread executing in KVM in order to deliver the timer signal to
  * that thread. This method is called as the first event in this
- * SimObject's event queue.
+ * SimObject's event queue and after drainResume to handle changes
+ * to event queue service threads.
  *
  * @see startup
  */
-void startupThread();
+void restartEqThread();

 /** Try to drain the CPU if a drain is pending */
 bool tryDrain();

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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary Python 2.x workaround

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50407 )



Change subject: python: Remove unnecessary Python 2.x workaround
..

python: Remove unnecessary Python 2.x workaround

We needed to explicitly cast the return value from getCode() to int to
avoid a Python 2.x issue where sys.exit() got confused by an
unexpected long argument. This isn't an issue in Python 3 since long
has been removed as a separate type.

Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/event.cc
1 file changed, 0 insertions(+), 11 deletions(-)



diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index 794b6e3..aefe50a 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -134,18 +134,7 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
 .def("getCause", ::getCause)
-#if PY_MAJOR_VERSION >= 3
 .def("getCode", ::getCode)
-#else
-// Workaround for an issue where PyBind11 converts the exit
-// code to a long. This is normally fine, but sys.exit treats
-// any non-int type as an error and exits with status 1 if it
-// is passed a long.
-.def("getCode", [](GlobalSimLoopExitEvent *e) {
-return py::reinterpret_steal(
-PyInt_FromLong(e->getCode()));
-})
-#endif
 ;

 // Event base class. These should never be returned directly to

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Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix fork for multithreaded simulations

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50408 )



Change subject: sim: Fix fork for multithreaded simulations
..

sim: Fix fork for multithreaded simulations

It is currently not possible to call m5.fork when the simulator is
running in with multiple parallel event queues. The POSIX standard
have very weak guarantees when forking a process with multiple
threads. In order to use fork correctly, we need to ensure that all
helper threads servicing event queues have terminated before the fork
system call is invoked.

There are two ways this could be implemented: 1) Always terminate
helper threads when taking a global simulator exit event, or 2)
terminate helper threads just before fork is called from Python.

This change implements the second strategy since the KVM-based CPUs
currently assume that TIDs don't change unless there is a fork event.

Change-Id: I22feaecd49f7f81689b43185d63a8f14428bed63
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/simulate.py
M src/python/pybind11/event.cc
M src/sim/simulate.cc
M src/sim/simulate.hh
4 files changed, 90 insertions(+), 14 deletions(-)



diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 66e6a08..b5b8c78 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012,2019 ARM Limited
+# Copyright (c) 2012, 2019, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -348,6 +348,9 @@

 drain()

+# Terminate helper threads that service parallel event queues.
+_m5.event.terminateEventQueueThreads()
+
 try:
 pid = os.fork()
 except OSError as e:
diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index aefe50a..7a02221 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -107,6 +107,7 @@

 m.def("simulate", ,
   py::arg("ticks") = MaxTick);
+m.def("terminateEventQueueThreads", );
 m.def("exitSimLoop", );
 m.def("getEventQueue", []() { return curEventQueue(); },
   py::return_value_policy::reference);
diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc
index 4a00869..a87bd04 100644
--- a/src/sim/simulate.cc
+++ b/src/sim/simulate.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * Copyright (c) 2013 Mark D. Hill and David A. Wood
@@ -30,6 +42,7 @@

 #include "sim/simulate.hh"

+#include 
 #include 
 #include 

@@ -46,11 +59,15 @@
 {

 //! Mutex for handling async events.
-std::mutex asyncEventMutex;
+static std::mutex asyncEventMutex;

 //! Global barrier for synchronizing threads entering/exiting the
 //! simulation loop.
-Barrier *threadBarrier;
+static Barrier *threadBarrier;
+
+static std::atomic terminateEqThreads = false;
+
+static std::vector eventThreads;

 //! forward declaration
 Event *doSimLoop(EventQueue *);
@@ -66,9 +83,12 @@
 static void
 thread_loop(EventQueue *queue)
 {
-while (true) {
-threadBarrier->wait();
+/* Wait for all initialisation to complete */
+threadBarrier->wait();
+
+while (!terminateEqThreads) {
 doSimLoop(queue);
+threadBarrier->wait();
 }
 }

@@ -86,18 +106,14 @@
 // create a thread for each of event queues referenced by the
 // instantiated sim objects.
 static bool threads_initialized = false;
-static std::vector threads;
+
+/* terminateEqThreads is initialised to false and should only be
+ * set to true temporarily in terminateEventQueueThreads. */
+assert(!terminateEqThreads);

 if (!threads_initialized) {
 threadBarrier = new Barrier(numMainEventQueues);

-// the main thread (the one we're currently running on)
-// handles queue 0, so we only need to allocate new threads
-// for queues 1..N-1.  We'll call these the "subordinate" threads.
-for (uint32

[gem5-dev] Change in gem5/gem5[stable]: python: Fix incorrect prefixes is m5.utils.convert

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/42783 )



Change subject: python: Fix incorrect prefixes is m5.utils.convert
..

python: Fix incorrect prefixes is m5.utils.convert

The conversion functions incorrectly assumed that kibibytes are 'kiB'
rather than 'KiB' (correct).

Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39375
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
(cherry picked from commit b67b917345e85d6c02aa8c37dc40524eac5622c6)
---
M src/python/m5/util/convert.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 077b6b4..ae667b3 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -62,7 +62,7 @@
 'Gi': gibi,
 'G': giga,
 'M': mega,
-'ki': kibi,
+'Ki': kibi,
 'k': kilo,
 'Mi': mebi,
 'm': milli,
@@ -84,7 +84,7 @@
 'G' : gibi,
 'Mi': mebi,
 'M' : mebi,
-'ki': kibi,
+'Ki': kibi,
 'k' : kibi,
 }


--
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Gerrit-Branch: stable
Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Gerrit-Change-Number: 42783
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39758 )


Change subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code
..

arch, mem, cpu, systemc: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39758
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Bobby R. Bruce 
---
M src/arch/arm/fastmodel/SConscript
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/qos/QoSPolicy.py
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/systemc/tests/config.py
M src/systemc/tests/verify.py
M src/unittest/genini.py
17 files changed, 10 insertions(+), 48 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index f5516fa..21b3d3c 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 from itertools import cycle

 Import('*')
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index 53026c1..0305a02 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re
diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index e34e06e..8bab7b9 100755
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop,  
Rom


 class Bah(object):
diff --git a/src/arch/x86/isa/microops/fpop.isa  
b/src/arch/x86/isa/microops/fpop.isa

index 238fa93..346f0d6 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -105,8 +105,6 @@

 let {{

-import six
-
 # Make these empty strings so that concatenating onto
 # them will always work.
 header_output = ""
@@ -199,8 +197,7 @@

 return cls

-@six.add_metaclass(FpOpMeta)
-class FpUnaryOp(X86Microop):
+class FpUnaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

@@ -235,8 +232,7 @@
 "dataSize" : self.dataSize,
 "spm" : self.spm}

-@six.add_metaclass(FpOpMeta)
-class FpBinaryOp(X86Microop):
+class FpBinaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/limmop.isa  
b/src/arch/x86/isa/microops/limmop.isa

index b46be03..51310b4 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -106,16 +106,12 @@
 }};

 let {{
-import six
-if six.PY3:
-long = int
-
 class LimmOp(X86Microop):
 def __init__(self, dest, imm, dataSize="env.dataSize"):
 self.className = "Limm"
 self.mnemonic = "limm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 self.imm = imm
 self.dataSize = dataSize
@@ -145,7 +141,7 @@
 self.className = "Lfpimm"
 self.mnemonic = "lfpimm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 elif isinstance(imm, float):
 imm = "floatToBits64(%.16f)" % imm
diff --git a/src/arch/x86/isa/microops/mediaop.isa  
b/src/arch/x86/isa/microops/mediaop.isa

index 7e5fd10..e149d44 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -202,8 +202,7 @@
 return cls

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39757 )


Change subject: tests: Remove Python 2.7 glue code
..

tests: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39757
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/configs/gpu-ruby.py
M tests/gem5/configs/base_config.py
M tests/gem5/configs/checkpoint.py
M tests/gem5/configs/switcheroo.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/memory/test.py
M tests/main.py
M tests/run.py
9 files changed, 4 insertions(+), 17 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index a463fe3..b561d02 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -33,8 +33,6 @@
 #  Author: Brad Beckmann
 #

-from __future__ import print_function
-
 import m5
 from m5.objects import *
 from m5.defines import buildEnv
diff --git a/tests/gem5/configs/base_config.py  
b/tests/gem5/configs/base_config.py

index 5623db8..b18cecf 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -42,12 +42,10 @@
 from common import Options
 from common.Caches import *
 from ruby import Ruby
-from six import add_metaclass

 _have_kvm_support = 'BaseKvmCPU' in globals()

-@add_metaclass(ABCMeta)
-class BaseSystem(object):
+class BaseSystem(object, metaclass=ABCMeta):
 """Base system builder.

 This class provides some basic functionality for creating an ARM
diff --git a/tests/gem5/configs/checkpoint.py  
b/tests/gem5/configs/checkpoint.py

index a652094..3545095 100644
--- a/tests/gem5/configs/checkpoint.py
+++ b/tests/gem5/configs/checkpoint.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from multiprocessing import Process
 import sys
 import os
diff --git a/tests/gem5/configs/switcheroo.py  
b/tests/gem5/configs/switcheroo.py

index cb47f90..fb1db81 100644
--- a/tests/gem5/configs/switcheroo.py
+++ b/tests/gem5/configs/switcheroo.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5
 from m5.objects import *
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index 467eb43..5ffb248 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -44,7 +44,8 @@
 import threading
 import gzip

-from six.moves import urllib
+import urllib.error
+import urllib.request

 from testlib.fixture import Fixture
 from testlib.configuration import config, constants
diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index a0d782b..3dccebb 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import sys
 import os
 import os.path
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 7b839f2..db20ab5 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -28,7 +28,6 @@
 Test file for simple memory test
 TODO: Add stats checking
 '''
-import six

 from testlib import *

@@ -50,7 +49,7 @@


 for name, params in simple_mem_params:
-args = ['--' + key + '=' + val for key,val in six.iteritems(params)]
+args = ['--' + key + '=' + val for key,val in params.items()]

 gem5_verify_config(
 name='simple_mem_' + name,
diff --git a/tests/main.py b/tests/main.py
index 3287ef1..39717f6 100755
--- a/tests/main.py
+++ b/tests/main.py
@@ -5,7 +5,6 @@

 Discovers and runs all tests from a given root directory.
 '''
-from __future__ import print_function

 import sys
 import os
diff --git a/tests/run.py b/tests/run.py
index a8b612b..c3360ac 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re

--
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[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )


Change subject: tests: Remove Python 2.7 glue code from testlib
..

tests: Remove Python 2.7 glue code from testlib

Remove the dependency on six in testlib.

Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39759
Reviewed-by: Bobby R. Bruce 
Tested-by: kokoro 
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
 import os
 import re

-from six import add_metaclass
 from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol

 from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
 # one in the list will be saved.
 common_args = AttrDict({arg.name:arg for arg in common_args})

-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
 class ExtendAction(argparse.Action):
 def __call__(self, parser, namespace, values, option_string=None):
 items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@


 '''
-from __future__ import print_function
-
 import multiprocessing
 import os
 import sys
@@ -46,7 +44,7 @@
 import testlib.state as state
 import testlib.terminal as terminal

-from six.moves import queue as Queue
+from queue import Queue
 from testlib.configuration import constants


diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@

 import os
 import re
-import six
 import sys
 import traceback

diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
 '''
 import testlib.wrappers as wrappers

-from six import add_metaclass
-
 class LogLevel():
 Fatal = 0
 Error = 1
@@ -56,8 +54,7 @@
 RecordTypeCounterMetaclass.counter += 1


-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
 '''
 A generic object that is passed to the :class:`Log` and its handlers.

diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
 import fcntl
 import termios
 import struct
-import six

 # Intended usage example:
 #
@@ -85,7 +84,7 @@
 def __init__(self, cap_string):
 for i, c in enumerate(color_names):
 setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
 setattr(self, name, cap_string(cap))

 termcap = ColorStrings(cap_string)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39759
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Gerrit-Change-Number: 39759
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Testlib six dependency

[Andreas Sandberg via gem5-dev]

Hi Jason,

Thanks for confirming that. I have posted an update here: 
https://gem5-review.googlesource.com/c/public/gem5/+/39759

Since there is no upstream for testlib, should we move it into tests/ somewhere 
instead of keeping it in ext/?

Cheers,
Andreas

On 26/01/2021 16:21, Jason Lowe-Power wrote:
Hi Andreas,

There is no upstream for testlib. It's a purely gem5 project. We should fix it 
in tree.

Jason

On Tue, Jan 26, 2021 at 4:56 AM Andreas Sandberg via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
Hi Everyone,

I have just posted a series of patches [1] that get rid of 'six' as a
dependency in gem5. However, there is still a dependency on six coming
from testlib. What's the process there? Should we fix it upstream and
backport it or is testlib now effectively a gem5 project?

Cheers,
Abdreas

[1] https://gem5-review.googlesource.com/c/public/gem5/+/39758

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[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )



Change subject: tests: Remove Python 2.7 glue code from testlib
..

tests: Remove Python 2.7 glue code from testlib

Remove the dependency on six in testlib.

Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg 
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
 import os
 import re

-from six import add_metaclass
 from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol

 from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
 # one in the list will be saved.
 common_args = AttrDict({arg.name:arg for arg in common_args})

-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
 class ExtendAction(argparse.Action):
 def __call__(self, parser, namespace, values, option_string=None):
 items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@


 '''
-from __future__ import print_function
-
 import multiprocessing
 import os
 import sys
@@ -46,7 +44,7 @@
 import testlib.state as state
 import testlib.terminal as terminal

-from six.moves import queue as Queue
+from queue import Queue
 from testlib.configuration import constants


diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@

 import os
 import re
-import six
 import sys
 import traceback

diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
 '''
 import testlib.wrappers as wrappers

-from six import add_metaclass
-
 class LogLevel():
 Fatal = 0
 Error = 1
@@ -56,8 +54,7 @@
 RecordTypeCounterMetaclass.counter += 1


-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
 '''
 A generic object that is passed to the :class:`Log` and its handlers.

diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
 import fcntl
 import termios
 import struct
-import six

 # Intended usage example:
 #
@@ -85,7 +84,7 @@
 def __init__(self, cap_string):
 for i, c in enumerate(color_names):
 setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
 setattr(self, name, cap_string(cap))

 termcap = ColorStrings(cap_string)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39759
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Gerrit-Change-Number: 39759
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39755 )


Change subject: configs: Remove Python 2.7 glue code
..

configs: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39755
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/sc_main.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/nvm/sweep.py
M configs/nvm/sweep_hybrid.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
70 files changed, 16 insertions(+), 241 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 8477d77..591c044 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from common.SysPaths import script, disk, binary
 from os import environ as env
 from m5.defines import buildEnv
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd80c1a..bd68465 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -40,9 +40,6 @@
 # Configure the M5 cache hierarchy config in one place
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import m5
 from m5.objects import *
 from common.Caches import *
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 77213e8..1468b95 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -37,9 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5.defines import buildEnv
 from m5.objects import *

diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 27febe2..d34143c 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -33,9 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5 import fatal
 import m5

[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )


Change subject: util: Remove Python 2.7 glue code
..

util: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39756
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
 import os.path
 import pickle
 import shutil
-import six
 import subprocess
 import textwrap

@@ -145,9 +144,9 @@
 # Settings.
 #

-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 key = d.get('key', None)
 if key is not None:
 assert('default' in d)
@@ -157,9 +156,7 @@
 all_settings[key] = instance
 return cls

-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
 key = None

 @abc.abstractmethod
@@ -420,17 +417,15 @@
 # Steps of the build process.
 #

-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 number = d.get('number', None)
 if number is not None:
 all_steps[number] = cls()
 return cls

-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
 'Steps to set up a cross compiling gcc.'
 number = None

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
 # upgraders in private branches.


-
-from six.moves import configparser
+import configparser
 import glob, types, sys, os
 import os.path as osp

diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
 import re
 import sys

-from six import add_metaclass
-
 from . import style
 from . import sort_includes
 from .region import *
@@ -102,8 +100,7 @@
 return regions


-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
 """Base class for style verifiers

 Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
 """
 pass

-@add_metaclass(ABCMeta)
 class LineVerifier(Verifier):
 def check(self, filename, regions=all_regions, fobj=None,  
silent=False):

 close = False

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39455 )


Change subject: sim: Use the Temperature type in power/thermal models
..

sim: Use the Temperature type in power/thermal models

The thermal models currently work on temperatures in Celsius stored in
plain doubles. Switch to using Temperature instead and internal
processing in Kelvin. There should be no impact on the result since
all thermal processes work on temperature deltas.

Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39455
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
---
M src/dev/arm/rv_ctrl.cc
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.hh
9 files changed, 46 insertions(+), 41 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 2d80bc2..6cacb4d 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010,2013,2015 ARM Limited
+ * Copyright (c) 2010, 2013, 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -304,7 +304,7 @@
 // Temperature reported in uC
 ThermalModel * tm = system->getThermalModel();
 if (tm) {
-double t = tm->getTemp();
+double t = tm->getTemperature().toCelsius();
 if (t < 0)
 warn("Temperature below zero!\n");
 return fmax(0, t) * 100;
diff --git a/src/sim/power/mathexpr_powermodel.cc  
b/src/sim/power/mathexpr_powermodel.cc

index 4f3f927..e66d8d9 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, 2020 ARM Limited
+ * Copyright (c) 2016-2017, 2020-2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -86,7 +86,7 @@

 // Automatic variables:
 if (name == "temp") {
-return _temp;
+return _temp.toCelsius();
 } else if (name == "voltage") {
 return clocked_object->voltage();
 } else if (name=="clock_period") {
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index 42515ac..e79ecbc 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2018, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp.toCelsius());
+pms->setTemperature(p.ambient_temp);
 }

 dynamicPower
@@ -86,7 +86,7 @@
 }

 void
-PowerModel::thermalUpdateCallback(const double & temp)
+PowerModel::thermalUpdateCallback(const Temperature )
 {
 for (auto & pms: states_pm)
 pms->setTemperature(temp);
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e6f5431..3a0fc64 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2018 ARM Limited
+ * Copyright (c) 2016, 2018, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,6 +39,7 @@
 #define __SIM_POWER_POWER_MODEL_HH__

 #include "base/statistics.hh"
+#include "base/temperature.hh"
 #include "enums/PMType.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
@@ -75,9 +76,9 @@
 /**
  * Temperature update.
  *
- * @param temp Current temperature of the HW part (Celsius)
+ * @param temp Current temperature of the HW part
  */
-virtual void setTemperature(double temp) { _temp = temp; }
+virtual void setTemperature(Temperature temp) { _temp = temp; }

 void setClockedObject(ClockedObject * clkobj) {
 clocked_object = clkobj;
@@ -86,7 +87,7 @@
   protected:

 /** Current temperature */
-double _temp;
+Temperature _temp;

 /** The clocked object we belong to */
 ClockedObject * clocked_object;
@@ -125,18 +126,18 @@

 virtual void regProbePoints();

-void thermalUpdateCallback(const double & temp);
+void thermalUpd

[gem5-dev] Testlib six dependency

[Andreas Sandberg via gem5-dev]

Hi Everyone,

I have just posted a series of patches [1] that get rid of 'six' as a
dependency in gem5. However, there is still a dependency on six coming
from testlib. What's the process there? Should we fix it upstream and
backport it or is testlib now effectively a gem5 project?

Cheers,
Abdreas

[1] https://gem5-review.googlesource.com/c/public/gem5/+/39758

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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39755 )



Change subject: configs: Remove Python 2.7 glue code
..

configs: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a
Signed-off-by: Andreas Sandberg 
---
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/FileSystemConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/ObjectList.py
M configs/common/Options.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/sc_main.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/nvm/sweep.py
M configs/nvm/sweep_hybrid.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
70 files changed, 16 insertions(+), 241 deletions(-)



diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index 8477d77..591c044 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from common.SysPaths import script, disk, binary
 from os import environ as env
 from m5.defines import buildEnv
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index bd80c1a..bd68465 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -40,9 +40,6 @@
 # Configure the M5 cache hierarchy config in one place
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import m5
 from m5.objects import *
 from common.Caches import *
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 77213e8..1468b95 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -37,9 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5.defines import buildEnv
 from m5.objects import *

diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index 27febe2..d34143c 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -33,9 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from m5 import fatal
 import m5.objects

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6fd39a5..6665225 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -38,20 +38,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39757 )



Change subject: tests: Remove Python 2.7 glue code
..

tests: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Signed-off-by: Andreas Sandberg 
---
M tests/configs/gpu-ruby.py
M tests/gem5/configs/base_config.py
M tests/gem5/configs/checkpoint.py
M tests/gem5/configs/switcheroo.py
M tests/gem5/fixture.py
M tests/gem5/fs/linux/arm/run.py
M tests/gem5/memory/test.py
M tests/main.py
M tests/run.py
9 files changed, 4 insertions(+), 17 deletions(-)



diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py
index a463fe3..b561d02 100644
--- a/tests/configs/gpu-ruby.py
+++ b/tests/configs/gpu-ruby.py
@@ -33,8 +33,6 @@
 #  Author: Brad Beckmann
 #

-from __future__ import print_function
-
 import m5
 from m5.objects import *
 from m5.defines import buildEnv
diff --git a/tests/gem5/configs/base_config.py  
b/tests/gem5/configs/base_config.py

index 5623db8..b18cecf 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -42,12 +42,10 @@
 from common import Options
 from common.Caches import *
 from ruby import Ruby
-from six import add_metaclass

 _have_kvm_support = 'BaseKvmCPU' in globals()

-@add_metaclass(ABCMeta)
-class BaseSystem(object):
+class BaseSystem(object, metaclass=ABCMeta):
 """Base system builder.

 This class provides some basic functionality for creating an ARM
diff --git a/tests/gem5/configs/checkpoint.py  
b/tests/gem5/configs/checkpoint.py

index a652094..3545095 100644
--- a/tests/gem5/configs/checkpoint.py
+++ b/tests/gem5/configs/checkpoint.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from multiprocessing import Process
 import sys
 import os
diff --git a/tests/gem5/configs/switcheroo.py  
b/tests/gem5/configs/switcheroo.py

index cb47f90..fb1db81 100644
--- a/tests/gem5/configs/switcheroo.py
+++ b/tests/gem5/configs/switcheroo.py
@@ -33,8 +33,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5
 from m5.objects import *
diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index 467eb43..5ffb248 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -44,7 +44,8 @@
 import threading
 import gzip

-from six.moves import urllib
+import urllib.error
+import urllib.request

 from testlib.fixture import Fixture
 from testlib.configuration import config, constants
diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py
index a0d782b..3dccebb 100644
--- a/tests/gem5/fs/linux/arm/run.py
+++ b/tests/gem5/fs/linux/arm/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import sys
 import os
 import os.path
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 7b839f2..db20ab5 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -28,7 +28,6 @@
 Test file for simple memory test
 TODO: Add stats checking
 '''
-import six

 from testlib import *

@@ -50,7 +49,7 @@


 for name, params in simple_mem_params:
-args = ['--' + key + '=' + val for key,val in six.iteritems(params)]
+args = ['--' + key + '=' + val for key,val in params.items()]

 gem5_verify_config(
 name='simple_mem_' + name,
diff --git a/tests/main.py b/tests/main.py
index 3287ef1..39717f6 100755
--- a/tests/main.py
+++ b/tests/main.py
@@ -5,7 +5,6 @@

 Discovers and runs all tests from a given root directory.
 '''
-from __future__ import print_function

 import sys
 import os
diff --git a/tests/run.py b/tests/run.py
index a8b612b..c3360ac 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -36,8 +36,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39757
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168
Gerrit-Change-Number: 39757
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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To u

[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39758 )



Change subject: arch, mem, cpu, systemc: Remove Python 2.7 glue code
..

arch, mem, cpu, systemc: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/fastmodel/SConscript
M src/arch/micro_asm.py
M src/arch/micro_asm_test.py
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/cpu/BaseCPU.py
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/O3CPU.py
M src/cpu/simple/BaseSimpleCPU.py
M src/mem/qos/QoSPolicy.py
M src/mem/slicc/main.py
M src/mem/slicc/util.py
M src/systemc/tests/config.py
M src/systemc/tests/verify.py
M src/unittest/genini.py
17 files changed, 10 insertions(+), 48 deletions(-)



diff --git a/src/arch/arm/fastmodel/SConscript  
b/src/arch/arm/fastmodel/SConscript

index f5516fa..21b3d3c 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -35,7 +35,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 from itertools import cycle

 Import('*')
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py
index 53026c1..0305a02 100644
--- a/src/arch/micro_asm.py
+++ b/src/arch/micro_asm.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import re
diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
index e34e06e..8bab7b9 100755
--- a/src/arch/micro_asm_test.py
+++ b/src/arch/micro_asm_test.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop,  
Rom


 class Bah(object):
diff --git a/src/arch/x86/isa/microops/fpop.isa  
b/src/arch/x86/isa/microops/fpop.isa

index 238fa93..346f0d6 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -105,8 +105,6 @@

 let {{

-import six
-
 # Make these empty strings so that concatenating onto
 # them will always work.
 header_output = ""
@@ -199,8 +197,7 @@

 return cls

-@six.add_metaclass(FpOpMeta)
-class FpUnaryOp(X86Microop):
+class FpUnaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

@@ -235,8 +232,7 @@
 "dataSize" : self.dataSize,
 "spm" : self.spm}

-@six.add_metaclass(FpOpMeta)
-class FpBinaryOp(X86Microop):
+class FpBinaryOp(X86Microop, metaclass=FpOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/limmop.isa  
b/src/arch/x86/isa/microops/limmop.isa

index b46be03..51310b4 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -106,16 +106,12 @@
 }};

 let {{
-import six
-if six.PY3:
-long = int
-
 class LimmOp(X86Microop):
 def __init__(self, dest, imm, dataSize="env.dataSize"):
 self.className = "Limm"
 self.mnemonic = "limm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 self.imm = imm
 self.dataSize = dataSize
@@ -145,7 +141,7 @@
 self.className = "Lfpimm"
 self.mnemonic = "lfpimm"
 self.dest = dest
-if isinstance(imm, (int, long)):
+if isinstance(imm, int):
 imm = "ULL(%d)" % imm
 elif isinstance(imm, float):
 imm = "floatToBits64(%.16f)" % imm
diff --git a/src/arch/x86/isa/microops/mediaop.isa  
b/src/arch/x86/isa/microops/mediaop.isa

index 7e5fd10..e149d44 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -202,8 +202,7 @@
 return cls


-@six.add_metaclass(MediaOpMeta)
-class MediaOp(X86Microop):
+class MediaOp(X86Microop, metaclass=MediaOpMeta):
 # This class itself doesn't act as a microop
 abstract = True

diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index da1f9ae..c465dcc 100644
--- a/src/arc

[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )



Change subject: util: Remove Python 2.7 glue code
..

util: Remove Python 2.7 glue code

Remove uses of six and from __future__ imports as they are no longer
needed.

Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg 
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)



diff --git a/util/build_cross_gcc/build_cross_gcc.py  
b/util/build_cross_gcc/build_cross_gcc.py

index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
 import os.path
 import pickle
 import shutil
-import six
 import subprocess
 import textwrap

@@ -145,9 +144,9 @@
 # Settings.
 #

-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 key = d.get('key', None)
 if key is not None:
 assert('default' in d)
@@ -157,9 +156,7 @@
 all_settings[key] = instance
 return cls

-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
 key = None

 @abc.abstractmethod
@@ -420,17 +417,15 @@
 # Steps of the build process.
 #

-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
 def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
 number = d.get('number', None)
 if number is not None:
 all_steps[number] = cls()
 return cls

-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
 'Steps to set up a cross compiling gcc.'
 number = None

diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
 # upgraders in private branches.


-
-from six.moves import configparser
+import configparser
 import glob, types, sys, os
 import os.path as osp

diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
 import re
 import sys

-from six import add_metaclass
-
 from . import style
 from . import sort_includes
 from .region import *
@@ -102,8 +100,7 @@
 return regions


-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
 """Base class for style verifiers

 Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
 """
 pass

-@add_metaclass(ABCMeta)
 class LineVerifier(Verifier):
 def check(self, filename, regions=all_regions, fobj=None,  
silent=False):

 close = False

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFrequency and anyToLatency

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )


Change subject: python: Require a unit in anyToFrequency and anyToLatency
..

python: Require a unit in anyToFrequency and anyToLatency

The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.

Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39435
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 1d78f82..e66eb5c 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -199,32 +199,40 @@
 return toMetricFloat(value, 'latency', 's')

 def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""

-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""

-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def toNetworkBandwidth(value):
 return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

index a9c9d46..da61843 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
 self.assertEqual(conv('1kHz'), 1e-3)

 self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')

 def test_anyToFrequency(self):
 conv = convert.anyToFrequency

-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
 self.assertEqual(conv('42kHz'), 42e3)

 self.assertEqual(conv('0.1s'), 10.0)
 self.assertEqual(conv('1ms'), 1000.0)

 self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')

 def test_toNetworkBandwidth(self):
 conv = convert.toNetworkBandwidth

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Gerrit-Change-Number: 39435
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sa

[gem5-dev] Change in gem5/gem5[develop]: base, python: Add a Temperature type and associated param

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39218 )


Change subject: base, python: Add a Temperature type and associated param
..

base, python: Add a Temperature type and associated param

Add a class to represent a temperature. The class stores temperatures
in Kelvin and provides helper methods to convert to/from Celsius. The
corresponding param type automatically converts from Kelvin, Celsius,
and Fahrenheit to the underlying C++ type.

Change-Id: I5783cc4f4fecbea5aba9821dfc71bfa77c3f75a9
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39218
Maintainer: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/base/SConscript
A src/base/temperature.cc
A src/base/temperature.hh
A src/base/temperature.test.cc
M src/python/m5/params.py
M src/python/m5/util/convert.py
M src/python/pybind11/core.cc
M tests/pyunit/util/test_convert.py
8 files changed, 478 insertions(+), 2 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/SConscript b/src/base/SConscript
index 3937314..204ed3c 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -72,6 +72,8 @@
 GTest('str.test', 'str.test.cc', 'str.cc')
 Source('time.cc')
 Source('version.cc')
+Source('temperature.cc')
+GTest('temperature.test', 'temperature.test.cc', 'temperature.cc')
 Source('trace.cc')
 GTest('trie.test', 'trie.test.cc')
 Source('types.cc')
diff --git a/src/base/temperature.cc b/src/base/temperature.cc
new file mode 100644
index 000..b1d9c9a
--- /dev/null
+++ b/src/base/temperature.cc
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "base/temperature.hh"
+
+Temperature
+Temperature::fromKelvin(double _value)
+{
+return Temperature(_value);
+}
+
+Temperature
+Temperature::fromCelsius(double _value)
+{
+return Temperature(273.15 + _value);
+}
+
+Temperature
+Temperature::fromFahrenheit(double _value)
+{
+return Temperature((_value + 459.67) / 1.8);
+}
+
+double
+Temperature::toFahrenheit() const
+{
+return value * 1.8 - 459.67;
+}
+
+std::ostream &
+operator<<(std::ostream , const Temperature )
+{
+out << temp.value << "K";
+return out;
+}
diff --git a/src/base/temperature.hh b/src/base/temperature.hh
new file mode 100644
index 000..bcb5199
--- /dev/null
+++ b/src/base/temperature.hh
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other

[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature param type

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39219 )


Change subject: sim: Use the Temperature param type
..

sim: Use the Temperature param type

Add support for passing typed temperatures using the new Temperature
param type.

Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39219
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/sim/power/PowerModel.py
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/power_model.cc
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_model.cc
6 files changed, 11 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py
index 2047c64..cfbd8cb 100644
--- a/src/sim/power/PowerModel.py
+++ b/src/sim/power/PowerModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2018 ARM Limited
+# Copyright (c) 2016-2018, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -63,4 +63,4 @@
 pm_type = Param.PMType("All", "Type of power model")

 # Ambient temperature to be used when no thermal model is present
-ambient_temp = Param.Float(25.0, "Ambient temperature")
+ambient_temp = Param.Temperature("25.0C", "Ambient temperature")
diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py
index 3fd5cad..57c53b2 100644
--- a/src/sim/power/ThermalDomain.py
+++ b/src/sim/power/ThermalDomain.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -46,4 +46,4 @@
 ]

 # Static temperature which may change over time
-initial_temperature = Param.Float(25.0, "Initial temperature")
+initial_temperature = Param.Temperature("25.0C", "Initial temperature")
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index 2894dd8..90710e1 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@
 ]

 # Static temperature which may change over time
-temperature = Param.Float(25.0, "Operational temperature in Celsius")
+temperature = Param.Temperature("25.0C", "Operational temperature")


 # Represents a thermal capacitor
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index fbc67d3..42515ac 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp);
+pms->setTemperature(p.ambient_temp.toCelsius());
 }

 dynamicPower
diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index a5eb33c..b0868be 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -49,7 +49,7 @@
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
-: SimObject(p), _initTemperature(p.initial_temperature),
+: SimObject(p), _initTemperature(p.initial_temperature.toCelsius()),
 node(NULL), subsystem(NULL),
 ADD_STAT(currentTemp, "Temperature in centigrade degrees")
 {
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index a37240b..c57e284 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -51,7 +51,7 @@
  * ThermalReference
  */
 ThermalReference::ThermalReference(const Params )
-: SimObject(p), _temperature(p.temperature), node(NULL)
+: SimObject(p), _temperature(p.temperature.toCelsius()), node(NULL)
 {
 }


--
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add Python unit tests for m5.util.convert

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39377 )


Change subject: tests: Add Python unit tests for m5.util.convert
..

tests: Add Python unit tests for m5.util.convert

Python unit tests need to be run from within gem5. This change adds a
script to run unit tests (tests/run_pyunit.py) and a unit test for
m5.util.convert.

The tests can be run as follows:

  ./build/NULL/gem5.opt tests/run_pyunit.py

Change-Id: I80d1aabbe1d87b01b48280972f9418317e648779
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39377
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Daniel Carvalho 
---
A tests/pyunit/__init__.py
A tests/pyunit/util/__init__.py
A tests/pyunit/util/test_convert.py
A tests/run_pyunit.py
4 files changed, 330 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/pyunit/__init__.py b/tests/pyunit/__init__.py
new file mode 100644
index 000..8b13789
--- /dev/null
+++ b/tests/pyunit/__init__.py
@@ -0,0 +1 @@
+
diff --git a/tests/pyunit/util/__init__.py b/tests/pyunit/util/__init__.py
new file mode 100644
index 000..8b13789
--- /dev/null
+++ b/tests/pyunit/util/__init__.py
@@ -0,0 +1 @@
+
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

new file mode 100644
index 000..6d02b51
--- /dev/null
+++ b/tests/pyunit/util/test_convert.py
@@ -0,0 +1,277 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2021 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import unittest
+
+from m5.util import convert
+
+def _ip(*args):
+return (args[0] << 24) | (args[1] << 16) | (args[2] << 8) | args[3]
+
+class ConvertTestSuite(unittest.TestCase):
+"""Test cases for unit conversion"""
+
+def test_toMetricFloat(self):
+def conv(x):
+return convert.toMetricFloat(x, 'value', 'X')
+
+self.assertEqual(conv('42'),  42e0)
+self.assertEqual(conv('42.5'),  42.5e0)
+self.assertEqual(conv('42kX'), 42e3)
+self.assertEqual(conv('42.5kX'), 42.5e3)
+self.assertEqual(conv('42MX'), 42e6)
+self.assertEqual(conv('42GX'), 42e9)
+self.assertEqual(conv('42TX'), 42e12)
+self.assertEqual(conv('42PX'), 42e15)
+self.assertEqual(conv('42EX'), 42e18)
+
+self.assertEqual(conv('42KiX'), 42 * 2**10)
+self.assertEqual(conv('42MiX'), 42 * 2**20)
+self.assertEqual(conv('42GiX'), 42 * 2**30)
+self.assertEqual(conv('42TiX'), 42 * 2**40)
+self.assertEqual(conv('42PiX'), 42 * 2**50)
+self.assertEqual(conv('42EiX'), 42 * 2**60)
+
+self.assertRaises(ValueError, conv, '42k')
+self.assertR

[gem5-dev] Change in gem5/gem5[develop]: sim: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39579 )


Change subject: sim: Consistently use ISO prefixes
..

sim: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39579
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/Process.py
M src/sim/syscall_emul.hh
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
 useArchPT = Param.Bool('false', 'maintain an in-memory version of the  
page\

 table in an architecture-specific format')
 kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in  
SE')

-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')

 uid = Param.Int(100, 'user id')
 euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 581e8db..d6afec8 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1822,7 +1822,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1865,7 +1865,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Gerrit-Change-Number: 39579
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39577 )


Change subject: python: Consistently use ISO prefixes
..

python: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39577
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/params.py
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 5ff5071..6227fad 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -678,7 +678,7 @@

 class MemorySize(CheckedInt):
 cxx_type = 'uint64_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 64
 unsigned = True
 def __init__(self, value):
@@ -690,7 +690,7 @@

 class MemorySize32(CheckedInt):
 cxx_type = 'uint32_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 32
 unsigned = True
 def __init__(self, value):
@@ -710,7 +710,7 @@
 else:
 try:
 # Often addresses are referred to with sizes. Ex: A device
-# base address is at "512MB".  Use toMemorySize() to  
convert
+# base address is at "512MiB".  Use toMemorySize() to  
convert
 # these into addresses. If the address is not specified  
with a
 # "size", an exception will occur and numeric translation  
will

 # proceed below.
@@ -1734,7 +1734,7 @@

 class MemoryBandwidth(float,ParamValue):
 cxx_type = 'float'
-ex_str = "1GB/s"
+ex_str = "1GiB/s"
 cmd_line_settable = True

 def __new__(cls, value):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39577
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Gerrit-Change-Number: 39577
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39575 )


Change subject: arch-arm, dev-arm: Consistently use ISO prefixes
..

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I9b47194d26d71c8ebedda6c31a5bac54b600d3bf
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39575
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/dev/arm/FlashDevice.py
M src/dev/arm/RealView.py
5 files changed, 49 insertions(+), 49 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index e445590..8674edc 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -53,10 +53,10 @@
 files_root_dir = Param.String("",
 "Host root directory for files handled by Semihosting")

-mem_reserve = Param.MemorySize("32MB",
+mem_reserve = Param.MemorySize("32MiB",
 "Amount of memory to reserve at the start of the address map.  
This "

 "memory won't be used by the heap reported to an application.");
-stack_size = Param.MemorySize("32MB", "Application stack size");
+stack_size = Param.MemorySize("32MiB", "Application stack size");

 time = Param.Time('01/01/2009',
   "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..7f19adb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -648,7 +648,7 @@
 MISCREG_TTBR0, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t0sz;
 currState->isUncacheable = currState->ttbcr.irgn0 == 0;
-if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
+if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GiB
 start_lookup_level = L2;
 } else if (currState->vaddr >= ttbr1_min) {
 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@
 MISCREG_TTBR1, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t1sz;
 currState->isUncacheable = currState->ttbcr.irgn1 == 0;
-// Lower limit >= 3 GB
+// Lower limit >= 3 GiB
 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
 start_lookup_level = L2;
 } else {
@@ -2379,16 +2379,16 @@
 pageSizes // see DDI 0487A D4-1661
 .init(10)
 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
-pageSizes.subname(0, "4K");
-pageSizes.subname(1, "16K");
-pageSizes.subname(2, "64K");
-pageSizes.subname(3, "1M");
-pageSizes.subname(4, "2M");
-pageSizes.subname(5, "16M");
-pageSizes.subname(6, "32M");
-pageSizes.subname(7, "512M");
-pageSizes.subname(8, "1G");
-pageSizes.subname(9, "4TB");
+pageSizes.subname(0, "4KiB");
+pageSizes.subname(1, "16KiB");
+pageSizes.subname(2, "64KiB");
+pageSizes.subname(3, "1MiB");
+pageSizes.subname(4, "2MiB&qu

[gem5-dev] Change in gem5/gem5[develop]: mem: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39576 )


Change subject: mem: Consistently use ISO prefixes
..

mem: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39576
Reviewed-by: Richard Cooper 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
7 files changed, 49 insertions(+), 48 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 4c21d52..e1941c3 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -44,9 +44,10 @@
 abstract = True
 cxx_header = "mem/abstract_mem.hh"

-# A default memory size of 128 MB (starting at 0) is used to
+# A default memory size of 128 MiB (starting at 0) is used to
 # simplify the regressions
-range = Param.AddrRange('128MB', "Address range (potentially  
interleaved)")

+range = Param.AddrRange('128MiB',
+"Address range (potentially interleaved)")
 null = Param.Bool(False, "Do not store data, always return zero")

 # All memories are passed to the global physical memory, and
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 85a6092..4f59498 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -259,7 +259,7 @@
 # an 8x8 configuration.
 class DDR3_1600_8x8(DRAMInterface):
 # size of device in bytes
-device_size = '512MB'
+device_size = '512MiB'

 # 8x8 configuration, 8 devices each with an 8-bit interface
 device_bus_width = 8
@@ -268,7 +268,7 @@
 burst_length = 8

 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
-device_rowbuffer_size = '1kB'
+device_rowbuffer_size = '1KiB'

 # 8x8 configuration, so 8 devices
 devices_per_rank = 8
@@ -338,7 +338,7 @@
 # [2] High performance AXI-4.0 based interconnect for extensible smart  
memory

 # cubes (E. Azarkhish et. al)
 # Assumed for the HMC model is a 30 nm technology node.
-# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory  
(4
+# The modelled HMC consists of 4 Gbit layers which sum up to 2GiB of  
memory (4

 # layers).
 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
 # In order to be able to use the same controller used for 2D DRAM  
generations

@@ -354,8 +354,8 @@
 # of the HMC
 class HMC_2500_1x32(DDR3_1600_8x8):
 # size of device
-# two banks per device with each bank 4MB [2]
-device_size = '8MB'
+# two banks per device with each bank 4MiB [2]
+device_size = '8MiB'

 # 1x32 configuration, 1 device with 32 TSVs [2]
 device_bus_width = 32
@@ -458,11 +458,11 @@
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
 # in an 16x4 configuration.
-# Total channel capacity is 32GB
-# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
+# Total channel capacity is 32GiB
+# 16 devices/rank * 2 ranks/channel * 1GiB/device = 32GiB/channel
 class DD

[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39584 )


Change subject: python: Remove Python 2.7 compatibility code
..

python: Remove Python 2.7 compatibility code

We don't support Python 2.7 anymore. Remove glue code like the six
dependency and "from __future__" imports from gem5's standard library.

Change-Id: I71834c325f86ff0329b222be87794ead96081f05
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39584
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
---
M src/python/importer.py
M src/python/m5/SimObject.py
M src/python/m5/__init__.py
M src/python/m5/core.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/ext/__init__.py
M src/python/m5/internal/params.py
M src/python/m5/main.py
M src/python/m5/objects/__init__.py
M src/python/m5/options.py
M src/python/m5/params.py
M src/python/m5/proxy.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
M src/python/m5/ticks.py
M src/python/m5/trace.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/convert.py
M src/python/m5/util/dot_writer.py
M src/python/m5/util/fdthelper.py
M src/python/m5/util/grammar.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/pybind.py
M src/python/m5/util/terminal.py
28 files changed, 32 insertions(+), 133 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/importer.py b/src/python/importer.py
index c29fb7b..b89b4a8 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Simple importer that allows python to import data from a dict of
 # code objects.  The keys are the module path, and the items are the
 # filename and bytecode of the file.
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b47d98d..1697237 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -38,13 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-from six import add_metaclass
-import six
-if six.PY3:
-long = int
-
 import sys
 from types import FunctionType, MethodType, ModuleType
 from functools import wraps
@@ -1178,8 +1171,7 @@
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
-@add_metaclass(MetaSimObject)
-class SimObject(object):
+class SimObject(object, metaclass=MetaSimObject):
 # Specify metaclass.  Any class inheriting from SimObject will
 # get this metaclass.
 type = 'SimObject'
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 309764d..254d9a6 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Import useful subpackages of M5, but *only* when run as an m5
 # script.  This is mostly to keep backward compatibility with existing
 # scripts while allowing new SCons code to operate properly.
diff --git a/src/python/m5/core.py b/src/python/m5/core.py
index 34d54bc..fcbf4aa 100644
--- a/src/python/m5/core.py
+++ b/src/python/m5/core.py
@@ -36,8 +36,5 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from _m5.core import setOutputDir
 from _m5.loader import setInterpDir
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index 6b45b16..10d0980 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from collections import Mapping

 import _m5.debug
diff --git a/src/python/m5/event.py b/src/python/m5/event.py
index 9b5532c..f0230cf 100644
--- a/src/python/m5/event.py
+++ b/src/python/m5/event.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 

[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39585 )


Change subject: scons: Remove Python 2.7 compatibility code
..

scons: Remove Python 2.7 compatibility code

Remove the dependency on six and most 'import x from __future__'. A
few instances of imports from the future have been left in place to
ensure that Python 2.7 users still get an error message when invoking
scons.

Change-Id: I366275a6040f0084e91198b5b5c2a648bffbf2d2
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39585
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
---
M SConstruct
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M site_scons/gem5_scons/__init__.py
M site_scons/site_tools/git.py
M src/SConscript
M src/mem/ruby/SConscript
M src/systemc/tests/SConscript
9 files changed, 5 insertions(+), 26 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index b5505ff..4cf2f10 100755
--- a/SConstruct
+++ b/SConstruct
@@ -75,8 +75,6 @@
 #
 ###

-from __future__ import print_function
-
 # Global Python includes
 import atexit
 import itertools
diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index 3bf5b30..e2cc847 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -28,8 +28,6 @@
 #
 # Authors: Nathan Binkert

-from __future__ import print_function
-
 import os, subprocess

 Import('main')
diff --git a/ext/systemc/SConscript b/ext/systemc/SConscript
index cb0c61d..0b6fb0c 100644
--- a/ext/systemc/SConscript
+++ b/ext/systemc/SConscript
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 import os
 from m5.util.terminal import get_termcap

diff --git a/ext/systemc/src/sysc/kernel/SConscript.sc  
b/ext/systemc/src/sysc/kernel/SConscript.sc

index ac79c2f..0e21f74 100644
--- a/ext/systemc/src/sysc/kernel/SConscript.sc
+++ b/ext/systemc/src/sysc/kernel/SConscript.sc
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 Import('systemc', 'SystemCSource')

 SystemCSource(
diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 4208cf1..708002f 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import textwrap
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index 87738b8..a77cffb 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -38,13 +38,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 import os
 import sys

 import gem5_scons.util
 from m5.util import readCommand
-from six.moves import input

 git_style_message = """
 You're missing the gem5 style or commit message hook. These hooks help
diff --git a/src/SConscript b/src/SConscript
index b55f485..dc57260 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -37,8 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import array
 import bisect
 import distutils.spawn
@@ -46,7 +44,6 @@
 import imp
 import os
 import re
-import six
 import sys
 import zlib

@@ -144,8 +141,7 @@
 super(SourceMeta, cls).__init__(name, bases, dict)
 cls.all = SourceList()

-@six.add_metaclass(SourceMeta)
-class SourceFile(object):
+class SourceFile(object, metaclass=SourceMeta):
 '''Base object that encapsulates the notion of a source file.
 This includes, the source node, target node, various manipulations
 of those.  A source file also specifies a set of tags which
@@ -157,14 +153,14 @@
 def __init__(self, source, tags=None, add_tags=None, append=None):
 if tags is None:
 tags='gem5 lib'
-if isinstance(tags, six.string_types):
+if isinstance(tags, str):
 tags = set([tags])
 if not isinstance(tags, set):
 tags = set(tags)
 self.tags = tags

 if add_tags:
-if isinstance(add_tags, six.string_types):
+if isinstance(add_tags, str):
 add_tags = set([add_tags])
 if not isinstance(add_tags, set):
 add_tags = set(add_tags)
@@ -266,7 +262,7 @@
 cpp_code(sym

[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39578 )


Change subject: dev: Consistently use ISO prefixes
..

dev: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39578
Reviewed-by: Richard Cooper 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
3 files changed, 20 insertions(+), 19 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index dd878e2..e5c5562 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -92,10 +92,11 @@
 type = 'EtherSwitch'
 cxx_header = "dev/net/etherswitch.hh"
 dump = Param.EtherDump(NULL, "dump object")
-fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in bits "

-  "per second")
+fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in "

+  "bits per second")
 interface = VectorEtherInt("Ethernet Interface")
-output_buffer_size = Param.MemorySize('1MB', "size of output port  
buffers")

+output_buffer_size = Param.MemorySize('1MiB',
+  "size of output port buffers")
 delay = Param.Latency('0us', "packet transmit delay")
 delay_var = Param.Latency('0ns', "packet transmit delay variability")
 time_to_live = Param.Latency('10ms', "time to live of MAC address  
maping")

@@ -139,8 +140,8 @@
 cxx_header = "dev/net/i8254xGBe.hh"
 hardware_address = Param.EthernetAddr(NextEthernetAddr,
 "Ethernet Hardware Address")
-rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
-tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
+rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
+tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
 rx_desc_cache_size = Param.Int(64,
 "Number of enteries in the rx descriptor cache")
 tx_desc_cache_size = Param.Int(64,
@@ -152,7 +153,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BAR0 = PciMemBar(size='128kB')
+BAR0 = PciMemBar(size='128KiB')
 MaximumLatency = 0x00
 MinimumGrant = 0xff
 InterruptLine = 0x1e
@@ -195,8 +196,8 @@

 rx_delay = Param.Latency('1us', "Receive Delay")
 tx_delay = Param.Latency('1us', "Transmit Delay")
-rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
-tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
+rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
+tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")

 rx_filter = Param.Bool(True, "Enable Receive Filter")
 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
@@ -218,7 +219,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BARs = (PciIoBar(size='256B'), PciMemBa

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39581 )


Change subject: configs: Remove Python 2 compatibility code in Arm configs
..

configs: Remove Python 2 compatibility code in Arm configs

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39581
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/arm/workloads.py
8 files changed, 1 insertion(+), 31 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 04f60a1..011883b 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -39,9 +39,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index e3cee1e..52613c6 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -35,20 +35,12 @@

 # System components used by the bigLITTLE.py configuration script

-from __future__ import print_function
-from __future__ import absolute_import
-
-import six
-
 import m5
 from m5.objects import *
 m5.util.addToPath('../../')
 from common.Caches import *
 from common import ObjectList

-if six.PY3:
-long = int
-
 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()

@@ -320,7 +312,7 @@
 self.iobridge = Bridge(delay='50ns')
 # Device DMA -> MEM
 mem_range = self.realview._mem_regions[0]
-assert long(mem_range.size()) >= long(Addr(mem_size))
+assert int(mem_range.size()) >= int(Addr(mem_size))
 self.mem_ranges = [
 AddrRange(start=mem_range.start, size=mem_size) ]

diff --git a/configs/example/arm/dist_bigLITTLE.py  
b/configs/example/arm/dist_bigLITTLE.py

index 1d82666..6d35e53 100644
--- a/configs/example/arm/dist_bigLITTLE.py
+++ b/configs/example/arm/dist_bigLITTLE.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # configuration to enabe dist-gem5 siulations of big.LITTLE systems.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 090e071..85213ee 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -36,10 +36,6 @@
 # This is an example configuration script for full system simulation of
 # a generic ARM bigLITTLE system.

-
-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os
 import sys
diff --git a/configs/example/arm/fs_power.py  
b/configs/example/arm/fs_power.py

index 72c6292..1c7b6b7 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # with example power models.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 8dee137..9d0f0d2 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 8b1dbd2..23da8e7 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

index ce48cdd..1fb9d

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )


Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..

arch-arm, dev-arm: Remove Python 2 compatibility code

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39580
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
 # root instead of appended.

 def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
 node.append(FdtPropertyStrings("device_type", ["memory"]))
 node.append(FdtPropertyWords("reg",
 state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@

 def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
 node.append(FdtPropertyWords("reg",
 state.addrCells(pio_addr) +
 state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
 idreg = Param.UInt32(0x, "ID Register, SYS_ID")

 def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
 node.appendCompatible("arm,vexpress-sysreg")
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@

 def generateDeviceTree(self, state):
 phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
 node.appendCompatible("arm,vexpress-osc")
 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
  [0x1, int(self.device)]))
@@ -595,7 +595,7 @@
 super(MmioSRAM, self).__init__(**kwargs)

 def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
 node.appendCompatible(["mmio-sram"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
 def generateDeviceTree(self, state):
 reg_addr = self.reg_map.start
 reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
 node.appendCompatible("arm,smmu-v3")
 node.append(FdtPropertyWords("reg",
 state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
 scp = Param.Scp(Parent.any, "System Control Processor")

 def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
 node.appendCompatible(["arm,mhu", "arm,primecell"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39580
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32f

[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39582 )


Change subject: configs: Weed out old port terminology in Arm examples
..

configs: Weed out old port terminology in Arm examples

Stop using the deprecated port names in Arm example scripts.

Change-Id: I11fea3e0df945ac64075b647766570604b70cad8
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39582
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/common/MemConfig.py
M configs/example/arm/devices.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_se.py
4 files changed, 20 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 63301ab..94b1655 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -151,7 +151,7 @@
 system.external_memory = m5.objects.ExternalSlave(
 port_type="tlm_slave",
 port_data=opt_tlm_memory,
-port=system.membus.master,
+port=system.membus.mem_side_ports,
 addr_ranges=system.mem_ranges)
 system.workload.addr_check = False
 return
@@ -269,12 +269,12 @@
 for i in range(len(mem_ctrls)):
 if opt_mem_type == "HMC_2500_1x32":
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar[i/4].master
+mem_ctrls[i].port = xbar[i/4].mem_side_ports
 # Set memory device size. There is an independent controller
 # for each vault. All vaults are same size.
 mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size
 else:
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar.master
+mem_ctrls[i].port = xbar.mem_side_ports

 subsystem.mem_ctrls = mem_ctrls
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 52613c6..9ef4d70 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -151,7 +151,7 @@
 self.l2 = self._l2_type()
 for cpu in self.cpus:
 cpu.connectAllPorts(self.toL2Bus)
-self.toL2Bus.master = self.l2.cpu_side
+self.toL2Bus.mem_side_ports = self.l2.cpu_side

 def addPMUs(self, ints, events=[]):
 """
@@ -181,7 +181,7 @@

 def connectMemSide(self, bus):
 try:
-self.l2.mem_side = bus.slave
+self.l2.mem_side = bus.cpu_side_ports
 except AttributeError:
 for cpu in self.cpus:
 cpu.connectAllPorts(bus)
@@ -223,8 +223,9 @@
 ])

 gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
-gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,  
gem5=system.iobus.slave)

-gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
+gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,
+gem5=system.iobus.cpu_side_ports)
+gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports)
 gic_g2t.addr_ranges = gic.get_addr_ranges()
 gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 gic.amba_s = gic_t2a.amba
@@ -255,7 +256,7 @@
 self.cpus = [ cpu ]

 a2t = AmbaToTlmBridge64(amba=cpu.amba)
-t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
+t2g = TlmToGem5Bridge64(tlm=a2t.tlm,  
gem5=system.membus.cpu_side_ports)

 system.gic_hub.a2t = a2t
 system.gic_hub.t2g = t2g

@@ -330,21 +331,21 @@
 self.realview.attachPciDevice(dev, self.iobus)

 def connect(self):
-self.iobridge.master = self.iobus.slave
-self.iobridge.slave = self.membus.master
+self.iobridge.mem_side_port = self.iobus.cpu_side_ports
+self.iobridge.cpu_side_port = self.membus.mem_side_ports

 if self._caches:
-self.iocache.mem_side = self.membus.slave
-self.iocache.cpu_side = self.iobus.master
+self.iocache.mem_side = self.membus.cpu_side_ports
+self.iocache.cpu_side = self.iobus.mem_side_ports
 else:
-self.dmabridge.master = self.membus.slave
-self.dmabridge.slave = self.iobus.master
+self.dmabridge.mem_side_port = self.membus.cpu_side_ports
+self.dmabridge.cpu_side_port = self.iobus.mem_side_ports

 if hasattr(self.realview.gic, 'cpu_addr'):
 self.gic_cpu_addr = self.realview.gic.cpu_addr
 self.realview.attachOnChipIO(self.membus, self.iobridge)
   

[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39584 )



Change subject: python: Remove Python 2.7 compatibility code
..

python: Remove Python 2.7 compatibility code

We don't support Python 2.7 anymore. Remove glue code like the six
dependency and "from __future__" imports from gem5's standard library.

Change-Id: I71834c325f86ff0329b222be87794ead96081f05
Signed-off-by: Andreas Sandberg 
---
M src/python/importer.py
M src/python/m5/SimObject.py
M src/python/m5/__init__.py
M src/python/m5/core.py
M src/python/m5/debug.py
M src/python/m5/event.py
M src/python/m5/ext/__init__.py
M src/python/m5/internal/params.py
M src/python/m5/main.py
M src/python/m5/objects/__init__.py
M src/python/m5/options.py
M src/python/m5/params.py
M src/python/m5/proxy.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
M src/python/m5/ticks.py
M src/python/m5/trace.py
M src/python/m5/util/__init__.py
M src/python/m5/util/attrdict.py
M src/python/m5/util/code_formatter.py
M src/python/m5/util/convert.py
M src/python/m5/util/dot_writer.py
M src/python/m5/util/fdthelper.py
M src/python/m5/util/grammar.py
M src/python/m5/util/jobfile.py
M src/python/m5/util/multidict.py
M src/python/m5/util/pybind.py
M src/python/m5/util/terminal.py
28 files changed, 32 insertions(+), 133 deletions(-)



diff --git a/src/python/importer.py b/src/python/importer.py
index c29fb7b..b89b4a8 100644
--- a/src/python/importer.py
+++ b/src/python/importer.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Simple importer that allows python to import data from a dict of
 # code objects.  The keys are the module path, and the items are the
 # filename and bytecode of the file.
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index b47d98d..1697237 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -38,13 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-from six import add_metaclass
-import six
-if six.PY3:
-long = int
-
 import sys
 from types import FunctionType, MethodType, ModuleType
 from functools import wraps
@@ -1178,8 +1171,7 @@
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
-@add_metaclass(MetaSimObject)
-class SimObject(object):
+class SimObject(object, metaclass=MetaSimObject):
 # Specify metaclass.  Any class inheriting from SimObject will
 # get this metaclass.
 type = 'SimObject'
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 309764d..254d9a6 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -24,9 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 # Import useful subpackages of M5, but *only* when run as an m5
 # script.  This is mostly to keep backward compatibility with existing
 # scripts while allowing new SCons code to operate properly.
diff --git a/src/python/m5/core.py b/src/python/m5/core.py
index 34d54bc..fcbf4aa 100644
--- a/src/python/m5/core.py
+++ b/src/python/m5/core.py
@@ -36,8 +36,5 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-from __future__ import absolute_import
-
 from _m5.core import setOutputDir
 from _m5.loader import setInterpDir
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index 6b45b16..10d0980 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -24,8 +24,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 from collections import Mapping

 import _m5.debug
diff --git a/src/python/m5/event.py b/src/python/m5/event.py
index 9b5532c..f0230cf 100644
--- a/src/python/m5/event.py
+++ b/src/python/m5/event.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import m5
 import _m5.event

diff --git a/src/python/m5/ext/__init__.py b/src/python/m5/ext/__init__.py
index f950c98..cdd1f42 100644
--- a/src/pyt

[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39581 )



Change subject: configs: Remove Python 2 compatibility code in Arm configs
..

configs: Remove Python 2 compatibility code in Arm configs

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad
Signed-off-by: Andreas Sandberg 
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/arm/workloads.py
8 files changed, 1 insertion(+), 31 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 04f60a1..011883b 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -39,9 +39,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index e3cee1e..52613c6 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -35,20 +35,12 @@

 # System components used by the bigLITTLE.py configuration script

-from __future__ import print_function
-from __future__ import absolute_import
-
-import six
-
 import m5
 from m5.objects import *
 m5.util.addToPath('../../')
 from common.Caches import *
 from common import ObjectList

-if six.PY3:
-long = int
-
 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()

@@ -320,7 +312,7 @@
 self.iobridge = Bridge(delay='50ns')
 # Device DMA -> MEM
 mem_range = self.realview._mem_regions[0]
-assert long(mem_range.size()) >= long(Addr(mem_size))
+assert int(mem_range.size()) >= int(Addr(mem_size))
 self.mem_ranges = [
 AddrRange(start=mem_range.start, size=mem_size) ]

diff --git a/configs/example/arm/dist_bigLITTLE.py  
b/configs/example/arm/dist_bigLITTLE.py

index 1d82666..6d35e53 100644
--- a/configs/example/arm/dist_bigLITTLE.py
+++ b/configs/example/arm/dist_bigLITTLE.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # configuration to enabe dist-gem5 siulations of big.LITTLE systems.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 090e071..85213ee 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -36,10 +36,6 @@
 # This is an example configuration script for full system simulation of
 # a generic ARM bigLITTLE system.

-
-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os
 import sys
diff --git a/configs/example/arm/fs_power.py  
b/configs/example/arm/fs_power.py

index 72c6292..1c7b6b7 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -36,9 +36,6 @@
 # This configuration file extends the example ARM big.LITTLE(tm)
 # with example power models.

-from __future__ import print_function
-from __future__ import absolute_import
-
 import argparse
 import os

diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index 8dee137..9d0f0d2 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 8b1dbd2..23da8e7 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -38,9 +38,6 @@
 at: http://www.arm.com/ResearchEnablement/SystemModeling
 """

-from __future__ import print_function
-from __future__ import absolute_import
-
 import os
 import m5
 from m5.util import addToPath
diff --git a/configs/example/arm/workloads.py  
b/configs/example/arm/workloads.py

index ce48cdd..1fb9d00 100644
--- a/configs/example/arm/workloads.py
+++ b/configs/example/arm/workloads.py
@@ -34,9 +34,6 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #

-from __future__ import print_function
-from __future__ import absolute_import
-
 import inspect
 import m5
 from m5.objects import *

--
To view, visit

[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39582 )



Change subject: configs: Weed out old port terminology in Arm examples
..

configs: Weed out old port terminology in Arm examples

Stop using the deprecated port names in Arm example scripts.

Change-Id: I11fea3e0df945ac64075b647766570604b70cad8
Signed-off-by: Andreas Sandberg 
---
M configs/common/MemConfig.py
M configs/example/arm/devices.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_se.py
4 files changed, 20 insertions(+), 19 deletions(-)



diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 63301ab..94b1655 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -151,7 +151,7 @@
 system.external_memory = m5.objects.ExternalSlave(
 port_type="tlm_slave",
 port_data=opt_tlm_memory,
-port=system.membus.master,
+port=system.membus.mem_side_ports,
 addr_ranges=system.mem_ranges)
 system.workload.addr_check = False
 return
@@ -269,12 +269,12 @@
 for i in range(len(mem_ctrls)):
 if opt_mem_type == "HMC_2500_1x32":
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar[i/4].master
+mem_ctrls[i].port = xbar[i/4].mem_side_ports
 # Set memory device size. There is an independent controller
 # for each vault. All vaults are same size.
 mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size
 else:
 # Connect the controllers to the membus
-mem_ctrls[i].port = xbar.master
+mem_ctrls[i].port = xbar.mem_side_ports

 subsystem.mem_ctrls = mem_ctrls
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 52613c6..9ef4d70 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -151,7 +151,7 @@
 self.l2 = self._l2_type()
 for cpu in self.cpus:
 cpu.connectAllPorts(self.toL2Bus)
-self.toL2Bus.master = self.l2.cpu_side
+self.toL2Bus.mem_side_ports = self.l2.cpu_side

 def addPMUs(self, ints, events=[]):
 """
@@ -181,7 +181,7 @@

 def connectMemSide(self, bus):
 try:
-self.l2.mem_side = bus.slave
+self.l2.mem_side = bus.cpu_side_ports
 except AttributeError:
 for cpu in self.cpus:
 cpu.connectAllPorts(bus)
@@ -223,8 +223,9 @@
 ])

 gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
-gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,  
gem5=system.iobus.slave)

-gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
+gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm,
+gem5=system.iobus.cpu_side_ports)
+gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.mem_side_ports)
 gic_g2t.addr_ranges = gic.get_addr_ranges()
 gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 gic.amba_s = gic_t2a.amba
@@ -255,7 +256,7 @@
 self.cpus = [ cpu ]

 a2t = AmbaToTlmBridge64(amba=cpu.amba)
-t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
+t2g = TlmToGem5Bridge64(tlm=a2t.tlm,  
gem5=system.membus.cpu_side_ports)

 system.gic_hub.a2t = a2t
 system.gic_hub.t2g = t2g

@@ -330,21 +331,21 @@
 self.realview.attachPciDevice(dev, self.iobus)

 def connect(self):
-self.iobridge.master = self.iobus.slave
-self.iobridge.slave = self.membus.master
+self.iobridge.mem_side_port = self.iobus.cpu_side_ports
+self.iobridge.cpu_side_port = self.membus.mem_side_ports

 if self._caches:
-self.iocache.mem_side = self.membus.slave
-self.iocache.cpu_side = self.iobus.master
+self.iocache.mem_side = self.membus.cpu_side_ports
+self.iocache.cpu_side = self.iobus.mem_side_ports
 else:
-self.dmabridge.master = self.membus.slave
-self.dmabridge.slave = self.iobus.master
+self.dmabridge.mem_side_port = self.membus.cpu_side_ports
+self.dmabridge.cpu_side_port = self.iobus.mem_side_ports

 if hasattr(self.realview.gic, 'cpu_addr'):
 self.gic_cpu_addr = self.realview.gic.cpu_addr
 self.realview.attachOnChipIO(self.membus, self.iobridge)
 self.realview.attachIO(self.iobus)
-self.system_port = self.membus.slave
+self.system_port = self.membus.cpu_side_ports

 def numCpuClusters(self):
 return len(self._clusters)
@@ -377,8 +378,8 @@
 key=lambda c:  
c.clk_domain.clock[0])

 

[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39585 )



Change subject: scons: Remove Python 2.7 compatibility code
..

scons: Remove Python 2.7 compatibility code

Remove the dependency on six and most 'import x from __future__'. A
few instances of imports from the future have been left in place to
ensure that Python 2.7 users still get an error message when invoking
scons.

Change-Id: I366275a6040f0084e91198b5b5c2a648bffbf2d2
Signed-off-by: Andreas Sandberg 
---
M SConstruct
M ext/libelf/SConscript
M ext/systemc/SConscript
M ext/systemc/src/sysc/kernel/SConscript.sc
M site_scons/gem5_scons/__init__.py
M site_scons/site_tools/git.py
M src/SConscript
M src/mem/ruby/SConscript
M src/systemc/tests/SConscript
9 files changed, 5 insertions(+), 26 deletions(-)



diff --git a/SConstruct b/SConstruct
index b5505ff..4cf2f10 100755
--- a/SConstruct
+++ b/SConstruct
@@ -75,8 +75,6 @@
 #
 ###

-from __future__ import print_function
-
 # Global Python includes
 import atexit
 import itertools
diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index 3bf5b30..e2cc847 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -28,8 +28,6 @@
 #
 # Authors: Nathan Binkert

-from __future__ import print_function
-
 import os, subprocess

 Import('main')
diff --git a/ext/systemc/SConscript b/ext/systemc/SConscript
index cb0c61d..0b6fb0c 100644
--- a/ext/systemc/SConscript
+++ b/ext/systemc/SConscript
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 import os
 from m5.util.terminal import get_termcap

diff --git a/ext/systemc/src/sysc/kernel/SConscript.sc  
b/ext/systemc/src/sysc/kernel/SConscript.sc

index ac79c2f..0e21f74 100644
--- a/ext/systemc/src/sysc/kernel/SConscript.sc
+++ b/ext/systemc/src/sysc/kernel/SConscript.sc
@@ -23,8 +23,6 @@
 # Authors: Christian Menard
 #  Matthias Jung

-from __future__ import print_function
-
 Import('systemc', 'SystemCSource')

 SystemCSource(
diff --git a/site_scons/gem5_scons/__init__.py  
b/site_scons/gem5_scons/__init__.py

index 4208cf1..708002f 100644
--- a/site_scons/gem5_scons/__init__.py
+++ b/site_scons/gem5_scons/__init__.py
@@ -38,8 +38,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import os
 import sys
 import textwrap
diff --git a/site_scons/site_tools/git.py b/site_scons/site_tools/git.py
index 87738b8..a77cffb 100644
--- a/site_scons/site_tools/git.py
+++ b/site_scons/site_tools/git.py
@@ -38,13 +38,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
 import os
 import sys

 import gem5_scons.util
 from m5.util import readCommand
-from six.moves import input

 git_style_message = """
 You're missing the gem5 style or commit message hook. These hooks help
diff --git a/src/SConscript b/src/SConscript
index b55f485..dc57260 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -37,8 +37,6 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import print_function
-
 import array
 import bisect
 import distutils.spawn
@@ -46,7 +44,6 @@
 import imp
 import os
 import re
-import six
 import sys
 import zlib

@@ -144,8 +141,7 @@
 super(SourceMeta, cls).__init__(name, bases, dict)
 cls.all = SourceList()

-@six.add_metaclass(SourceMeta)
-class SourceFile(object):
+class SourceFile(object, metaclass=SourceMeta):
 '''Base object that encapsulates the notion of a source file.
 This includes, the source node, target node, various manipulations
 of those.  A source file also specifies a set of tags which
@@ -157,14 +153,14 @@
 def __init__(self, source, tags=None, add_tags=None, append=None):
 if tags is None:
 tags='gem5 lib'
-if isinstance(tags, six.string_types):
+if isinstance(tags, str):
 tags = set([tags])
 if not isinstance(tags, set):
 tags = set(tags)
 self.tags = tags

 if add_tags:
-if isinstance(add_tags, six.string_types):
+if isinstance(add_tags, str):
 add_tags = set([add_tags])
 if not isinstance(add_tags, set):
 add_tags = set(add_tags)
@@ -266,7 +262,7 @@
 cpp_code(symbol_declaration + ' = {')
 cpp_code.indent()
 step = 16
-for i in six.moves.range(0, len(data), step):
+for i in range(0, len(data), step):
 x = array.array('B', data[i:i+step])
 cpp_code(''.join('%d,'

[gem5-dev] Change in gem5/gem5[develop]: cpu: Don't use deprecated port names

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39583 )



Change subject: cpu: Don't use deprecated port names
..

cpu: Don't use deprecated port names

The BaseCPU has a couple of helper methods that wire up ports using
the deprecated port names. Fix that.

Change-Id: I68452eeef921347e8773d50efd210d2c6844fd90
Signed-off-by: Andreas Sandberg 
---
M src/cpu/BaseCPU.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 025e985..d981570 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -192,13 +192,13 @@

 def connectCachedPorts(self, bus):
 for p in self._cached_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)

 def connectUncachedPorts(self, bus):
 for p in self._uncached_interrupt_response_ports:
-exec('self.%s = bus.master' % p)
+exec('self.%s = bus.mem_side_ports' % p)
 for p in self._uncached_interrupt_request_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)

 def connectAllPorts(self, cached_bus, uncached_bus = None):
 self.connectCachedPorts(cached_bus)

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I68452eeef921347e8773d50efd210d2c6844fd90
Gerrit-Change-Number: 39583
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )



Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..

arch-arm, dev-arm: Remove Python 2 compatibility code

Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
 # root instead of appended.

 def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
 node.append(FdtPropertyStrings("device_type", ["memory"]))
 node.append(FdtPropertyWords("reg",
 state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@

 def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
 node.append(FdtPropertyWords("reg",
 state.addrCells(pio_addr) +
 state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
 idreg = Param.UInt32(0x, "ID Register, SYS_ID")

 def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
 node.appendCompatible("arm,vexpress-sysreg")
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@

 def generateDeviceTree(self, state):
 phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
 node.appendCompatible("arm,vexpress-osc")
 node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
  [0x1, int(self.device)]))
@@ -595,7 +595,7 @@
 super(MmioSRAM, self).__init__(**kwargs)

 def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
 node.appendCompatible(["mmio-sram"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
 def generateDeviceTree(self, state):
 reg_addr = self.reg_map.start
 reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
 node.appendCompatible("arm,smmu-v3")
 node.append(FdtPropertyWords("reg",
 state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
 scp = Param.Scp(Parent.any, "System Control Processor")

 def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
 node.appendCompatible(["arm,mhu", "arm,primecell"])
 node.append(FdtPropertyWords("reg",
 state.addrCells(self.pio_addr) +

--
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Gerrit-Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Gerrit-Change-Number: 39580
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[gem5-dev] Change in gem5/gem5[develop]: sim: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39579 )



Change subject: sim: Consistently use ISO prefixes
..

sim: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg 
---
M src/sim/Process.py
M src/sim/syscall_emul.hh
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
 useArchPT = Param.Bool('false', 'maintain an in-memory version of the  
page\

 table in an architecture-specific format')
 kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in  
SE')

-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')

 uid = Param.Int(100, 'user id')
 euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 79cd35a..16fd175 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1824,7 +1824,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1867,7 +1867,7 @@
 const ByteOrder bo = OS::byteOrder;
 switch (resource) {
   case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
 rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
 rlp->rlim_cur = htog(rlp->rlim_cur, bo);
 rlp->rlim_max = htog(rlp->rlim_max, bo);

--
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Gerrit-Change-Number: 39579
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39578 )



Change subject: dev: Consistently use ISO prefixes
..

dev: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a
Signed-off-by: Andreas Sandberg 
---
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
3 files changed, 20 insertions(+), 19 deletions(-)



diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index dd878e2..e5c5562 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -92,10 +92,11 @@
 type = 'EtherSwitch'
 cxx_header = "dev/net/etherswitch.hh"
 dump = Param.EtherDump(NULL, "dump object")
-fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in bits "

-  "per second")
+fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed  
in "

+  "bits per second")
 interface = VectorEtherInt("Ethernet Interface")
-output_buffer_size = Param.MemorySize('1MB', "size of output port  
buffers")

+output_buffer_size = Param.MemorySize('1MiB',
+  "size of output port buffers")
 delay = Param.Latency('0us', "packet transmit delay")
 delay_var = Param.Latency('0ns', "packet transmit delay variability")
 time_to_live = Param.Latency('10ms', "time to live of MAC address  
maping")

@@ -139,8 +140,8 @@
 cxx_header = "dev/net/i8254xGBe.hh"
 hardware_address = Param.EthernetAddr(NextEthernetAddr,
 "Ethernet Hardware Address")
-rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
-tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
+rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
+tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
 rx_desc_cache_size = Param.Int(64,
 "Number of enteries in the rx descriptor cache")
 tx_desc_cache_size = Param.Int(64,
@@ -152,7 +153,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BAR0 = PciMemBar(size='128kB')
+BAR0 = PciMemBar(size='128KiB')
 MaximumLatency = 0x00
 MinimumGrant = 0xff
 InterruptLine = 0x1e
@@ -195,8 +196,8 @@

 rx_delay = Param.Latency('1us', "Receive Delay")
 tx_delay = Param.Latency('1us', "Transmit Delay")
-rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
-tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
+rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
+tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")

 rx_filter = Param.Bool(True, "Enable Receive Filter")
 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
@@ -218,7 +219,7 @@
 SubClassCode = 0x00
 ClassCode = 0x02
 ProgIF = 0x00
-BARs = (PciIoBar(size='256B'), PciMemBar(size='4kB'))
+BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
 MaximumLatency = 0x34
 MinimumGrant = 0xb0
 InterruptLine = 0x1e
@@ -232,12 +233,12 @@
 cxx_header = "dev/net/sinic.hh"

 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+tx_max_copy = Param.MemorySize('16KiB', "tx 

[gem5-dev] Change in gem5/gem5[develop]: python: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39577 )



Change subject: python: Consistently use ISO prefixes
..

python: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/params.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 45082d7..2b52b93 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -692,7 +692,7 @@

 class MemorySize(CheckedInt):
 cxx_type = 'uint64_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 64
 unsigned = True
 def __init__(self, value):
@@ -704,7 +704,7 @@

 class MemorySize32(CheckedInt):
 cxx_type = 'uint32_t'
-ex_str = '512MB'
+ex_str = '512MiB'
 size = 32
 unsigned = True
 def __init__(self, value):
@@ -724,7 +724,7 @@
 else:
 try:
 # Often addresses are referred to with sizes. Ex: A device
-# base address is at "512MB".  Use toMemorySize() to  
convert
+# base address is at "512MiB".  Use toMemorySize() to  
convert
 # these into addresses. If the address is not specified  
with a
 # "size", an exception will occur and numeric translation  
will

 # proceed below.
@@ -1748,7 +1748,7 @@

 class MemoryBandwidth(float,ParamValue):
 cxx_type = 'float'
-ex_str = "1GB/s"
+ex_str = "1GiB/s"
 cmd_line_settable = True

 def __new__(cls, value):

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93
Gerrit-Change-Number: 39577
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39576 )



Change subject: arch-arm, dev-arm: Consistently use ISO prefixes
..

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32
Signed-off-by: Andreas Sandberg 
---
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
7 files changed, 49 insertions(+), 48 deletions(-)



diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index 4c21d52..e1941c3 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -44,9 +44,10 @@
 abstract = True
 cxx_header = "mem/abstract_mem.hh"

-# A default memory size of 128 MB (starting at 0) is used to
+# A default memory size of 128 MiB (starting at 0) is used to
 # simplify the regressions
-range = Param.AddrRange('128MB', "Address range (potentially  
interleaved)")

+range = Param.AddrRange('128MiB',
+"Address range (potentially interleaved)")
 null = Param.Bool(False, "Do not store data, always return zero")

 # All memories are passed to the global physical memory, and
diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 85a6092..4f59498 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -259,7 +259,7 @@
 # an 8x8 configuration.
 class DDR3_1600_8x8(DRAMInterface):
 # size of device in bytes
-device_size = '512MB'
+device_size = '512MiB'

 # 8x8 configuration, 8 devices each with an 8-bit interface
 device_bus_width = 8
@@ -268,7 +268,7 @@
 burst_length = 8

 # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
-device_rowbuffer_size = '1kB'
+device_rowbuffer_size = '1KiB'

 # 8x8 configuration, so 8 devices
 devices_per_rank = 8
@@ -338,7 +338,7 @@
 # [2] High performance AXI-4.0 based interconnect for extensible smart  
memory

 # cubes (E. Azarkhish et. al)
 # Assumed for the HMC model is a 30 nm technology node.
-# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory  
(4
+# The modelled HMC consists of 4 Gbit layers which sum up to 2GiB of  
memory (4

 # layers).
 # Each layer has 16 vaults and each vault consists of 2 banks per layer.
 # In order to be able to use the same controller used for 2D DRAM  
generations

@@ -354,8 +354,8 @@
 # of the HMC
 class HMC_2500_1x32(DDR3_1600_8x8):
 # size of device
-# two banks per device with each bank 4MB [2]
-device_size = '8MB'
+# two banks per device with each bank 4MiB [2]
+device_size = '8MiB'

 # 1x32 configuration, 1 device with 32 TSVs [2]
 device_bus_width = 32
@@ -458,11 +458,11 @@
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
 # in an 16x4 configuration.
-# Total channel capacity is 32GB
-# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
+# Total channel capacity is 32GiB
+# 16 devices/rank * 2 ranks/channel * 1GiB/device = 32GiB/channel
 class DDR4_2400_16x4(DRAMInterface):
 # size of device
-device_size = '1GB'
+device_size = '1GiB'

 # 16x4 configuration, 16 devices each with a 4-bit interface
 device_bus_width = 4
@@ -569,14 +569,14 @@
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
 # in an 8x8 configuration.
-# Total channel capa

[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39575 )



Change subject: arch-arm, dev-arm: Consistently use ISO prefixes
..

arch-arm, dev-arm: Consistently use ISO prefixes

We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I9b47194d26d71c8ebedda6c31a5bac54b600d3bf
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/dev/arm/FlashDevice.py
M src/dev/arm/RealView.py
5 files changed, 49 insertions(+), 49 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index e445590..8674edc 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -53,10 +53,10 @@
 files_root_dir = Param.String("",
 "Host root directory for files handled by Semihosting")

-mem_reserve = Param.MemorySize("32MB",
+mem_reserve = Param.MemorySize("32MiB",
 "Amount of memory to reserve at the start of the address map.  
This "

 "memory won't be used by the heap reported to an application.");
-stack_size = Param.MemorySize("32MB", "Application stack size");
+stack_size = Param.MemorySize("32MiB", "Application stack size");

 time = Param.Time('01/01/2009',
   "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..7f19adb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -648,7 +648,7 @@
 MISCREG_TTBR0, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t0sz;
 currState->isUncacheable = currState->ttbcr.irgn0 == 0;
-if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
+if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GiB
 start_lookup_level = L2;
 } else if (currState->vaddr >= ttbr1_min) {
 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@
 MISCREG_TTBR1, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t1sz;
 currState->isUncacheable = currState->ttbcr.irgn1 == 0;
-// Lower limit >= 3 GB
+// Lower limit >= 3 GiB
 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
 start_lookup_level = L2;
 } else {
@@ -2379,16 +2379,16 @@
 pageSizes // see DDI 0487A D4-1661
 .init(10)
 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
-pageSizes.subname(0, "4K");
-pageSizes.subname(1, "16K");
-pageSizes.subname(2, "64K");
-pageSizes.subname(3, "1M");
-pageSizes.subname(4, "2M");
-pageSizes.subname(5, "16M");
-pageSizes.subname(6, "32M");
-pageSizes.subname(7, "512M");
-pageSizes.subname(8, "1G");
-pageSizes.subname(9, "4TB");
+pageSizes.subname(0, "4KiB");
+pageSizes.subname(1, "16KiB");
+pageSizes.subname(2, "64KiB");
+pageSizes.subname(3, "1MiB");
+pageSizes.subname(4, "2MiB");
+pageSizes.subname(5, "16MiB");
+pageSizes.subname(6, "32MiB");
+pageSizes.subname(7, "512MiB");
+pageSizes.subname(8, "1GiB");
+pageSizes.subname(9, "4TiB");

 requestOrigin
  

[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect prefixes is m5.utils.convert

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39375 )


Change subject: python: Fix incorrect prefixes is m5.utils.convert
..

python: Fix incorrect prefixes is m5.utils.convert

The conversion functions incorrectly assumed that kibibytes are 'kiB'
rather than 'KiB' (correct).

Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39375
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/util/convert.py
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass

Objections:
  Gabe Black: I would prefer this is not merged as is



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index d3088f6..73335e6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -62,7 +62,7 @@
 'Gi': gibi,
 'G': giga,
 'M': mega,
-'ki': kibi,
+'Ki': kibi,
 'k': kilo,
 'Mi': mebi,
 'm': milli,
@@ -84,7 +84,7 @@
 'G' : gibi,
 'Mi': mebi,
 'M' : mebi,
-'ki': kibi,
+'Ki': kibi,
 'k' : kibi,
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39375
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Gerrit-Change-Number: 39375
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim, mem, dev, arch: Consistently use ISO prefixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39475 )



Change subject: sim, mem, dev, arch: Consistently use ISO prefixes
..

sim, mem, dev, arch: Consistently use ISO prefixes

We currently use a the ambiguous JEDEC prefixes (e.g., MB) in a lot of
places instead of the unambiguous ISO/IEC prefixes (e.g., MiB). This
change replaces most the old prefixes with the new ISO/IEC prefixes in
the code base.

Change-Id: I0849b97d75e17fca2c782166185f41dd2cf6b0a5
Signed-off-by: Andreas Sandberg 
---
M src/arch/arm/ArmSemihosting.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
M src/arch/mips/process.cc
M src/arch/x86/pagetable_walker.cc
M src/dev/arm/FlashDevice.py
M src/dev/arm/RealView.py
M src/dev/net/Ethernet.py
M src/dev/pci/CopyEngine.py
M src/dev/x86/Pc.py
M src/gpu-compute/GPU.py
M src/gpu-compute/LdsState.py
M src/learning_gem5/part2/HelloObject.py
M src/learning_gem5/part2/SimpleCache.py
M src/mem/AbstractMemory.py
M src/mem/DRAMInterface.py
M src/mem/NVMInterface.py
M src/mem/SimpleMemory.py
M src/mem/XBar.py
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/tags/Tags.py
M src/python/m5/params.py
M src/sim/Process.py
M src/sim/syscall_emul.hh
24 files changed, 138 insertions(+), 136 deletions(-)



diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index e445590..8674edc 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -53,10 +53,10 @@
 files_root_dir = Param.String("",
 "Host root directory for files handled by Semihosting")

-mem_reserve = Param.MemorySize("32MB",
+mem_reserve = Param.MemorySize("32MiB",
 "Amount of memory to reserve at the start of the address map.  
This "

 "memory won't be used by the heap reported to an application.");
-stack_size = Param.MemorySize("32MB", "Application stack size");
+stack_size = Param.MemorySize("32MiB", "Application stack size");

 time = Param.Time('01/01/2009',
   "System time to use ('Now' for actual time)")
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index e658b02..7f19adb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -648,7 +648,7 @@
 MISCREG_TTBR0, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t0sz;
 currState->isUncacheable = currState->ttbcr.irgn0 == 0;
-if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
+if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GiB
 start_lookup_level = L2;
 } else if (currState->vaddr >= ttbr1_min) {
 DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@
 MISCREG_TTBR1, currState->tc, !currState->isSecure));
 tsz = currState->ttbcr.t1sz;
 currState->isUncacheable = currState->ttbcr.irgn1 == 0;
-// Lower limit >= 3 GB
+// Lower limit >= 3 GiB
 if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
 start_lookup_level = L2;
 } else {
@@ -2379,16 +2379,16 @@
 pageSizes // see DDI 0487A D4-1661
 .init(10)
 .flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
-pageSizes.subname(0, "4K");
-pageSizes.subname(1, "16K");
-pageSizes.subname(2, "64K");
-pageSizes.subname(3, "1M");
-pageSizes.subname(4, "2M");
-pageSizes.subname(5, "16M");
-pageSizes.subname(6, "32M");
-pageSizes.subname(7, "512M");
-pageSizes.subname(8, "1G");
-pageSizes.subname(9, "4TB");
+pageSizes.subname(0, "4KiB");
+pageSizes.subname(1, "16KiB");
+pageSizes.subname(2, "64KiB");
+pageSizes.subname(3, "1MiB");
+pageSizes.subname(4, "2MiB");
+pageSizes.subname(5, "16MiB");
+pageSizes.subname(6, "32MiB");
+pageSizes.subname(7, "512MiB");
+pageSizes.subname(8, "1GiB");
+pageSizes.subname(9, "4TiB");

 requestOrigin
 .init(2,2) // Instruction/Data, requests/completed
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index dbb480e..f4ee552 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -132,7 +132,7 @@
 return (EntryType)(data & 0x3);
 }

-/** Is the page a Supersection (16MB)?*/
+/** Is the page a Supersection (16 MiB)?*/
 bool supersection() const
 {
 return bi

[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39455 )



Change subject: sim: Use the Temperature type in power/thermal models
..

sim: Use the Temperature type in power/thermal models

The thermal models currently work on temperatures in Celsius stored in
plain doubles. Switch to using Temperature instead and internal
processing in Kelvin. There should be no impact on the result since
all thermal processes work on temperature deltas.

Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Signed-off-by: Andreas Sandberg 
---
M src/dev/arm/rv_ctrl.cc
M src/sim/power/mathexpr_powermodel.cc
M src/sim/power/power_model.cc
M src/sim/power/power_model.hh
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
M src/sim/power/thermal_node.hh
9 files changed, 39 insertions(+), 34 deletions(-)



diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc
index 2d80bc2..8e4e6cf 100644
--- a/src/dev/arm/rv_ctrl.cc
+++ b/src/dev/arm/rv_ctrl.cc
@@ -304,7 +304,7 @@
 // Temperature reported in uC
 ThermalModel * tm = system->getThermalModel();
 if (tm) {
-double t = tm->getTemp();
+double t = tm->getTemperature().toCelsius();
 if (t < 0)
 warn("Temperature below zero!\n");
 return fmax(0, t) * 100;
diff --git a/src/sim/power/mathexpr_powermodel.cc  
b/src/sim/power/mathexpr_powermodel.cc

index 4f3f927..c8a6cef 100644
--- a/src/sim/power/mathexpr_powermodel.cc
+++ b/src/sim/power/mathexpr_powermodel.cc
@@ -86,7 +86,7 @@

 // Automatic variables:
 if (name == "temp") {
-return _temp;
+return _temp.toCelsius();
 } else if (name == "voltage") {
 return clocked_object->voltage();
 } else if (name=="clock_period") {
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index 42515ac..74ab548 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2018,2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp.toCelsius());
+pms->setTemperature(p.ambient_temp);
 }

 dynamicPower
@@ -86,7 +86,7 @@
 }

 void
-PowerModel::thermalUpdateCallback(const double & temp)
+PowerModel::thermalUpdateCallback(const Temperature )
 {
 for (auto & pms: states_pm)
 pms->setTemperature(temp);
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e6f5431..8a11895 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, 2018 ARM Limited
+ * Copyright (c) 2016, 2018, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,6 +39,7 @@
 #define __SIM_POWER_POWER_MODEL_HH__

 #include "base/statistics.hh"
+#include "base/temperature.hh"
 #include "enums/PMType.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
@@ -77,7 +78,7 @@
  *
  * @param temp Current temperature of the HW part (Celsius)
  */
-virtual void setTemperature(double temp) { _temp = temp; }
+virtual void setTemperature(Temperature temp) { _temp = temp; }

 void setClockedObject(ClockedObject * clkobj) {
 clocked_object = clkobj;
@@ -86,7 +87,7 @@
   protected:

 /** Current temperature */
-double _temp;
+Temperature _temp;

 /** The clocked object we belong to */
 ClockedObject * clocked_object;
@@ -125,18 +126,18 @@

 virtual void regProbePoints();

-void thermalUpdateCallback(const double & temp);
+void thermalUpdateCallback(const Temperature );

   protected:
 /** Listener class to catch thermal events */
-class ThermalProbeListener : public ProbeListenerArgBase
+class ThermalProbeListener : public ProbeListenerArgBase
 {
   public:
 ThermalProbeListener(PowerModel &_pm, ProbeManager *pm,
   const std::string )
 : ProbeListenerArgBase(pm, name), pm(_pm) {}

-void notify(const double )
+void notify(const Temperature )
 {
 pm.thermalUpdateCallback(temp);
 }
diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index b0868be..2d9076b 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -49,15 +49,15 @@
 #include "sim/sub_system.hh&

[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFreuency and anyToLatency

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )



Change subject: python: Require a unit in anyToFreuency and anyToLatency
..

python: Require a unit in anyToFreuency and anyToLatency

The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.

Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index ce06ea4..12d3aa1 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -203,32 +203,40 @@
 return toMetricFloat(value, 'latency', 's')

 def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""

-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""

-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be  
unambiguous.")


 def toNetworkBandwidth(value):
 return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

index 6d02b51..fcfedc4 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
 self.assertEqual(conv('1kHz'), 1e-3)

 self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')

 def test_anyToFrequency(self):
 conv = convert.anyToFrequency

-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
 self.assertEqual(conv('42kHz'), 42e3)

 self.assertEqual(conv('0.1s'), 10.0)
 self.assertEqual(conv('1ms'), 1000.0)

 self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')

 def test_toNetworkBandwidth(self):
 conv = convert.toNetworkBandwidth

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Gerrit-Change-Number: 39435
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialise params in thermal models

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39221 )


Change subject: sim: Don't serialise params in thermal models
..

sim: Don't serialise params in thermal models

ThermalDomain and ThermalReference shouldn't serialise their params.

Change-Id: Idc4438b68c0db1fe312d37888c901f2ea87b1d60
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39221
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
4 files changed, 4 insertions(+), 81 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index e9f4d3c..a5eb33c 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -46,7 +46,6 @@
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_model.hh"
 #include "sim/probe/probe.hh"
-#include "sim/serialize.hh"
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
@@ -80,18 +79,6 @@
 ppThermalUpdate->notify(node->temp);
 }

-void
-ThermalDomain::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_initTemperature);
-}
-
-void
-ThermalDomain::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_initTemperature);
-}
-

 LinearEquation
 ThermalDomain::getEquation(ThermalNode * tn, unsigned n, double step) const
diff --git a/src/sim/power/thermal_domain.hh  
b/src/sim/power/thermal_domain.hh

index 421f340..9da753e 100644
--- a/src/sim/power/thermal_domain.hh
+++ b/src/sim/power/thermal_domain.hh
@@ -93,9 +93,6 @@
   */
 void setSubSystem(SubSystem * ss);

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
   private:
 double _initTemperature;
 ThermalNode * node;
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 9f970de..a37240b 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -45,7 +45,6 @@
 #include "sim/clocked_object.hh"
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_domain.hh"
-#include "sim/serialize.hh"
 #include "sim/sim_object.hh"

 /**
@@ -56,18 +55,6 @@
 {
 }

-void
-ThermalReference::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_temperature);
-}
-
-void
-ThermalReference::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_temperature);
-}
-
 LinearEquation
 ThermalReference::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const {
@@ -83,18 +70,6 @@
 {
 }

-void
-ThermalResistor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_resistance);
-}
-
-void
-ThermalResistor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_resistance);
-}
-
 LinearEquation
 ThermalResistor::getEquation(ThermalNode * n, unsigned nnodes,
  double step) const
@@ -130,18 +105,6 @@
 {
 }

-void
-ThermalCapacitor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_capacitance);
-}
-
-void
-ThermalCapacitor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_capacitance);
-}
-
 LinearEquation
 ThermalCapacitor::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const
@@ -181,18 +144,6 @@
 }

 void
-ThermalModel::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_step);
-}
-
-void
-ThermalModel::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_step);
-}
-
-void
 ThermalModel::doStep()
 {
 // Calculate new temperatures!
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 295e508..95d0c7a 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -62,9 +62,6 @@
 typedef ThermalResistorParams Params;
 ThermalResistor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 void setNodes(ThermalNode * n1, ThermalNode * n2) {
 node1 = n1;
 node2 = n2;
@@ -75,7 +72,7 @@

   private:
 /* Resistance value in K/W */
-double _resistance;
+const double _resistance;
 /* Nodes connected to the resistor */
 ThermalNode * node1, * node2;
 };
@@ -91,9 +88,6 @@
 typedef ThermalCapacitorParams Params;
 ThermalCapacitor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 LinearEquation getEquation(ThermalNode * tn, unsigned n,
double step) con

[gem5-dev] Change in gem5/gem5[develop]: sim: Thermal model style fixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39220 )


Change subject: sim: Thermal model style fixes
..

sim: Thermal model style fixes

Fix various style issues in the thermal model implementation.

Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39220
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
2 files changed, 23 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 408642c..9f970de 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -39,6 +39,7 @@

 #include "base/statistics.hh"
 #include "params/ThermalCapacitor.hh"
+#include "params/ThermalModel.hh"
 #include "params/ThermalReference.hh"
 #include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
@@ -253,24 +254,37 @@
 schedule(stepEvent, curTick() + SimClock::Int::s * _step);
 }

-void ThermalModel::addDomain(ThermalDomain * d) {
+void
+ThermalModel::addDomain(ThermalDomain * d)
+{
 domains.push_back(d);
 entities.push_back(d);
 }
-void ThermalModel::addReference(ThermalReference * r) {
+
+void
+ThermalModel::addReference(ThermalReference * r)
+{
 references.push_back(r);
 entities.push_back(r);
 }
-void ThermalModel::addCapacitor(ThermalCapacitor * c) {
+
+void
+ThermalModel::addCapacitor(ThermalCapacitor * c)
+{
 capacitors.push_back(c);
 entities.push_back(c);
 }
-void ThermalModel::addResistor(ThermalResistor * r) {
+
+void
+ThermalModel::addResistor(ThermalResistor * r)
+{
 resistors.push_back(r);
 entities.push_back(r);
 }

-double ThermalModel::getTemp() const {
+double
+ThermalModel::getTemp() const
+{
 // Just pick the highest temperature
 double temp = 0;
 for (auto & n : eq_nodes)
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 81c1de8..295e508 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -40,16 +40,16 @@

 #include 

-#include "params/ThermalCapacitor.hh"
-#include "params/ThermalModel.hh"
-#include "params/ThermalReference.hh"
-#include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
 #include "sim/power/thermal_domain.hh"
 #include "sim/power/thermal_entity.hh"
 #include "sim/power/thermal_node.hh"
 #include "sim/sim_object.hh"

+struct ThermalCapacitorParams;
+struct ThermalModelParams;
+struct ThermalReferenceParams;
+struct ThermalResistorParams;

 /**
  * A ThermalResistor is used to model a thermal resistance between two

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Gerrit-Change-Number: 39220
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add Python unit tests for m5.util.convert

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39377 )



Change subject: tests: Add Python unit tests for m5.util.convert
..

tests: Add Python unit tests for m5.util.convert

Change-Id: I80d1aabbe1d87b01b48280972f9418317e648779
Signed-off-by: Andreas Sandberg 
---
A tests/pyunit/__init__.py
A tests/pyunit/util/__init__.py
A tests/pyunit/util/test_convert.py
A tests/run_pyunit.py
4 files changed, 319 insertions(+), 0 deletions(-)



diff --git a/tests/pyunit/__init__.py b/tests/pyunit/__init__.py
new file mode 100644
index 000..8b13789
--- /dev/null
+++ b/tests/pyunit/__init__.py
@@ -0,0 +1 @@
+
diff --git a/tests/pyunit/util/__init__.py b/tests/pyunit/util/__init__.py
new file mode 100644
index 000..8b13789
--- /dev/null
+++ b/tests/pyunit/util/__init__.py
@@ -0,0 +1 @@
+
diff --git a/tests/pyunit/util/test_convert.py  
b/tests/pyunit/util/test_convert.py

new file mode 100644
index 000..6010ab5
--- /dev/null
+++ b/tests/pyunit/util/test_convert.py
@@ -0,0 +1,266 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2021 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import unittest
+
+from m5.util import convert
+
+def _ip(*args):
+return (args[0] << 24) | (args[1] << 16) | (args[2] << 8) | args[3]
+
+class ConvertTestSuite(unittest.TestCase):
+"""Test cases for unit conversion"""
+
+def test_toMetricFloat(self):
+def conv(x):
+return convert.toMetricFloat(x, 'value', 'X')
+
+self.assertEqual(conv('42'),  42e0)
+self.assertEqual(conv('42.0'),  42e0)
+self.assertEqual(conv('42kX'), 42e3)
+self.assertEqual(conv('42.0kX'), 42e3)
+self.assertEqual(conv('42MX'), 42e6)
+self.assertEqual(conv('42GX'), 42e9)
+self.assertEqual(conv('42TX'), 42e12)
+self.assertEqual(conv('42PX'), 42e15)
+self.assertEqual(conv('42EX'), 42e18)
+
+self.assertEqual(conv('42KiX'), 42 * 2**10)
+self.assertEqual(conv('42MiX'), 42 * 2**20)
+self.assertEqual(conv('42GiX'), 42 * 2**30)
+self.assertEqual(conv('42TiX'), 42 * 2**40)
+self.assertEqual(conv('42PiX'), 42 * 2**50)
+self.assertEqual(conv('42EiX'), 42 * 2**60)
+
+self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42KX')
+self.assertRaises(ValueError, conv, '42kiX')
+
+self.assertEqual(convert.toMetricFloat('42'), 42)
+# Prefixes not allowed without a unit
+self.assertRaises(ValueError, convert.toMetricFloat, '42k')
+
+def test_toMetricInteger(self):
+def conv(x):
+return convert.toMetricInteger(x, 'value', 'X')
+
+self.assertEqual(conv('42'),  42 * 10**0)
+self.assertEqual(conv('42kX'), 42 * 10**3)
+self.assertEqual(conv

[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect anyToLatency conversion

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39376 )



Change subject: python: Fix incorrect anyToLatency conversion
..

python: Fix incorrect anyToLatency conversion

The anyToLatency conversion function incorrectly inverted values
without units.

Change-Id: Ife0aa6837bf7d830b9a3f2611c77f6501cfe19ab
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/util/convert.py
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 73335e6..4dab2e6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -156,13 +156,13 @@
 def anyToLatency(value):
 """result is a clock period"""
 try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
+return toLatency(value)
+except ValueError:
 pass

 try:
-return toLatency(value)
-except ValueError:
+return 1 / toFrequency(value)
+except (ValueError, ZeroDivisionError):
 pass

 raise ValueError("cannot convert '%s' to clock period" % value)

--
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Gerrit-Change-Id: Ife0aa6837bf7d830b9a3f2611c77f6501cfe19ab
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect prefixes is m5.utils.convert

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39375 )



Change subject: python: Fix incorrect prefixes is m5.utils.convert
..

python: Fix incorrect prefixes is m5.utils.convert

The conversion functions incorrectly assumed that kibibytes are 'kiB'
rather than 'KiB' (correct).

Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/util/convert.py
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index d3088f6..73335e6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -62,7 +62,7 @@
 'Gi': gibi,
 'G': giga,
 'M': mega,
-'ki': kibi,
+'Ki': kibi,
 'k': kilo,
 'Mi': mebi,
 'm': milli,
@@ -84,7 +84,7 @@
 'G' : gibi,
 'Mi': mebi,
 'M' : mebi,
-'ki': kibi,
+'Ki': kibi,
 'k' : kibi,
 }


--
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Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5
Gerrit-Change-Number: 39375
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: python: Refactor toNum to support a selection of units

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39217 )



Change subject: python: Refactor toNum to support a selection of units
..

python: Refactor toNum to support a selection of units

Add support for matching one of several different units in toNum. The
units parameter can now either be a tuple or a string describing the
supported unit(s). The function now returns a (magnitude, unit) tuple.

Change-Id: I683819722a93ade91a6def2bfa77209c29b4b39e
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/util/convert.py
1 file changed, 36 insertions(+), 12 deletions(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index d3088f6..772fba2 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2005 The Regents of The University of Michigan
 # Copyright (c) 2010 Advanced Micro Devices, Inc.
 # All rights reserved.
@@ -92,34 +104,46 @@
 if not isinstance(value, str):
 raise TypeError("wrong type '%s' should be str" % type(value))

+def _find_suffix(value, suffixes, default=''):
+matches = [ sfx for sfx in suffixes if value.endswith(sfx) ]
+assert len(matches) <= 1
+
+return matches[0] if matches else default

 # memory size configuration stuff
 def toNum(value, target_type, units, prefixes, converter):
 assertStr(value)

 def convert(val):
+return converter(val)
 try:
 return converter(val)
 except ValueError:
 raise ValueError(
 "cannot convert '%s' to %s" % (value, target_type))

-if units and not value.endswith(units):
-units = None
+# Units can be None, the empty string, or an a list/tuple. Convert
+# to a tuple for consistent handling.
 if not units:
-return convert(value)
+units = tuple()
+elif isinstance(units, str):
+units = (units,)
+else:
+units = tuple(units)

-value = value[:-len(units)]
+unit = _find_suffix(value, units)

-prefix = next((p for p in prefixes.keys() if value.endswith(p)), None)
-if not prefix:
-return convert(value)
-value = value[:-len(prefix)]
+# We only allow a prefix if there is a unit
+if unit:
+prefix = _find_suffix(value[:-len(unit)], prefixes)
+scale = prefixes[prefix] if prefix else 1
+else:
+prefix, scale = '', 1

-return convert(value) * prefixes[prefix]
+return convert(value[:len(value) - len(unit) - len(prefix)]) * scale,  
unit


 def toFloat(value, target_type='float', units=None, prefixes=[]):
-return toNum(value, target_type, units, prefixes, float)
+return toNum(value, target_type, units, prefixes, float)[0]

 def toMetricFloat(value, target_type='float', units=None):
 return toFloat(value, target_type, units, metric_prefixes)
@@ -128,8 +152,8 @@
 return toFloat(value, target_type, units, binary_prefixes)

 def toInteger(value, target_type='integer', units=None, prefixes=[]):
-intifier = lambda x: int(x, 0)
-return toNum(value, target_type, units, prefixes, intifier)
+return toNum(value, target_type, units, prefixes,
+ lambda x: int(x, 0))[0]

 def toMetricInteger(value, target_type='integer', units=None):
 return toInteger(value, target_type, units, metric_prefixes)

--
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Gerrit-Change-Number: 39217
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[gem5-dev] Change in gem5/gem5[develop]: base, python: Add a Temperature type and associated param

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39218 )



Change subject: base, python: Add a Temperature type and associated param
..

base, python: Add a Temperature type and associated param

Add a class to represent a temperature. The class stores temperatures
in Kelvin and provides helper methods to convert to/from Celsius. The
corresponding param type automatically converts from Kelvin, Celsius,
and Fahrenheit to the underlying C++ type.

Change-Id: I5783cc4f4fecbea5aba9821dfc71bfa77c3f75a9
Signed-off-by: Andreas Sandberg 
---
M src/base/SConscript
A src/base/temperature.cc
A src/base/temperature.hh
M src/python/m5/params.py
M src/python/m5/util/convert.py
M src/python/pybind11/core.cc
6 files changed, 258 insertions(+), 2 deletions(-)



diff --git a/src/base/SConscript b/src/base/SConscript
index b3d9506..dd699f3 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -71,6 +71,7 @@
 GTest('str.test', 'str.test.cc', 'str.cc')
 Source('time.cc')
 Source('version.cc')
+Source('temperature.cc')
 Source('trace.cc')
 GTest('trie.test', 'trie.test.cc')
 Source('types.cc')
diff --git a/src/base/temperature.cc b/src/base/temperature.cc
new file mode 100644
index 000..d225b26
--- /dev/null
+++ b/src/base/temperature.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "base/temperature.hh"
+
+Temperature
+Temperature::fromKelvin(double _value)
+{
+return Temperature(_value);
+}
+
+Temperature
+Temperature::fromCelsius(double _value)
+{
+return Temperature(_value - 273.15);
+}
+
+std::ostream&
+operator<<(std::ostream , const Temperature )
+{
+out << temp.value << "K";
+return out;
+}
diff --git a/src/base/temperature.hh b/src/base/temperature.hh
new file mode 100644
index 000..f36b1e1
--- /dev/null
+++ b/src/base/temperature.hh
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, 

[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialise params in thermal models

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39221 )



Change subject: sim: Don't serialise params in thermal models
..

sim: Don't serialise params in thermal models

ThermalDomain and ThermalReference shouldn't serialise their params.

Change-Id: Idc4438b68c0db1fe312d37888c901f2ea87b1d60
Signed-off-by: Andreas Sandberg 
---
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_domain.hh
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
4 files changed, 3 insertions(+), 80 deletions(-)



diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index a2276c5..b0868be 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -46,7 +46,6 @@
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_model.hh"
 #include "sim/probe/probe.hh"
-#include "sim/serialize.hh"
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
@@ -80,18 +79,6 @@
 ppThermalUpdate->notify(node->temp);
 }

-void
-ThermalDomain::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_initTemperature);
-}
-
-void
-ThermalDomain::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_initTemperature);
-}
-

 LinearEquation
 ThermalDomain::getEquation(ThermalNode * tn, unsigned n, double step) const
diff --git a/src/sim/power/thermal_domain.hh  
b/src/sim/power/thermal_domain.hh

index 421f340..9da753e 100644
--- a/src/sim/power/thermal_domain.hh
+++ b/src/sim/power/thermal_domain.hh
@@ -93,9 +93,6 @@
   */
 void setSubSystem(SubSystem * ss);

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
   private:
 double _initTemperature;
 ThermalNode * node;
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 306a4fa..c57e284 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -45,7 +45,6 @@
 #include "sim/clocked_object.hh"
 #include "sim/linear_solver.hh"
 #include "sim/power/thermal_domain.hh"
-#include "sim/serialize.hh"
 #include "sim/sim_object.hh"

 /**
@@ -56,18 +55,6 @@
 {
 }

-void
-ThermalReference::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_temperature);
-}
-
-void
-ThermalReference::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_temperature);
-}
-
 LinearEquation
 ThermalReference::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const {
@@ -83,18 +70,6 @@
 {
 }

-void
-ThermalResistor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_resistance);
-}
-
-void
-ThermalResistor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_resistance);
-}
-
 LinearEquation
 ThermalResistor::getEquation(ThermalNode * n, unsigned nnodes,
  double step) const
@@ -130,18 +105,6 @@
 {
 }

-void
-ThermalCapacitor::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_capacitance);
-}
-
-void
-ThermalCapacitor::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_capacitance);
-}
-
 LinearEquation
 ThermalCapacitor::getEquation(ThermalNode * n, unsigned nnodes,
   double step) const
@@ -181,18 +144,6 @@
 }

 void
-ThermalModel::serialize(CheckpointOut ) const
-{
-SERIALIZE_SCALAR(_step);
-}
-
-void
-ThermalModel::unserialize(CheckpointIn )
-{
-UNSERIALIZE_SCALAR(_step);
-}
-
-void
 ThermalModel::doStep()
 {
 // Calculate new temperatures!
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 295e508..3d9b36d 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -62,9 +62,6 @@
 typedef ThermalResistorParams Params;
 ThermalResistor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 void setNodes(ThermalNode * n1, ThermalNode * n2) {
 node1 = n1;
 node2 = n2;
@@ -91,9 +88,6 @@
 typedef ThermalCapacitorParams Params;
 ThermalCapacitor(const Params );

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 LinearEquation getEquation(ThermalNode * tn, unsigned n,
double step) const override;

@@ -104,7 +98,7 @@

   private:
 /* Capacitance value in J/K */
-double _capacitance;
+const double _capacitance;
 /* Nodes connected to the resistor */
 ThermalNode * node1, * node2;
 };
@@ -128,11 +122,8 @@
 LinearEquation getEquation(ThermalNode * tn, unsigned n,
double step) const override;

-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-
 /* Fixed temperature value in centigrate de

[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature param type

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39219 )



Change subject: sim: Use the Temperature param type
..

sim: Use the Temperature param type

Add support for passing typed temperatures using the new Temperature
param type.

Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Signed-off-by: Andreas Sandberg 
---
M src/sim/power/PowerModel.py
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/power_model.cc
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_model.cc
6 files changed, 11 insertions(+), 11 deletions(-)



diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py
index 2047c64..cfbd8cb 100644
--- a/src/sim/power/PowerModel.py
+++ b/src/sim/power/PowerModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2018 ARM Limited
+# Copyright (c) 2016-2018, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -63,4 +63,4 @@
 pm_type = Param.PMType("All", "Type of power model")

 # Ambient temperature to be used when no thermal model is present
-ambient_temp = Param.Float(25.0, "Ambient temperature")
+ambient_temp = Param.Temperature("25.0C", "Ambient temperature")
diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py
index 3fd5cad..57c53b2 100644
--- a/src/sim/power/ThermalDomain.py
+++ b/src/sim/power/ThermalDomain.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -46,4 +46,4 @@
 ]

 # Static temperature which may change over time
-initial_temperature = Param.Float(25.0, "Initial temperature")
+initial_temperature = Param.Temperature("25.0C", "Initial temperature")
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index 2894dd8..90710e1 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@
 ]

 # Static temperature which may change over time
-temperature = Param.Float(25.0, "Operational temperature in Celsius")
+temperature = Param.Temperature("25.0C", "Operational temperature")


 # Represents a thermal capacitor
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index fbc67d3..42515ac 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -66,7 +66,7 @@
 // The temperature passed here will be overwritten, if there is
 // a thermal model present
 for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp);
+pms->setTemperature(p.ambient_temp.toCelsius());
 }

 dynamicPower
diff --git a/src/sim/power/thermal_domain.cc  
b/src/sim/power/thermal_domain.cc

index e9f4d3c..a2276c5 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,7 +50,7 @@
 #include "sim/sub_system.hh"

 ThermalDomain::ThermalDomain(const Params )
-: SimObject(p), _initTemperature(p.initial_temperature),
+: SimObject(p), _initTemperature(p.initial_temperature.toCelsius()),
 node(NULL), subsystem(NULL),
 ADD_STAT(currentTemp, "Temperature in centigrade degrees")
 {
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 408642c..ce2abe3 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -51,7 +51,7 @@
  * ThermalReference
  */
 ThermalReference::ThermalReference(const Params )
-: SimObject(p), _temperature(p.temperature), node(NULL)
+: SimObject(p), _temperature(p.temperature.toCelsius()), node(NULL)
 {
 }


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Gerrit-Change-Number: 39219
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Thermal model style fixes

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39220 )



Change subject: sim: Thermal model style fixes
..

sim: Thermal model style fixes

Fix various style issues in the thermal model implementation.

Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Signed-off-by: Andreas Sandberg 
---
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
2 files changed, 23 insertions(+), 9 deletions(-)



diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index ce2abe3..306a4fa 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -39,6 +39,7 @@

 #include "base/statistics.hh"
 #include "params/ThermalCapacitor.hh"
+#include "params/ThermalModel.hh"
 #include "params/ThermalReference.hh"
 #include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
@@ -253,24 +254,37 @@
 schedule(stepEvent, curTick() + SimClock::Int::s * _step);
 }

-void ThermalModel::addDomain(ThermalDomain * d) {
+void
+ThermalModel::addDomain(ThermalDomain * d)
+{
 domains.push_back(d);
 entities.push_back(d);
 }
-void ThermalModel::addReference(ThermalReference * r) {
+
+void
+ThermalModel::addReference(ThermalReference * r)
+{
 references.push_back(r);
 entities.push_back(r);
 }
-void ThermalModel::addCapacitor(ThermalCapacitor * c) {
+
+void
+ThermalModel::addCapacitor(ThermalCapacitor * c)
+{
 capacitors.push_back(c);
 entities.push_back(c);
 }
-void ThermalModel::addResistor(ThermalResistor * r) {
+
+void
+ThermalModel::addResistor(ThermalResistor * r)
+{
 resistors.push_back(r);
 entities.push_back(r);
 }

-double ThermalModel::getTemp() const {
+double
+ThermalModel::getTemp() const
+{
 // Just pick the highest temperature
 double temp = 0;
 for (auto & n : eq_nodes)
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 81c1de8..295e508 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -40,16 +40,16 @@

 #include 

-#include "params/ThermalCapacitor.hh"
-#include "params/ThermalModel.hh"
-#include "params/ThermalReference.hh"
-#include "params/ThermalResistor.hh"
 #include "sim/clocked_object.hh"
 #include "sim/power/thermal_domain.hh"
 #include "sim/power/thermal_entity.hh"
 #include "sim/power/thermal_node.hh"
 #include "sim/sim_object.hh"

+struct ThermalCapacitorParams;
+struct ThermalModelParams;
+struct ThermalReferenceParams;
+struct ThermalResistorParams;

 /**
  * A ThermalResistor is used to model a thermal resistance between two

--
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Gerrit-Change-Number: 39220
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[gem5-dev] Change in gem5/gem5[develop]: misc: Convert MAINTAINERS to YAML

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37035 )


Change subject: misc: Convert MAINTAINERS to YAML
..

misc: Convert MAINTAINERS to YAML

Convert MAINTAINERS to YAML and rename it to MAINTAINERS.yaml.

Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37035
Reviewed-by: Hoa Nguyen 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D MAINTAINERS
A MAINTAINERS.yaml
2 files changed, 303 insertions(+), 147 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/MAINTAINERS b/MAINTAINERS
deleted file mode 100644
index 7ae23fd..000
--- a/MAINTAINERS
+++ /dev/null
@@ -1,147 +0,0 @@
-See CONTRIBUTING.md for details of gem5's contribution process.
-
-This file contains the keywords used in commit messages. Each keyword has  
one
-or more maintainers. At least one (not all) of these maintainers must  
review
-the patch before it can be pushed. These people will automatically be  
emailed

-when you upload the patch to Gerrit (https://gem5-review.googlesource.com).
-These keywords mostly follow the directory structure.
-
-Maintainers have the following responsibilities:
-1. That at least one maintainer of each subsystem reviews all changes to  
that

-   subsystem (they will be automatically tagged and emailed on each new
-   change).
-2. They will complete your reviews in a timely manner (within a few  
business

-   days).
-3. They pledge to uphold gem5's community standards and its code of  
conduct by
-   being polite and professional in their code reviews. See  
CODE-OF-CONDUCT.md.

-
-PMC Members (general maintainers):
-  Andreas Sandberg 
-  Brad Beckmann 
-  David Wood 
-  Gabe Black 
-  Giacomo Travaglini 
-  Jason Lowe-Power  (chair)
-  Matt Sinclair 
-  Tony Gutierrez 
-  Steve Reinhardt 
-
-arch: General architecture-specific components
-  Gabe Black 
-arch-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-arch-gcn3:
-  UNSUPPORTED
-arch-mips:
-  UNSUPPORTED
-arch-power:
-  Boris Shingarov 
-arch-riscv:
-  UNSUPPORTED
-arch-sparc:
-  Gabe Black 
-arch-x86:
-  Gabe Black 
-
-base:
-  Bobby Bruce 
-base-stats:
-  UNSUPPORTED
-
-configs:
-  Jason Lowe-Power 
-
-cpu: General changes to all CPU models (e.g., BaseCPU)
-  Gabe Black 
-  Jason Lowe-Power 
-cpu-kvm:
-  Andreas Sandberg 
-cpu-minor:
-  Zhengrong Wang 
-cpu-o3:
-  UNSUPPORTED
-cpu-simple:
-  Jason Lowe-Power 
-  Gabe Black 
-
-dev:
-  Gabe Black 
-dev-hsa:
-  UNSUPPORTED
-dev-virtio:
-  Andreas Sandberg 
-dev-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-
-doc:
-  Bobby Bruce 
-
-ext: Components external to gem5
-  Bobby Bruce 
-  Jason Lowe-Power 
-ext-testlib:
-  Bobby Bruce 
-  Hoa Nguyen 
-
-fastmodel: Changes relating to ARM Fast Models
-  Gabe Black 
-
-gpu-compute:
-  Matt Poremba 
-
-learning-gem5: The code and configs for the Learning gem5 book
-  Jason Lowe-Power 
-
-mem: General memory system (e.g., XBar, Packet)
-  Nikos Nikoleris 
-mem-cache: Classic caches and coherence
-  Nikos Nikoleris 
-mem-dram:
-  Nikos Nikoleris 
-mem-garnet: Garnet subcomponent of Ruby
-  Srikant Bharadwaj 
-mem-ruby: Ruby structures and protocols
-  Jason Lowe-Power 
-
-misc: Anything outside of the other categories
-  Bobby Bruce 
-  Jason Lowe-Power 
-
-python: Python SimObject wrapping and infrastructure
-  Andreas Sandberg 
-  Jason Lowe-Power 
-
-resources: The gem5-resources repo with auxiliary resources for simulation
-  Bobby Bruce 
-  Jason Lowe-Power 
-
-scons: Build system
-  Gabe Black 
-
-sim: General simulation components
-  Jason Lowe-Power 
-sim-se: Syscall emulation
-  UNSUPPORTED
-
-system-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-
-systemc: Code for the gem5 SystemC implementation and interface
-  Gabe Black 
-
-tests: testing changes
-  Bobby Bruce 
-
-util:
-  Gabe Black 
-util-docker:
-  Bobby Bruce 
-util-m5:
-  Gabe Black 
-
-website: The gem5-website repo which contains the gem5.org site
-  Bobby Bruce 
-  Hoa Nguyen 
diff --git a/MAINTAINERS.yaml b/MAINTAINERS.yaml
new file mode 100644
index 000..8a2bf75
--- /dev/null
+++ b/MAINTAINERS.yaml
@@ -0,0 +1,303 @@
+# See CONTRIBUTING.md for details of gem5's contribution process.
+#
+# This file contains a list of gem5's subsystems and their
+# maintainers. The key used to identifity a subsystem should be used
+# as a tag in commit messages targetting that subsystem. At least one
+# (not all) of these maintainers must review the patch before it can
+# be pushed. These people will automatically be emailed when you
+# upload the patch to Gerrit (https://gem5-review.googlesource.com).
+# These subsystem keys mostly follow the directory structure.
+#
+# Maintainers have the following responsibilities:
+# 1. That at least one maintainer of each

[gem5-dev] Change in gem5/gem5[develop]: util: Add a library to parser MAINTAINERS.yaml

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37036 )



Change subject: util: Add a library to parser MAINTAINERS.yaml
..

util: Add a library to parser MAINTAINERS.yaml

Add a very simple library to parse MAINTAINERS.yaml. There are
currently no tools that use the library, but it can be tested using
`python3 -m "maint.lib.maintainers"` from within the util directory.

Change-Id: Id2edff94451f27e0b601994d198d0647325e4b35
Signed-off-by: Andreas Sandberg 
---
A util/maint/lib/__init__.py
A util/maint/lib/maintainers.py
2 files changed, 128 insertions(+), 0 deletions(-)



diff --git a/util/maint/lib/__init__.py b/util/maint/lib/__init__.py
new file mode 100644
index 000..e5a0d9b
--- /dev/null
+++ b/util/maint/lib/__init__.py
@@ -0,0 +1 @@
+#!/usr/bin/env python3
diff --git a/util/maint/lib/maintainers.py b/util/maint/lib/maintainers.py
new file mode 100644
index 000..cffcee5
--- /dev/null
+++ b/util/maint/lib/maintainers.py
@@ -0,0 +1,127 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2017-2018 Arm Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import email.utils
+import enum
+import os
+from typing import Any, Dict, Iterator, List, Mapping, Optional, TextIO, \
+Tuple, Union
+
+import yaml
+
+class Status(enum.Enum):
+MAINTAINED = enum.auto()
+ORPHANED = enum.auto()
+
+@classmethod
+def from_str(cls, key: str) -> 'Status':
+_status_dict = {
+'maintained': cls.MAINTAINED,
+'orphaned': cls.ORPHANED,
+}
+return _status_dict[key]
+
+def __str__(self) -> str:
+return {
+Status.MAINTAINED: 'maintained',
+Status.ORPHANED: 'orphaned',
+}[self]
+
+class Subsystem(object):
+tag: str
+status: Status
+maintainers: List[Tuple[str, str]] # Name, email
+description: str
+
+def __init__(self, tag: str,
+ maintainers: Optional[Iterator[Tuple[str, str]]],
+ description: str = '',
+ status: Status = Status.ORPHANED):
+self.tag = tag
+self.status = status
+self.maintainers = list(maintainers) if maintainers is not None  
else []

+self.description = description if description is not None else ''
+
+class Maintainers(object):
+DEFAULT_MAINTAINERS = os.path.join(os.path.dirname(__file__),
+   '../../../MAINTAINERS')
+
+_subsystems: Dict[str, Subsystem] # tag -> Subsystem
+
+def __init__(self, path_or_file: Optional[Union[TextIO, str]] = None):
+maintainers = Maintainers._load_maintainers_file(path_or_file)
+self._subsystems = {}
+for tag, maint in maintainers.items():
+self._subsystems[tag] = Maintainers._parse_subsystem(tag,  
maint)

+
+@classmethod
+d

[gem5-dev] Change in gem5/gem5[develop]: misc: Convert MAINTAINERS to YAML

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37035 )



Change subject: misc: Convert MAINTAINERS to YAML
..

misc: Convert MAINTAINERS to YAML

Convert MAINTAINERS to YAML and rename it to MAINTAINERS.yaml.

Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0
Signed-off-by: Andreas Sandberg 
---
D MAINTAINERS
A MAINTAINERS.yaml
2 files changed, 223 insertions(+), 116 deletions(-)



diff --git a/MAINTAINERS b/MAINTAINERS
deleted file mode 100644
index 913daaf..000
--- a/MAINTAINERS
+++ /dev/null
@@ -1,116 +0,0 @@
-See CONTRIBUTING.md for details of gem5's contribution process.
-
-This file contains the keywords used in commit messages. Each keyword has  
one
-or more maintainers. At least one (not all) of these maintainers must  
review
-the patch before it can be pushed. These people will automatically be  
emailed

-when you upload the patch to Gerrit (https://gem5-review.googlesource.com).
-These keywords mostly follow the directory structure.
-
-Individuals on the project management committee are maintainers for all of  
the

-gem5 components (i.e., they can review any patch as the maintainer). These
-individuals are required to review any patches to components without  
explicit

-maintainers.
-
-PMC Members (general maintainers):
-  Ali Saidi 
-  Andreas Sandberg 
-  Brad Beckmann 
-  David Wood 
-  Gabe Black 
-  Giacomo Travaglini 
-  Jason Lowe-Power  (chair)
-  Matt Sinclair 
-  Tony Gutierrez 
-  Steve Reinhardt 
-
-arch: General architecture-specific components
-  Gabe Black 
-arch-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-arch-gcn3:
-  Tony Gutierrez 
-arch-mips:
-arch-power:
-arch-riscv:
-  Alec Roelke 
-arch-sparc:
-  Gabe Black 
-arch-x86:
-  Gabe Black 
-
-base:
-
-configs:
-  Jason Lowe-Power 
-
-cpu: General changes to all CPU models (e.g., BaseCPU)
-cpu-kvm:
-  Andreas Sandberg 
-cpu-minor:
-cpu-o3:
-cpu-simple:
-
-dev:
-dev-hsa:
-  Tony Gutierrez 
-dev-virtio:
-  Andreas Sandberg 
-
-dev-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-
-ext: Components external to gem5
-
-fastmodel: Changes relating to ARM Fast Models
-  Gabe Black 
-
-gpu-compute:
-  Tony Gutierrez 
-  Matt Poremba 
-
-learning-gem5: The code and configs for the Learning gem5 book (see
-   learning.gem5.com)
-  Jason Lowe-Power 
-
-mem: General memory system (e.g., XBar, Packet)
-  Nikos Nikoleris 
-mem-cache: Classic caches and coherence
-  Nikos Nikoleris 
-mem-garnet: Garnet subcomponent of Ruby
-  Tushar Krishna 
-mem-ruby: Ruby structures and protocols
-  Brad Beckmann 
-  Jason Lowe-Power 
-
-misc: Anything outside of the other categories
-
-python: Python SimObject wrapping and infrastructure
-  Andreas Sandberg 
-
-scons: Build system
-  Gabe Black 
-
-sim: General simulation components
-  Jason Lowe-Power 
-sim-se: Syscall emulation
-  Brandon Potter 
-sim-power: Power modeling
-  Andreas Sandberg 
-
-stats: Updates to statistics for regressions
-
-system: System boot code and related components
-system-arm:
-  Andreas Sandberg 
-  Giacomo Travaglini 
-
-systemc: Code for the gem5 SystemC implementation and interface
-  Gabe Black 
-
-tests: testing changes (not stats updates for tests. See stats:)
-  Bobby Bruce 
-
-util:
-  Gabe Black 
diff --git a/MAINTAINERS.yaml b/MAINTAINERS.yaml
new file mode 100644
index 000..dfd3351
--- /dev/null
+++ b/MAINTAINERS.yaml
@@ -0,0 +1,223 @@
+# See CONTRIBUTING.md for details of gem5's contribution process.
+#
+# This file contains a list of gem5's subsystems and their
+# maintainers. The key used to identifity a subsystem should be used
+# as a tag in commit messages targetting that subsystem. At least one
+# (not all) of these maintainers must review the patch before it can
+# be pushed. These people will automatically be emailed when you
+# upload the patch to Gerrit (https://gem5-review.googlesource.com).
+# These subsystem keys mostly follow the directory structure.
+#
+# Individuals on the project management committee are maintainers for all  
of the
+# gem5 components (i.e., they can review any patch as the maintainer).  
These
+# individuals are required to review any patches to components without  
explicit

+# maintainers.
+#
+# Entries have the following format:
+#   key:
+# desc: >-
+#   Optional description of the subsystem.
+# status: maintained
+# maintainers:
+#   - John Doe 
+#   - Jane Doe 
+#
+#
+# The status field should have one of the following values:
+#   - maintained: The component has an active maintainer.
+#   - orphaned: The component is looking for a new owner.
+
+pmc:
+  desc: >-
+List of PMC Members (general maintainers)
+  status: maintained
+  maintainers:
+- Ali Saidi 
+- Andreas Sandberg 
+- Brad Beckmann 
+- David Wood 
+- Gabe Black 
+- Giacomo Travaglini 
+- Jason Lowe-Power  (chair)
+- Matt Si

[gem5-dev] Change in gem5/gem5[develop]: scons: Test if binaries can embed the Python interpreter

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36383 )


Change subject: scons: Test if binaries can embed the Python interpreter
..

scons: Test if binaries can embed the Python interpreter

Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.

Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36383
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 33 insertions(+), 3 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 8e7ec34..a057da3 100755
--- a/SConstruct
+++ b/SConstruct
@@ -575,6 +575,27 @@
 context.Result(ret)
 return ret

+def CheckPythonLib(context):
+context.Message('Checking Python version... ')
+ret = context.TryRun(r"""
+#include 
+
+int
+main(int argc, char **argv) {
+pybind11::scoped_interpreter guard{};
+pybind11::exec(
+"import sys\n"
+"vi = sys.version_info\n"
+"sys.stdout.write('%i.%i.%i' % (vi.major, vi.minor,  
vi.micro));\n");

+return 0;
+}
+""", extension=".cc")
+context.Result(ret[1] if ret[0] == 1 else 0)
+if ret[0] == 0:
+return None
+else:
+return tuple(map(int, ret[1].split(".")))
+
 # Platform-specific configuration.  Note again that we assume that all
 # builds under a given build root run on the same host platform.
 conf = Configure(main,
@@ -582,6 +603,7 @@
  log_file = joinpath(build_root, 'scons_config.log'),
  custom_tests = {
 'CheckMember' : CheckMember,
+'CheckPythonLib' : CheckPythonLib,
 })

 # Check if we should compile a 64 bit binary on Mac OS X/Darwin
@@ -637,9 +659,6 @@
   main['PYTHON_CONFIG'])

 print("Info: Using Python config: %s" % (python_config, ))
-if python_config != 'python3-config':
-warning('python3-config could not be found.\n'
-'Future releases of gem5 will drop support for python2.')

 py_includes = readCommand([python_config, '--includes'],
   exception='').split()
@@ -697,6 +716,17 @@
 marshal_env = main.Clone()
 marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
 marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+py_version = conf.CheckPythonLib()
+if not py_version:
+error("Can't find a working Python installation")
+
+# Found a working Python installation. Check if it meets minimum
+# requirements.
+if py_version[0] < 3 or \
+   (py_version[0] == 3 and py_version[1] < 6):
+error('Python version too old. Version 3.6 or newer is required.')
+elif py_version[0] > 3:
+warning('Python version too new. Python 3 expected.')

 # On Solaris you need to use libsocket for socket ops
 if not  
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Gerrit-Change-Number: 36383
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg 
Gerrit-Assignee: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby R. Bruce 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Don't check for Python 2

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36535 )


Change subject: scons: Don't check for Python 2
..

scons: Don't check for Python 2

The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.

Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36535
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index a057da3..5033344 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,7 @@
 ('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler  
flags', ''),

 ('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
 ('PYTHON_CONFIG', 'Python config binary to use',
-  
[ 'python3-config', 'python-config', 'python2.7-config', 'python2-config']

+ [ 'python3-config', 'python-config']
 ),
 ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
 ('BATCH', 'Use batch pool for build and tests', False),

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Gerrit-Change-Number: 36535
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Assignee: Jason Lowe-Power 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Don't check for Python 2

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36535 )



Change subject: scons: Don't check for Python 2
..

scons: Don't check for Python 2

The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.

Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/SConstruct b/SConstruct
index 3b157f0..8005a98 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,7 @@
 ('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler  
flags', ''),

 ('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
 ('PYTHON_CONFIG', 'Python config binary to use',
-  
[ 'python3-config', 'python-config', 'python2.7-config', 'python2-config']

+ [ 'python3-config', 'python-config']
 ),
 ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
 ('BATCH', 'Use batch pool for build and tests', False),

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Gerrit-Change-Number: 36535
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Test if binaries can embed the Python interpreter

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/36383 )



Change subject: scons: Test if binaries can embed the Python interpreter
..

scons: Test if binaries can embed the Python interpreter

Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.

Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 37 insertions(+), 3 deletions(-)



diff --git a/SConstruct b/SConstruct
index 8e7ec34..16558d2 100755
--- a/SConstruct
+++ b/SConstruct
@@ -575,6 +575,27 @@
 context.Result(ret)
 return ret

+def CheckPythonLib(context):
+context.Message('Checking for Python...')
+ret = context.TryRun(r"""
+#include 
+
+int
+main(int argc, char **argv) {
+pybind11::scoped_interpreter guard{};
+pybind11::exec(
+"import sys\n"
+"vi = sys.version_info\n"
+"sys.stdout.write('%i.%i.%i' % (vi.major, vi.minor,  
vi.micro));\n");

+return 0;
+}
+""", extension=".cc")
+context.Result(ret[1] if ret[0] == 1 else 0)
+if ret[0] == 0:
+return None
+else:
+return tuple((int(x) for x in ret[1].split(".")))
+
 # Platform-specific configuration.  Note again that we assume that all
 # builds under a given build root run on the same host platform.
 conf = Configure(main,
@@ -582,6 +603,7 @@
  log_file = joinpath(build_root, 'scons_config.log'),
  custom_tests = {
 'CheckMember' : CheckMember,
+'CheckPythonLib' : CheckPythonLib,
 })

 # Check if we should compile a 64 bit binary on Mac OS X/Darwin
@@ -637,9 +659,6 @@
   main['PYTHON_CONFIG'])

 print("Info: Using Python config: %s" % (python_config, ))
-if python_config != 'python3-config':
-warning('python3-config could not be found.\n'
-'Future releases of gem5 will drop support for python2.')

 py_includes = readCommand([python_config, '--includes'],
   exception='').split()
@@ -697,6 +716,21 @@
 marshal_env = main.Clone()
 marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
 marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+py_version = conf.CheckPythonLib()
+if not py_version:
+error("Can't find a working Python installation")
+else:
+# Found a working Python installation. Check if it meets minimum
+# requirements.
+if py_version[0] < 2 or \
+   (py_version[0] == 2 and py_version[1] < 7) or \
+   (py_version[0] == 3 and py_version[1] < 6):
+error('Python version too old. '
+  'At least version Python 2.7 or 3.6 is required.')
+elif py_version[0] == 2:
+warning('Future releases of gem5 will drop support for Python 2.7')
+elif py_version[0] > 3:
+warning('Python version too new. Python 3.x expected.')

 # On Solaris you need to use libsocket for socket ops
 if not  
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):


--
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Gerrit-Change-Number: 36383
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: stats: Output new-world stats before legacy stats

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35617 )


Change subject: stats: Output new-world stats before legacy stats
..

stats: Output new-world stats before legacy stats

Now that global stats have been converted to new-style stats, it's
desirable to output them before legacy stats. This ensures that global
statistics (e.g., host_seconds) show up first in the stat file.

Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35617
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/stats/__init__.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/stats/__init__.py  
b/src/python/m5/stats/__init__.py

index 6c4a42c..1fc6c9c 100644
--- a/src/python/m5/stats/__init__.py
+++ b/src/python/m5/stats/__init__.py
@@ -345,13 +345,13 @@
 for p in reversed(root.path_list()):
 visitor.endGroup()
 else:
+# New stats starting from root.
+dump_group(Root.getInstance())
+
 # Legacy stats
 for stat in stats_list:
 stat.visit(visitor)

-# New stats starting from root.
-dump_group(Root.getInstance())
-
 lastDump = 0
 # List[SimObject].
 global_dump_roots = []

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260
Gerrit-Change-Number: 35617
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim, stats: Move global stats to Root

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35616 )


Change subject: sim, stats: Move global stats to Root
..

sim, stats: Move global stats to Root

Global stats are currently exposed using the legacy stat system (i.e.,
without a parent group). This change moves global stats from
stat_control.cc to a group that gets exported from the Root object.

The implementation adds the Root::Stats class which has a single
global instance. This instance is exposed to the rest of the simulator
using the global rootStats symbol. The intention is that objects that
need global statistics in formulas access them through the rootStats
object.

The global names simSeconds, simTicks, simFreq, and hostSeconds are
now references to their respective members in the rootStats object.

Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35616
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/SConscript
M src/sim/root.cc
M src/sim/root.hh
M src/sim/stat_control.cc
M src/sim/stat_control.hh
A src/sim/stats.cc
M src/sim/stats.hh
7 files changed, 164 insertions(+), 105 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/SConscript b/src/sim/SConscript
index 6bda828..78d9bf5 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -81,6 +81,7 @@
 Source('mathexpr.cc')
 Source('power_state.cc')
 Source('power_domain.cc')
+Source('stats.cc')

 GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
 GTest('guest_abi.test', 'guest_abi.test.cc')
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 5a17442..e1c6a7b 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2011 Advanced Micro Devices, Inc.
  * All rights reserved.
@@ -27,6 +39,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#include "base/hostinfo.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -36,6 +49,56 @@
 #include "sim/root.hh"

 Root *Root::_root = NULL;
+Root::Stats Root::Stats::instance;
+Root::Stats  = Root::Stats::instance;
+
+Root::Stats::Stats()
+: Stats::Group(nullptr),
+simSeconds(this, "sim_seconds", "Number of seconds simulated"),
+simTicks(this, "sim_ticks", "Number of ticks simulated"),
+finalTick(this, "final_tick",
+  "Number of ticks from beginning of simulation "
+  "(restored from checkpoints and never reset)"),
+simFreq(this, "sim_freq", "Frequency of simulated ticks"),
+hostSeconds(this, "host_seconds", "Real time elapsed on the host"),
+hostTickRate(this, "host_tick_rate", "Simulator tick rate (ticks/s)"),
+hostMemory(this, "host_mem_usage", "Number of bytes of host memory  
used"),

+
+statTime(true),
+startTick(0)
+{
+simFreq.scalar(SimClock::Frequency);
+simTicks.functor([this]() { return curTick() - startTick; });
+finalTick.functor(curTick);
+
+hostMemory
+.functor(memUsage)
+.prereq(hostMemory)
+;
+
+hostSeconds
+.functor([this]() {
+Time now;
+now.setTimer();
+return now - statTime;
+})
+.precision(2)
+;
+
+hostTickRate.precision(0);
+
+simSeconds = simTicks / simFreq;
+hostTickRate = simTicks / hostSeconds;
+}
+
+void
+Root::Stats::resetStats()
+{
+statTime.setTimer();
+startTick = curTick();
+
+Stats::Group::resetStats();
+}

 /*
  * This function is called periodically by an event in M5 and ensures that
@@ -112,6 +175,12 @@
 lastTime.setTimer();

 simQuantum = p->sim_quantum;
+
+// Some of the statistics are global and need to be accessed by
+// stat formulas. The most convenient way to implement that is by
+// having a single glob

[gem5-dev] Change in gem5/gem5[develop]: stats: Make Stats::Group::mergeStatGroup public

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35615 )


Change subject: stats: Make Stats::Group::mergeStatGroup public
..

stats: Make Stats::Group::mergeStatGroup public

The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.

This change adds some error checking to mergeStatGroup and marks it as
a public method.

Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35615
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/stats/group.cc
M src/base/stats/group.hh
2 files changed, 17 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a76ad4f..f1eda1d 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -47,7 +47,7 @@
 namespace Stats {

 Group::Group(Group *parent, const char *name)
-: mergedParent(name ? nullptr : parent)
+: mergedParent(nullptr)
 {
 if (parent && name) {
 parent->addStatGroup(name, this);
@@ -152,7 +152,22 @@
 void
 Group::mergeStatGroup(Group *block)
 {
+panic_if(!block, "No stat block provided");
+panic_if(block->mergedParent,
+ "Stat group already merged into another group");
+panic_if(block == this, "Stat group can't merge with itself");
+
+// Track the new stat group
 mergedStatGroups.push_back(block);
+
+// We might not have seen stats that were associated with the
+// child group before it was merged, so add them here.
+for (auto  : block->stats)
+addStat(s);
+
+// Setup the parent pointer so the child know that it needs to
+// register new stats with the parent.
+block->mergedParent = this;
 }

 const std::map &
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 985bf61..ef223bc 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -194,7 +194,6 @@
  */
 const Info * resolveStat(std::string name) const;

-  private:
 /**
  * Merge the contents (stats & children) of a block to this block.
  *
@@ -205,7 +204,7 @@

   private:
 /** Parent pointer if merged into parent */
-Group *const mergedParent;
+Group *mergedParent;

 std::map statGroups;
 std::vector mergedStatGroups;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Gerrit-Change-Number: 35615
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stats: Output new-world stats before legacy stats

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35617 )



Change subject: stats: Output new-world stats before legacy stats
..

stats: Output new-world stats before legacy stats

Now that global stats have been converted to new-style stats, it's
desirable to output them before legacy stats. This ensures that global
statistics (e.g., host_seconds) show up first in the stat file.

Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/stats/__init__.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/python/m5/stats/__init__.py  
b/src/python/m5/stats/__init__.py

index 6c4a42c..1fc6c9c 100644
--- a/src/python/m5/stats/__init__.py
+++ b/src/python/m5/stats/__init__.py
@@ -345,13 +345,13 @@
 for p in reversed(root.path_list()):
 visitor.endGroup()
 else:
+# New stats starting from root.
+dump_group(Root.getInstance())
+
 # Legacy stats
 for stat in stats_list:
 stat.visit(visitor)

-# New stats starting from root.
-dump_group(Root.getInstance())
-
 lastDump = 0
 # List[SimObject].
 global_dump_roots = []

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260
Gerrit-Change-Number: 35617
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim, stats: Move global stats to Root

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35616 )



Change subject: sim, stats: Move global stats to Root
..

sim, stats: Move global stats to Root

Global stats are currently exposed using the legacy stat system (i.e.,
without a parent group). This change moves global stats from
stat_control.cc to a group that gets exported from the Root object.

The implementation adds the Root::Stats class which has a single
global instance. This instance is exposed to the rest of the simulator
using the global rootStats symbol. The intention is that objects that
need global statistics in formulas access them through the rootStats
object.

The global names simSeconds, simTicks, simFreq, and hostSeconds are
now references to their respective members in the rootStats object.

Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e
Signed-off-by: Andreas Sandberg 
---
M src/sim/SConscript
M src/sim/root.cc
M src/sim/root.hh
M src/sim/stat_control.cc
M src/sim/stat_control.hh
A src/sim/stats.cc
M src/sim/stats.hh
7 files changed, 162 insertions(+), 105 deletions(-)



diff --git a/src/sim/SConscript b/src/sim/SConscript
index 6bda828..78d9bf5 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -81,6 +81,7 @@
 Source('mathexpr.cc')
 Source('power_state.cc')
 Source('power_domain.cc')
+Source('stats.cc')

 GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
 GTest('guest_abi.test', 'guest_abi.test.cc')
diff --git a/src/sim/root.cc b/src/sim/root.cc
index 5a17442..b41ab2d 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2011 Advanced Micro Devices, Inc.
  * All rights reserved.
@@ -27,6 +39,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#include "base/hostinfo.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -36,6 +49,54 @@
 #include "sim/root.hh"

 Root *Root::_root = NULL;
+Root::Stats Root::Stats::instance;
+Root::Stats  = Root::Stats::instance;
+
+Root::Stats::Stats()
+: Stats::Group(nullptr),
+simSeconds(this, "sim_seconds", "Number of seconds simulated"),
+simTicks(this, "sim_ticks", "Number of ticks simulated"),
+finalTick(this, "final_tick",
+  "Number of ticks from beginning of simulation "
+  "(restored from checkpoints and never reset)"),
+simFreq(this, "sim_freq", "Frequency of simulated ticks"),
+hostSeconds(this, "host_seconds", "Real time elapsed on the host"),
+hostTickRate(this, "host_tick_rate", "Simulator tick rate (ticks/s)"),
+hostMemory(this, "host_mem_usage", "Number of bytes of host memory  
used"),

+
+statTime(true),
+startTick(0)
+{
+simFreq.scalar(SimClock::Frequency);
+simTicks.functor([this]() { return curTick() - startTick; });
+finalTick.functor(curTick);
+
+hostMemory
+.functor(memUsage)
+.prereq(hostMemory)
+;
+
+hostSeconds
+.functor([this]() {
+Time now;
+now.setTimer();
+return now - statTime;
+})
+.precision(2)
+;
+
+hostTickRate.precision(0);
+
+simSeconds = simTicks / simFreq;
+hostTickRate = simTicks / hostSeconds;
+}
+
+void
+Root::Stats::resetStats()
+{
+statTime.setTimer();
+startTick = curTick();
+}

 /*
  * This function is called periodically by an event in M5 and ensures that
@@ -112,6 +173,12 @@
 lastTime.setTimer();

 simQuantum = p->sim_quantum;
+
+// Some of the statistics are global and need to be accessed by
+// stat formulas. The most convenient way to implement that is by
+// having a single global stat group for global stats. Merge that
+// group into the root object here.
+mergeStatGroup(::Stats::instance);
 }

 void
diff --git a/src/sim/root.hh b/src/sim/root.hh
index 0638559..a88673a 100644
--- a/src/sim/root.hh
+++ b/src/sim/root.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (

[gem5-dev] Change in gem5/gem5[develop]: stats: Make Stats::Group::mergeStatGroup public

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35615 )



Change subject: stats: Make Stats::Group::mergeStatGroup public
..

stats: Make Stats::Group::mergeStatGroup public

The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.

This change adds some error checking to mergeStatGroup and marks it as
a public method.

Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg 
---
M src/base/stats/group.cc
M src/base/stats/group.hh
2 files changed, 17 insertions(+), 3 deletions(-)



diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a76ad4f..f1eda1d 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -47,7 +47,7 @@
 namespace Stats {

 Group::Group(Group *parent, const char *name)
-: mergedParent(name ? nullptr : parent)
+: mergedParent(nullptr)
 {
 if (parent && name) {
 parent->addStatGroup(name, this);
@@ -152,7 +152,22 @@
 void
 Group::mergeStatGroup(Group *block)
 {
+panic_if(!block, "No stat block provided");
+panic_if(block->mergedParent,
+ "Stat group already merged into another group");
+panic_if(block == this, "Stat group can't merge with itself");
+
+// Track the new stat group
 mergedStatGroups.push_back(block);
+
+// We might not have seen stats that were associated with the
+// child group before it was merged, so add them here.
+for (auto  : block->stats)
+addStat(s);
+
+// Setup the parent pointer so the child know that it needs to
+// register new stats with the parent.
+block->mergedParent = this;
 }

 const std::map &
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 985bf61..ef223bc 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -194,7 +194,6 @@
  */
 const Info * resolveStat(std::string name) const;

-  private:
 /**
  * Merge the contents (stats & children) of a block to this block.
  *
@@ -205,7 +204,7 @@

   private:
 /** Parent pointer if merged into parent */
-Group *const mergedParent;
+Group *mergedParent;

 std::map statGroups;
 std::vector mergedStatGroups;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Gerrit-Change-Number: 35615
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )


Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
..

base, sim, mem, arch: Remove the dummy CPU in NULL

The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.

Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Reviewed-by: Daniel Carvalho 
Tested-by: kokoro 
---
M src/arch/mips/locked_mem.hh
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/arch/riscv/locked_mem.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
11 files changed, 17 insertions(+), 102 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 8400ed6..153a991 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -50,6 +50,7 @@
 #include "arch/registers.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
+#include "cpu/base.hh"
 #include "debug/LLSC.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 Import('*')
-
-if env['TARGET_ISA'] == 'null':
-Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual propert

[gem5-dev] Change in gem5/gem5[develop]: stats: Move global CPU stats to BaseCPU

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34395 )


Change subject: stats: Move global CPU stats to BaseCPU
..

stats: Move global CPU stats to BaseCPU

We currently register global CPU statistics such as sim_insts and
sim_ops from stat_control.cc. This adds an undesriable dependency on
BaseCPU from stats_contro.cc. Move the CPU-specific stats to a global
stat group in BaseCPU. This group is merged with the Root object's
stats which means that they appear as global stats in a typical stat
dump.

Care has been taken to keep the old stat names. However, the order of
the stats.txt will be slightly different due to the way legacy stats
and new-style stats are serialised.

Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34395
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Daniel Carvalho 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/stat_control.cc
M src/sim/stats.hh
4 files changed, 65 insertions(+), 49 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 9ba1b31..ef843d7 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2016-2017, 2019 ARM Limited
+ * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -63,6 +63,7 @@
 #include "sim/clocked_object.hh"
 #include "sim/full_system.hh"
 #include "sim/process.hh"
+#include "sim/root.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
@@ -72,6 +73,8 @@

 using namespace std;

+std::unique_ptr BaseCPU::globalStats;
+
 vector BaseCPU::cpuList;

 // This variable reflects the max number of threads in any CPU.  Be
@@ -370,6 +373,12 @@
 {
 ClockedObject::regStats();

+if (!globalStats) {
+/* We need to construct the global CPU stat structure here
+ * since it needs a pointer to the Root object. */
+globalStats.reset(new GlobalStats(Root::root()));
+}
+
 using namespace Stats;

 numCycles
@@ -754,3 +763,39 @@
 {
 return params()->wait_for_remote_gdb;
 }
+
+
+BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
+: ::Stats::Group(parent),
+simInsts(this, "sim_insts", "Number of instructions simulated"),
+simOps(this, "sim_ops", "Number of ops (including micro ops)  
simulated"),

+hostInstRate(this, "host_inst_rate",
+ "Simulator instruction rate (inst/s)"),
+hostOpRate(this, "host_op_rate",
+   "Simulator op (including micro ops) rate (op/s)")
+{
+simInsts
+.functor(BaseCPU::numSimulatedInsts)
+.precision(0)
+.prereq(simInsts)
+;
+
+simOps
+.functor(BaseCPU::numSimulatedOps)
+.precision(0)
+.prereq(simOps)
+;
+
+hostInstRate
+.precision(0)
+.prereq(simInsts)
+;
+
+hostOpRate
+.precision(0)
+.prereq(simOps)
+;
+
+hostInstRate = simInsts / hostSeconds;
+hostOpRate = simOps / hostSeconds;
+}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c830576..9cf4baa 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -145,6 +145,23 @@
 /** Cache the cache line size that we get from the system */
 const unsigned int _cacheLineSize;

+/** Global CPU statistics that are merged into the Root object. */
+struct GlobalStats : public Stats::Group {
+GlobalStats(::Stats::Group *parent);
+
+::Stats::Value simInsts;
+::Stats::Value simOps;
+
+::Stats::Formula hostInstRate;
+::Stats::Formula hostOpRate;
+};
+
+/**
+ * Pointer to the global stat structure. This needs to be
+ * constructed from regStats since we merge it into the root
+ * group. */
+static std::unique_ptr globalStats;
+
   public:

 /**
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 075be5b..5b66786 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -53,10 +53,6 @@
 #include "base/hostinfo.hh"
 #include "base/statistics.hh"
 #include "base/time.hh"
-#include "config/the_isa.hh"
-#if THE_ISA != NULL_ISA
-#include "cpu/base.hh"
-#endif
 #include "sim/global_event.hh"

 using namespace std;
@@ -65,6 +61,7 @@
 Stats::Value simTicks;
 Stats::Value finalTick;
 Stats::Value simFreq;
+Stats::Value hostSeconds;

 name

[gem5-dev] Change in gem5/gem5[develop]: stats: Move global CPU stats to BaseCPU

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34395 )



Change subject: stats: Move global CPU stats to BaseCPU
..

stats: Move global CPU stats to BaseCPU

We currently register global CPU statistics such as sim_insts and
sim_ops from stat_control.cc. This adds an undesriable dependency on
BaseCPU from stats_contro.cc. Move the CPU-specific stats to a global
stat group in BaseCPU. This group is merged with the Root object's
stats which means that they appear as global stats in a typical stat
dump.

Care has been taken to keep the old stat names. However, the order of
the stats.txt will be slightly different due to the way legacy stats
and new-style stats are serialised.

Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76
Signed-off-by: Andreas Sandberg 
---
M src/cpu/base.cc
M src/cpu/base.hh
M src/sim/stat_control.cc
M src/sim/stats.hh
4 files changed, 65 insertions(+), 45 deletions(-)



diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 9ba1b31..ef843d7 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2016-2017, 2019 ARM Limited
+ * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -63,6 +63,7 @@
 #include "sim/clocked_object.hh"
 #include "sim/full_system.hh"
 #include "sim/process.hh"
+#include "sim/root.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
@@ -72,6 +73,8 @@

 using namespace std;

+std::unique_ptr BaseCPU::globalStats;
+
 vector BaseCPU::cpuList;

 // This variable reflects the max number of threads in any CPU.  Be
@@ -370,6 +373,12 @@
 {
 ClockedObject::regStats();

+if (!globalStats) {
+/* We need to construct the global CPU stat structure here
+ * since it needs a pointer to the Root object. */
+globalStats.reset(new GlobalStats(Root::root()));
+}
+
 using namespace Stats;

 numCycles
@@ -754,3 +763,39 @@
 {
 return params()->wait_for_remote_gdb;
 }
+
+
+BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
+: ::Stats::Group(parent),
+simInsts(this, "sim_insts", "Number of instructions simulated"),
+simOps(this, "sim_ops", "Number of ops (including micro ops)  
simulated"),

+hostInstRate(this, "host_inst_rate",
+ "Simulator instruction rate (inst/s)"),
+hostOpRate(this, "host_op_rate",
+   "Simulator op (including micro ops) rate (op/s)")
+{
+simInsts
+.functor(BaseCPU::numSimulatedInsts)
+.precision(0)
+.prereq(simInsts)
+;
+
+simOps
+.functor(BaseCPU::numSimulatedOps)
+.precision(0)
+.prereq(simOps)
+;
+
+hostInstRate
+.precision(0)
+.prereq(simInsts)
+;
+
+hostOpRate
+.precision(0)
+.prereq(simOps)
+;
+
+hostInstRate = simInsts / hostSeconds;
+hostOpRate = simOps / hostSeconds;
+}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c830576..9cf4baa 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -145,6 +145,23 @@
 /** Cache the cache line size that we get from the system */
 const unsigned int _cacheLineSize;

+/** Global CPU statistics that are merged into the Root object. */
+struct GlobalStats : public Stats::Group {
+GlobalStats(::Stats::Group *parent);
+
+::Stats::Value simInsts;
+::Stats::Value simOps;
+
+::Stats::Formula hostInstRate;
+::Stats::Formula hostOpRate;
+};
+
+/**
+ * Pointer to the global stat structure. This needs to be
+ * constructed from regStats since we merge it into the root
+ * group. */
+static std::unique_ptr globalStats;
+
   public:

 /**
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 075be5b..26a6a27 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -65,6 +65,7 @@
 Stats::Value simTicks;
 Stats::Value finalTick;
 Stats::Value simFreq;
+Stats::Value hostSeconds;

 namespace Stats {

@@ -97,42 +98,14 @@

 struct Global
 {
-Stats::Formula hostInstRate;
-Stats::Formula hostOpRate;
 Stats::Formula hostTickRate;
 Stats::Value hostMemory;
-Stats::Value hostSeconds;
-
-Stats::Value simInsts;
-Stats::Value simOps;

 Global();
 };

 Global::Global()
 {
-simInsts
-.name("sim_insts")
-.desc("Number of instructions simulated")
-.precision(0)
-.prereq(simInsts)
-;
-
-simOps
-.name("sim_ops")
-.desc("Number of ops (including micro ops) simulated")
-.precision(0)
-.

[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in VirtIO devices

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33296 )


Change subject: dev: Use the new ByteOrder param type in VirtIO devices
..

dev: Use the new ByteOrder param type in VirtIO devices

VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).

Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33296
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/dev/virtio/VirtIO.py
M src/dev/virtio/base.cc
2 files changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index bebacad..ed8cffa 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -50,6 +50,7 @@
 subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")

 system = Param.System(Parent.any, "system object")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")

 class VirtIODummyDevice(VirtIODeviceBase):
 type = 'VirtIODummyDevice'
diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 6b4fe0a..84841af 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -37,10 +37,10 @@

 #include "dev/virtio/base.hh"

+#include "base/trace.hh"
 #include "debug/VIO.hh"
 #include "params/VirtIODeviceBase.hh"
 #include "params/VirtIODummyDevice.hh"
-#include "sim/system.hh"

 VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
@@ -326,7 +326,7 @@
size_t config_size, FeatureBits  
features)

 : SimObject(params),
   guestFeatures(0),
-  byteOrder(params->system->getGuestByteOrder()),
+  byteOrder(params->byte_order),
   deviceId(id), configSize(config_size), deviceFeatures(features),
   _deviceStatus(0), _queueSelect(0)
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Gerrit-Change-Number: 33296
Gerrit-PatchSet: 7
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in SimpleUart

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33295 )


Change subject: dev: Use the new ByteOrder param type in SimpleUart
..

dev: Use the new ByteOrder param type in SimpleUart

Use the new ByteOrder param type in SimpleUart. The default value is
currently little endian. However, it is expected that most users of
this device will use single-byte accesses which aren't affected by
endianness.

Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33295
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/dev/serial/Uart.py
M src/dev/serial/simple.cc
2 files changed, 2 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 97efcdd..7955d69 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -52,7 +52,7 @@
 class SimpleUart(Uart):
 type = 'SimpleUart'
 cxx_header = "dev/serial/simple.hh"
-big_endian = Param.Bool(False, "Is the device Big Endian?")
+byte_order = Param.ByteOrder("little", "Device byte order")
 pio_size = Param.Addr(0x4, "Size of address range")
 end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
 "received on the UART")
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
index 97018ab..339d6b9 100644
--- a/src/dev/serial/simple.cc
+++ b/src/dev/serial/simple.cc
@@ -43,9 +43,7 @@
 #include "sim/sim_exit.hh"

 SimpleUart::SimpleUart(const SimpleUartParams *p)
-: Uart(p, p->pio_size),
-  byteOrder(p->big_endian ? ByteOrder::big : ByteOrder::little),
-  endOnEOT(p->end_on_eot)
+: Uart(p, p->pio_size), byteOrder(p->byte_order),  
endOnEOT(p->end_on_eot)

 {
 }


--
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To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Gerrit-Change-Number: 33295
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34236 )



Change subject: base, sim, mem, arch: Remove the dummy CPU in NULL
..

base, sim, mem, arch: Remove the dummy CPU in NULL

The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.

Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg 
---
M src/arch/null/SConscript
D src/arch/null/cpu_dummy.cc
D src/arch/null/cpu_dummy.hh
M src/cpu/base.hh
M src/mem/abstract_mem.cc
M src/mem/cache/prefetch/base.cc
M src/sim/stat_control.cc
M src/sim/system.cc
M src/sim/system.hh
9 files changed, 9 insertions(+), 100 deletions(-)



diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 Import('*')
-
-if env['TARGET_ISA'] == 'null':
-Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder.  You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyrig

[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )


Change subject: sim: Expose the system's byte order as a param
..

sim: Expose the system's byte order as a param

There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.

Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/System.py b/src/sim/System.py
index dcef74b..caf32fb 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -48,6 +48,11 @@
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
 'atomic_noncaching']

+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+default_byte_order = 'big'
+else:
+default_byte_order = 'little'
+
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
@@ -84,6 +89,9 @@

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

+byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
 redirect_paths = VectorParam.RedirectPath([], "Path redirections")

 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop  
when "

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8e2c472..8b31b2f 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
 ByteOrder
 getGuestByteOrder() const
 {
-#if THE_ISA != NULL_ISA
-return TheISA::GuestByteOrder;
-#else
-panic("The NULL ISA has no endianness.");
-#endif
+return _params->byte_order;
 }

  /**

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Gerrit-Change-Number: 33175
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup debug flags API

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34118 )


Change subject: base: Cleanup debug flags API
..

base: Cleanup debug flags API

The debug flags API has a couple of quirks that should be cleaned
up. Specifically:

 * Only CompoundFlag should expose a list of children.
 * The global enable flag is just called "active", this isn't very
   descriptive.
 * Only SimpleFlag exposed a status member. This should be in the base
   class to make the API symmetric.
 * Flag::Sync() is an implementation detail and needs to be protected.

Change-Id: I4d7fd32c80891191aa04f0bd0c334c8cf8d372f5
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34118
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/debug.cc
M src/base/debug.hh
M src/base/trace.cc
M src/python/m5/debug.py
M src/python/pybind11/debug.cc
5 files changed, 79 insertions(+), 44 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/debug.cc b/src/base/debug.cc
index 47febd0..45d9f9d 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -67,7 +79,7 @@
 return flags;
 }

-bool SimpleFlag::_active = false;
+bool Flag::_globalEnable = false;

 Flag *
 findFlag(const std::string )
@@ -96,17 +108,17 @@
 }

 void
-SimpleFlag::enableAll()
+Flag::globalEnable()
 {
-_active = true;
+_globalEnable = true;
 for (auto& i : allFlags())
 i.second->sync();
 }

 void
-SimpleFlag::disableAll()
+Flag::globalDisable()
 {
-_active = false;
+_globalEnable = false;
 for (auto& i : allFlags())
 i.second->sync();
 }
@@ -125,6 +137,19 @@
 k->disable();
 }

+bool
+CompoundFlag::status() const
+{
+if (_kids.empty())
+return false;
+
+for (auto& k : _kids) {
+if (!k->status())
+return false;
+}
+
+return true;
+}

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 1d35be0..a5dc43c 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2010 The Hewlett-Packard Development Company
  * All rights reserved.
@@ -42,45 +54,48 @@
 class Flag
 {
   protected:
+static bool _globalEnable; // whether debug tracings are enabled
+
 const char *_name;
 const char *_desc;

+virtual void sync() { }
+
   public:
 Flag(const char *name, const char *desc);
 virtual ~Flag();

 std::string name() const { return _name; }
 std::string desc() const { return _desc; }
-virtual std::vector kids() { return std::vector(); }

 virtual void enable() = 0;
 virtual void disable() = 0;
-virtual void sync() {}
+virtual bool status() const = 0;
+
+operator bool() const { return status(); }
+bool operator!() const { return !status(); }
+
+static void globalEnable();
+static void globalDisable();
 };

 class SimpleFlag : public Flag
 {
-static bool _active; // whether debug tracings are enabled
   protected:
 bool _tracing; // tracing is enabled and flag is on
 bool _status;  // flag status

+void sync() override { _tracing = _globalEnable && _status; }
+
   public:
 SimpleFlag(const char *name, const char *desc)
 : Flag(name, desc), _status(false)
 { }

[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify arch enum generation

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )


Change subject: scons: Simplify arch enum generation
..

scons: Simplify arch enum generation

C++ allows a trailing comma after the last item in an enum, so there
is no need for a special case.

Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34116
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/SConscript
1 file changed, 4 insertions(+), 10 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/SConscript b/src/SConscript
index 4b6db44..9f82bdc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,11 +645,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class Arch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''
@@ -690,11 +687,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class GPUArch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Gerrit-Change-Number: 34116
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove unused Debug::All flag

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )


Change subject: base: Remove unused Debug::All flag
..

base: Remove unused Debug::All flag

The Debug::All flag doesn't seem to be used. Remove it.

Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34117
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 0 insertions(+), 31 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/debug.cc b/src/base/debug.cc
index b165f64..47febd0 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -125,35 +125,6 @@
 k->disable();
 }

-struct AllFlags : public Flag
-{
-AllFlags()
-: Flag("All", "All Flags")
-{}
-
-void
-enable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->enable();
-}
-
-void
-disable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->disable();
-}
-};
-
-AllFlags theAllFlags;
-Flag *const All = 

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 479a830..1d35be0 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -108,8 +108,6 @@

 Flag *findFlag(const std::string );

-extern Flag *const All;
-
 bool changeFlag(const char *s, bool value);

 } // namespace Debug

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Gerrit-Change-Number: 34117
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Daniel Carvalho 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unused debug APIs

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )


Change subject: python: Remove unused debug APIs
..

python: Remove unused debug APIs

The following APIs are not exported from the _m5 namespace and not
used by any of the debug glue code:

 * m5.debug.findFlag
 * m5.debug.setDebugFlag
 * m5.debug.clearDebugFlag
 * m5.debug.dumpDebugFlags

All of them have a clean Python interface where flags are exported
using the m5.debug.flags dictionary. There is also an m5.debug.help
function that lists the available debug flags.

Remove the unused APIs to avoid confusion.

Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34120
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/pybind11/debug.cc
1 file changed, 0 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 69c497c..84673f1 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -83,10 +83,6 @@
 m_debug
 .def("getAllFlagsVersion", []() { return Debug::allFlagsVersion; })
 .def("allFlags", ::allFlags,  
py::return_value_policy::reference)

-.def("findFlag", ::findFlag)
-.def("setDebugFlag", )
-.def("clearDebugFlag", )
-.def("dumpDebugFlags", )

 .def("schedBreak", )
 .def("setRemoteGDBPort", )

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Gerrit-Change-Number: 34120
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup Debug::CompoundFlag

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )


Change subject: base: Cleanup Debug::CompoundFlag
..

base: Cleanup Debug::CompoundFlag

Compound flags are currently constructed using a constructor with a
finite set of arguments that default to nullptr that refer to child
flags. C++11 introduces two cleaner ways to achieve the same thing,
variadic templates and initializer_list. Use an initializer list to
pass dependent flags.

Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34115
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/SConscript
M src/base/debug.hh
2 files changed, 9 insertions(+), 29 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/SConscript b/src/SConscript
index d9cde28..4b6db44 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1071,15 +1071,12 @@
 if not compound:
 code('SimpleFlag $name("$name", "$desc");')
 else:
-comp_code('CompoundFlag $name("$name", "$desc",')
+comp_code('CompoundFlag $name("$name", "$desc", {')
 comp_code.indent()
-last = len(compound) - 1
-for i,flag in enumerate(compound):
-if i != last:
-comp_code('&$flag,')
-else:
-comp_code('&$flag);')
+for flag in compound:
+comp_code('&$flag,')
 comp_code.dedent()
+comp_code('});')

 code.append(comp_code)
 code()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7c9834c..479a830 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -30,6 +30,7 @@
 #ifndef __BASE_DEBUG_HH__
 #define __BASE_DEBUG_HH__

+#include 
 #include 
 #include 
 #include 
@@ -87,31 +88,13 @@
   protected:
 std::vector _kids;

-void
-addFlag(Flag *f)
-{
-if (f != nullptr)
-_kids.push_back(f);
-}
-
   public:
+template
 CompoundFlag(const char *name, const char *desc,
-Flag *f00 = nullptr, Flag *f01 = nullptr,
-Flag *f02 = nullptr, Flag *f03 = nullptr,
-Flag *f04 = nullptr, Flag *f05 = nullptr,
-Flag *f06 = nullptr, Flag *f07 = nullptr,
-Flag *f08 = nullptr, Flag *f09 = nullptr,
-Flag *f10 = nullptr, Flag *f11 = nullptr,
-Flag *f12 = nullptr, Flag *f13 = nullptr,
-Flag *f14 = nullptr, Flag *f15 = nullptr,
-Flag *f16 = nullptr, Flag *f17 = nullptr,
-Flag *f18 = nullptr, Flag *f19 = nullptr)
-: Flag(name, desc)
+ std::initializer_list flags)
+: Flag(name, desc),
+  _kids(flags)
 {
-addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03);  
addFlag(f04);
-addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08);  
addFlag(f09);
-addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13);  
addFlag(f14);
-addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);  
addFlag(f19);

 }

 std::vector kids() { return _kids; }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Gerrit-Change-Number: 34115
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Assignee: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: python: Add the ability to check if a debug flag has been enabled

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )


Change subject: python: Add the ability to check if a debug flag has been  
enabled

..

python: Add the ability to check if a debug flag has been enabled

There is currently no Python API to check if a debug flag is
enabled. Add a new status property that can be read or set to control
the status of a flag. The stat of a flag can also be queried by
converting it to a bool.

For example:

  m5.debug.flags["XBar"].status = True

  if m5.debug.flags["XBar"]:
  print("XBar debugging is on")

Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34119
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/pybind11/debug.cc
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index ed2942b..69c497c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -98,6 +98,20 @@
 .def_property_readonly("desc", ::Flag::desc)
 .def("enable", ::Flag::enable)
 .def("disable", ::Flag::disable)
+.def_property("status",
+  [](const Debug::Flag *flag) {
+  return flag->status();
+  },
+  [](Debug::Flag *flag, bool state) {
+  if (state) {
+  flag->enable();
+  } else {
+  flag->disable();
+  }
+  })
+.def("__bool__", [](const Debug::Flag *flag) {
+return flag->status();
+})
 ;

 py::class_(m_debug, "SimpleFlag", c_flag);

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Gerrit-Change-Number: 34119
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unused debug APIs

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )



Change subject: python: Remove unused debug APIs
..

python: Remove unused debug APIs

The following APIs are not exported from the _m5 namespace and not
used by any of the debug glue code:

 * m5.debug.findFlag
 * m5.debug.setDebugFlag
 * m5.debug.clearDebugFlag
 * m5.debug.dumpDebugFlags

All of them have a clean Python interface where flags are exported
using the m5.debug.flags dictionary. There is also an m5.debug.help
function that lists the available debug flags.

Remove the unused APIs to avoid confusion.

Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/debug.cc
1 file changed, 0 insertions(+), 4 deletions(-)



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 69c497c..84673f1 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -83,10 +83,6 @@
 m_debug
 .def("getAllFlagsVersion", []() { return Debug::allFlagsVersion; })
 .def("allFlags", ::allFlags,  
py::return_value_policy::reference)

-.def("findFlag", ::findFlag)
-.def("setDebugFlag", )
-.def("clearDebugFlag", )
-.def("dumpDebugFlags", )

 .def("schedBreak", )
 .def("setRemoteGDBPort", )

--
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[gem5-dev] Change in gem5/gem5[develop]: python: Add the ability to check if a debug flag has been enabled

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )



Change subject: python: Add the ability to check if a debug flag has been  
enabled

..

python: Add the ability to check if a debug flag has been enabled

There is currently no Python API to check if a debug flag is
enabled. Add a new status property that can be read or set to control
the status of a flag. The stat of a flag can also be queried by
converting it to a bool.

For example:

  m5.debug.flags["XBar"].status = True

  if m5.debug.flags["XBar"]:
  print("XBar debugging is on")

Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/debug.cc
1 file changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index ed2942b..69c497c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -98,6 +98,20 @@
 .def_property_readonly("desc", ::Flag::desc)
 .def("enable", ::Flag::enable)
 .def("disable", ::Flag::disable)
+.def_property("status",
+  [](const Debug::Flag *flag) {
+  return flag->status();
+  },
+  [](Debug::Flag *flag, bool state) {
+  if (state) {
+  flag->enable();
+  } else {
+  flag->disable();
+  }
+  })
+.def("__bool__", [](const Debug::Flag *flag) {
+return flag->status();
+})
 ;

 py::class_(m_debug, "SimpleFlag", c_flag);

--
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup debug flags API

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34118 )



Change subject: base: Cleanup debug flags API
..

base: Cleanup debug flags API

The debug flags API has a couple of quirks that should be cleaned
up. Specifically:

 * Only CompoundFlag should expose a list of children.
 * The global enable flag is just called "active", this isn't very
   descriptive.
 * Only SimpleFlag exposed a status member. This should be in the base
   class to make the API symmetric.
 * Flag::Sync() is an implementation detail and needs to be protected.

Change-Id: I4d7fd32c80891191aa04f0bd0c334c8cf8d372f5
Signed-off-by: Andreas Sandberg 
---
M src/base/debug.cc
M src/base/debug.hh
M src/base/trace.cc
M src/python/m5/debug.py
M src/python/pybind11/debug.cc
5 files changed, 79 insertions(+), 44 deletions(-)



diff --git a/src/base/debug.cc b/src/base/debug.cc
index 47febd0..45d9f9d 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -67,7 +79,7 @@
 return flags;
 }

-bool SimpleFlag::_active = false;
+bool Flag::_globalEnable = false;

 Flag *
 findFlag(const std::string )
@@ -96,17 +108,17 @@
 }

 void
-SimpleFlag::enableAll()
+Flag::globalEnable()
 {
-_active = true;
+_globalEnable = true;
 for (auto& i : allFlags())
 i.second->sync();
 }

 void
-SimpleFlag::disableAll()
+Flag::globalDisable()
 {
-_active = false;
+_globalEnable = false;
 for (auto& i : allFlags())
 i.second->sync();
 }
@@ -125,6 +137,19 @@
 k->disable();
 }

+bool
+CompoundFlag::status() const
+{
+if (_kids.empty())
+return false;
+
+for (auto& k : _kids) {
+if (!k->status())
+return false;
+}
+
+return true;
+}

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 1d35be0..a5dc43c 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2010 The Hewlett-Packard Development Company
  * All rights reserved.
@@ -42,45 +54,48 @@
 class Flag
 {
   protected:
+static bool _globalEnable; // whether debug tracings are enabled
+
 const char *_name;
 const char *_desc;

+virtual void sync() { }
+
   public:
 Flag(const char *name, const char *desc);
 virtual ~Flag();

 std::string name() const { return _name; }
 std::string desc() const { return _desc; }
-virtual std::vector kids() { return std::vector(); }

 virtual void enable() = 0;
 virtual void disable() = 0;
-virtual void sync() {}
+virtual bool status() const = 0;
+
+operator bool() const { return status(); }
+bool operator!() const { return !status(); }
+
+static void globalEnable();
+static void globalDisable();
 };

 class SimpleFlag : public Flag
 {
-static bool _active; // whether debug tracings are enabled
   protected:
 bool _tracing; // tracing is enabled and flag is on
 bool _status;  // flag status

+void sync() override { _tracing = _globalEnable && _status; }
+
   public:
 SimpleFlag(const char *name, const char *desc)
 : Flag(name, desc), _status(false)
 { }

-bool status() const { return _tracing; }
-operator bool() const { return _tracing; }
-bool operator!() const { return !_tracing; }
+bool status() const override { return _tracing; }

-void enable()  { _status = true;  sync(); }
-

[gem5-dev] Change in gem5/gem5[develop]: base: Remove unused Debug::All flag

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )



Change subject: base: Remove unused Debug::All flag
..

base: Remove unused Debug::All flag

The Debug::All flag doesn't seem to be used. Remove it.

Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Signed-off-by: Andreas Sandberg 
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 0 insertions(+), 31 deletions(-)



diff --git a/src/base/debug.cc b/src/base/debug.cc
index b165f64..47febd0 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -125,35 +125,6 @@
 k->disable();
 }

-struct AllFlags : public Flag
-{
-AllFlags()
-: Flag("All", "All Flags")
-{}
-
-void
-enable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->enable();
-}
-
-void
-disable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->disable();
-}
-};
-
-AllFlags theAllFlags;
-Flag *const All = 

 bool
 changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 479a830..1d35be0 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -108,8 +108,6 @@

 Flag *findFlag(const std::string );

-extern Flag *const All;
-
 bool changeFlag(const char *s, bool value);

 } // namespace Debug

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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify arch enum generation

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )



Change subject: scons: Simplify arch enum generation
..

scons: Simplify arch enum generation

C++ allows a trailing comma after the last item in an enum, so there
is no need for a special case.

Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Signed-off-by: Andreas Sandberg 
---
M src/SConscript
1 file changed, 4 insertions(+), 10 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index 4b6db44..9f82bdc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,11 +645,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class Arch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''
@@ -690,11 +687,8 @@
 # create an enum for any run-time determination of the ISA, we
 # reuse the same name as the namespaces
 code('enum class GPUArch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code('  $0 = $1', namespace(isa), define(isa))
-else:
-code('  $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code('  $0 = $1,', namespace(isa), define(isa))
 code('};')

 code('''

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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup Debug::CompoundFlag

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )



Change subject: base: Cleanup Debug::CompoundFlag
..

base: Cleanup Debug::CompoundFlag

Compound flags are currently constructed using a constructor with a
finite set of arguments that default to nullptr that refer to child
flags. C++11 introduces two cleaner ways to achieve the same thing,
variadic templates and initializer_list. Use an initializer list to
pass dependent flags.

Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Signed-off-by: Andreas Sandberg 
---
M src/SConscript
M src/base/debug.hh
2 files changed, 9 insertions(+), 29 deletions(-)



diff --git a/src/SConscript b/src/SConscript
index d9cde28..4b6db44 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1071,15 +1071,12 @@
 if not compound:
 code('SimpleFlag $name("$name", "$desc");')
 else:
-comp_code('CompoundFlag $name("$name", "$desc",')
+comp_code('CompoundFlag $name("$name", "$desc", {')
 comp_code.indent()
-last = len(compound) - 1
-for i,flag in enumerate(compound):
-if i != last:
-comp_code('&$flag,')
-else:
-comp_code('&$flag);')
+for flag in compound:
+comp_code('&$flag,')
 comp_code.dedent()
+comp_code('});')

 code.append(comp_code)
 code()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7c9834c..479a830 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -30,6 +30,7 @@
 #ifndef __BASE_DEBUG_HH__
 #define __BASE_DEBUG_HH__

+#include 
 #include 
 #include 
 #include 
@@ -87,31 +88,13 @@
   protected:
 std::vector _kids;

-void
-addFlag(Flag *f)
-{
-if (f != nullptr)
-_kids.push_back(f);
-}
-
   public:
+template
 CompoundFlag(const char *name, const char *desc,
-Flag *f00 = nullptr, Flag *f01 = nullptr,
-Flag *f02 = nullptr, Flag *f03 = nullptr,
-Flag *f04 = nullptr, Flag *f05 = nullptr,
-Flag *f06 = nullptr, Flag *f07 = nullptr,
-Flag *f08 = nullptr, Flag *f09 = nullptr,
-Flag *f10 = nullptr, Flag *f11 = nullptr,
-Flag *f12 = nullptr, Flag *f13 = nullptr,
-Flag *f14 = nullptr, Flag *f15 = nullptr,
-Flag *f16 = nullptr, Flag *f17 = nullptr,
-Flag *f18 = nullptr, Flag *f19 = nullptr)
-: Flag(name, desc)
+ std::initializer_list flags)
+: Flag(name, desc),
+  _kids(flags)
 {
-addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03);  
addFlag(f04);
-addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08);  
addFlag(f09);
-addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13);  
addFlag(f14);
-addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);  
addFlag(f19);

 }

 std::vector kids() { return _kids; }

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[gem5-dev] Re: ARM build failures

[Andreas Sandberg via gem5-dev]

+ Ciro, Richard

Hi Everyone,

Thanks for pointing this out and submitting a fix.

Richard/Ciro/Giacomo: Could one of you review this so we can merge the fix?

Thanks,
Andreas

On 31/08/2020 05:41, Bobby Bruce wrote:
Hey Gabe,

Iru Cai made a fix for this a week or so ago: 
https://gem5-review.googlesource.com/c/public/gem5/+/33154. Not sure if this 
addresses all concerns, but their change is mostly basic reduction due to `imm` 
and `ecount` being unsigned. I also find if you take on board these 
observations, there's at least one unreachable branch, and one condition that's 
always true (see my comments in the Gerrit PatchSet).

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Sun, Aug 30, 2020 at 3:52 AM Gabe Black via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
Hi folks. I'm seeing a few build failures for ARM with gcc version 10.2. Since 
these look like they may be real bugs and I don't want to make a mess fixing 
them or do a bunch of research, I'll mention them here so we can collectively 
find the right fix. There are a lot of instances of these two:

build/ARM/arch/arm/generated/exec-ns.cc.inc:278501:40: error: comparison of 
unsigned express
ion in '>= 0' is always true [-Werror=type-limits]
278501 | bool posCount = ((count * imm) >= 0);


build/ARM/arch/arm/generated/exec-ns.cc.inc:278970:40: error: comparison of 
unsigned express
ion in '< 0' is always false [-Werror=type-limits]
278970 | bool negCount = ((count * imm) < 0);

I'm not sure what's going on with these. Maybe applying the same template with 
both signed and unsigned imm and count fields? As far as I can tell with a 
little digging around, imm is usually unsigned. I'm not sure where count comes 
from, but I'm guessing also unsigned?

build/ARM/arch/arm/generated/exec-ns.cc.inc:169243:29: error: 
'destReg.ArmISAInst::VqdmulhsQ
<_Element>::execute::RegVect::regs[0]' may be used uninitialized 
in this functi
on [-Werror=maybe-uninitialized]
169243 | FpDestP0 = letoh(destReg.regs[0]);

I haven't looked into these at all.

build/ARM/arch/arm/generated/exec-ns.cc.inc:169491:17: error: comparison of 
unsigned express
ion in '< 0' is always false [-Werror=type-limits]
169491 | if (imm < 0 && imm >= eCount) {

This one looks really fishy. How would imm be both less than 0 and also greater 
than eCount? Is eCount negative? Is it ok for it to be just a little negative? 
Is this supposed to be an ||? Apparently imm is unsigned anyway, so comparing 
it with 0 is pointless.

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: python: Add support for introspecting scalar stats

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33176 )


Change subject: python: Add support for introspecting scalar stats
..

python: Add support for introspecting scalar stats

This change adds a wrapper for the ScalarInfo stat type to enable
introspection of scalar stats from Python. Due to the slightly
confusing use of proxy objects in the stat system, PyBind11 fails to
automatically cast to the right wrapper type. This is worked around in
the by explicitly casting to the relevant type's Python wrapper.

To make the interface more Python-friendly, this change also changes
the semantics of resolveStat to raise an exception if the stat can't
be found.

Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33176
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/pybind11/stats.cc
1 file changed, 46 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1149eba..b146aa3 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -54,6 +54,25 @@

 namespace py = pybind11;

+static const py::object
+cast_stat_info(const Stats::Info *info)
+{
+/* PyBind11 gets confused by the InfoProxy magic, so we need to
+ * explicitly cast to the right wrapper type. */
+
+#define TRY_CAST(T) do {\
+auto _stat = dynamic_cast(info); \
+if (_stat)  \
+return py::cast(_stat); \
+} while (0)
+
+TRY_CAST(Stats::ScalarInfo);
+
+return py::cast(info);
+
+#undef TRY_CAST
+}
+
 namespace Stats {

 void
@@ -120,14 +139,39 @@
 .def("visit", ::Info::visit)
 ;

+py::class_>(
+   m, "ScalarInfo")
+.def("value", ::ScalarInfo::value)
+.def("result", ::ScalarInfo::result)
+.def("total", ::ScalarInfo::total)
+;
+
 py::class_>(
 m, "Group")
 .def("regStats", ::Group::regStats)
 .def("resetStats", ::Group::resetStats)
 .def("preDumpStats", ::Group::preDumpStats)
-.def("getStats", ::Group::getStats)
+.def("getStats", [](const Stats::Group )
+ -> std::vector {
+
+ auto stats = self.getStats();
+std::vector py_stats;
+py_stats.reserve(stats.size());
+std::transform(stats.begin(), stats.end(),
+   std::back_inserter(py_stats),
+   cast_stat_info);
+return py_stats;
+})
 .def("getStatGroups", ::Group::getStatGroups)
 .def("addStatGroup", ::Group::addStatGroup)
-.def("resolveStat", ::Group::resolveStat)
+.def("resolveStat", [](const Stats::Group ,
+   const std::string ) -> py::object {
+ const Stats::Info *stat = self.resolveStat(name);
+ if (!stat)
+ throw pybind11::key_error("Unknown stat name");
+
+ return cast_stat_info(stat);
+ })
 ;
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Gerrit-Change-Number: 33176
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in VirtIO devices

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33296 )



Change subject: dev: Use the new ByteOrder param type in VirtIO devices
..

dev: Use the new ByteOrder param type in VirtIO devices

VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).

Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg 
---
M src/dev/virtio/VirtIO.py
M src/dev/virtio/base.cc
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index bebacad..ed8cffa 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -50,6 +50,7 @@
 subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")

 system = Param.System(Parent.any, "system object")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")

 class VirtIODummyDevice(VirtIODeviceBase):
 type = 'VirtIODummyDevice'
diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 6b4fe0a..f991625 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -40,7 +40,6 @@
 #include "debug/VIO.hh"
 #include "params/VirtIODeviceBase.hh"
 #include "params/VirtIODummyDevice.hh"
-#include "sim/system.hh"

 VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
@@ -326,7 +325,7 @@
size_t config_size, FeatureBits  
features)

 : SimObject(params),
   guestFeatures(0),
-  byteOrder(params->system->getGuestByteOrder()),
+  byteOrder(params->byte_order),
   deviceId(id), configSize(config_size), deviceFeatures(features),
   _deviceStatus(0), _queueSelect(0)
 {

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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in SimpleUart

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33295 )



Change subject: dev: Use the new ByteOrder param type in SimpleUart
..

dev: Use the new ByteOrder param type in SimpleUart

Use the new ByteOrder param type in SimpleUart. The default value is
inherited from a parent object (likely the system) with a byte_order
param.

Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg 
---
M src/dev/serial/Uart.py
M src/dev/serial/simple.cc
2 files changed, 2 insertions(+), 4 deletions(-)



diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 97efcdd..5e64481 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -52,7 +52,7 @@
 class SimpleUart(Uart):
 type = 'SimpleUart'
 cxx_header = "dev/serial/simple.hh"
-big_endian = Param.Bool(False, "Is the device Big Endian?")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")
 pio_size = Param.Addr(0x4, "Size of address range")
 end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
 "received on the UART")
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
index 97018ab..339d6b9 100644
--- a/src/dev/serial/simple.cc
+++ b/src/dev/serial/simple.cc
@@ -43,9 +43,7 @@
 #include "sim/sim_exit.hh"

 SimpleUart::SimpleUart(const SimpleUartParams *p)
-: Uart(p, p->pio_size),
-  byteOrder(p->big_endian ? ByteOrder::big : ByteOrder::little),
-  endOnEOT(p->end_on_eot)
+: Uart(p, p->pio_size), byteOrder(p->byte_order),  
endOnEOT(p->end_on_eot)

 {
 }


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[gem5-dev] Change in gem5/gem5[develop]: python: Add support for introspecting scalar stats

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33176 )



Change subject: python: Add support for introspecting scalar stats
..

python: Add support for introspecting scalar stats

This change adds a wrapper for the ScalarInfo stat type to enable
introspection of scalar stats from Python. Due to the slightly
confusing use of proxy objects in the stat system, PyBind11 fails to
automatically cast to the right wrapper type. This is worked around in
the by explicitly casting to the relevant type's Python wrapper.

To make the interface more Python-friendly, this change also changes
the semantics of resolveStat to raise an exception if the stat can't
be found.

Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Signed-off-by: Andreas Sandberg 
---
M src/python/pybind11/stats.cc
1 file changed, 46 insertions(+), 2 deletions(-)



diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1149eba..f69aa70 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -54,6 +54,25 @@

 namespace py = pybind11;

+static const py::object
+cast_stat_info(const Stats::Info *info)
+{
+/* PyBind11 gets confused by the InfoProxy magic, so we need to
+ * explicitly cast to the right wrapper type. */
+
+#define TRY_CAST(T) do {\
+auto _stat = dynamic_cast(info); \
+if (_stat)  \
+return py::cast(_stat); \
+} while (0)
+
+TRY_CAST(Stats::ScalarInfo);
+
+return py::cast(info);
+
+#undef TRY_CAST
+}
+
 namespace Stats {

 void
@@ -120,14 +139,39 @@
 .def("visit", ::Info::visit)
 ;

+py::class_>(
+   m, "ScalarInfo")
+.def("value", ::ScalarInfo::value)
+.def("result", ::ScalarInfo::result)
+.def("total", ::ScalarInfo::result)
+;
+
 py::class_>(
 m, "Group")
 .def("regStats", ::Group::regStats)
 .def("resetStats", ::Group::resetStats)
 .def("preDumpStats", ::Group::preDumpStats)
-.def("getStats", ::Group::getStats)
+.def("getStats", [](const Stats::Group )
+ -> std::vector {
+
+ auto stats = self.getStats();
+std::vector py_stats;
+py_stats.reserve(stats.size());
+std::transform(stats.begin(), stats.end(),
+   std::back_inserter(py_stats),
+   cast_stat_info);
+return py_stats;
+})
 .def("getStatGroups", ::Group::getStatGroups)
 .def("addStatGroup", ::Group::addStatGroup)
-.def("resolveStat", ::Group::resolveStat)
+.def("resolveStat", [](const Stats::Group ,
+   const std::string ) -> py::object {
+ const Stats::Info *stat = self.resolveStat(name);
+ if (!stat)
+ throw pybind11::key_error("Unknown stat name");
+
+ return cast_stat_info(stat);
+ })
 ;
 }

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[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )



Change subject: sim: Expose the system's byte order as a param
..

sim: Expose the system's byte order as a param

There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.

Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg 
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)



diff --git a/src/sim/System.py b/src/sim/System.py
index f4a9f82..773bb32 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -54,6 +54,11 @@
 'little',
 ]

+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+defult_byte_order = 'big'
+else:
+default_byte_order = 'little'
+
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
@@ -90,6 +95,9 @@

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

+byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
 redirect_paths = VectorParam.RedirectPath([], "Path redirections")

 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop  
when "

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821..b7fb789 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
 ByteOrder
 getGuestByteOrder() const
 {
-#if THE_ISA != NULL_ISA
-return TheISA::GuestByteOrder;
-#else
-panic("The NULL ISA has no endianness.");
-#endif
+return _params->byte_order;
 }

  /**

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[gem5-dev] gem5 documentation repo

[Andreas Sandberg via gem5-dev]

Hi All,

I just had a quick look at the excellent new documentation section on
the gem5 website. A big thanks to everyone who has worked on making that
a reality!

One thing that I noticed when browsing the documentation is hosted in
the website repo and not the code repo. Would it make sense to move it
across to the code repo make sure it tracks the source code?

In practice, we probably want to present (at least) two different views
of the documentation, one for the latest release and one for develop.
Another option would be to deal with versioning in the website repo, but
that will make it hard to keep the documentation up-to-date when
submitting code changes.

Cheers,
Andreas

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[gem5-dev] Re: [Suggestion] Replace gem5-users mailing-list with Discourse

[Andreas Sandberg via gem5-dev]

On 06/07/2020 19:37, Jason Lowe-Power wrote:
On Mon, Jul 6, 2020 at 11:22 AM Andreas Sandberg via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
Hi Bobby,

Can't we solve some of these issues by just moving the mailinglist to a better system 
with good archiving? That should solve both the spam issue and some of the usability 
issues. I have looked at bit at groups.io<http://groups.io> since it is used in 
a project I'm contributing to in my spare time and it seems like a good hybrid 
between a mailinglist and a forum. They seem to have good support for grouping by 
topic, hash tag filtering, RSS feeds, and plenty of integrations.

The maintenance requirement of gem5-us...@gem5.org<mailto:gem5-us...@gem5.org> 
has been extraordinary. I really don't see how we can keep using that mailing list. 
Bobby has spent 50+ hours fighting with it in the past 6 months. From what I can 
tell, the way we have many people posting to a single list that ~1000 people 
subscribe to just isn't a normal use case for email anymore. We're getting blocked by 
spam filters, having to answer lots of questions about how to subscribe, etc.


The number of subscribers shouldn't be a problem. The Zephyr mailinglists have 
close to 2000 subscribers and several other open source projects have 
mailinglists with thousands of subscribers.

I think part of the problem here is that the mail servers for gem5.org are 
misconfigured or at least lack the configuration required for modern email 
systems.  According to the SMTP headers, our email servers have flagged a 
recent email from the dev list as failing SPF checks. I suspect the domain 
lacks (correct) SPF, DKIM, and DMARC records. Missing records will cause issues 
(higher likelihood of being flagged as spam), while incorrect ones will likely 
flag emails as spam right away.


If someone else is willing to step up and take ownership of the mailing list 
that would be great. It's just not something that we currently have resources 
for right now. We thought that moving to a managed system would help, but it 
hasn't solved the main problems: mail is still getting hijacked by spam 
filters, and people are still having problems signing up.


I really can't see what a Discourse-style forum would give us that you can't 
get from an email list with a good archive. I generally find forums at least as 
annoying as email archives when going back to look for information about a 
topic. The lack of threading within topics tends to make discussion really hard 
to follow, which usually isn't an issue in a well-behaved email list.

I'm not sure I understand the difference between Discourse and 
groups.io<http://groups.io> other than the interface. Could you describe why you 
think that groups.io<http://groups.io> would be better than discourse?

Also, from my experience, we have a number of people who try to contribute that *don't* 
have a well behaved email client. We see a large number of messages that are "off 
thread" (e.g., replying to a digest, changing the subject line accidentally, or just 
replying to the wrong message).


My impression of groups.io is that it is primarily an email distribution 
service with a fancy web frontend while Discourse is primarily a web system 
with email notifications.



Is the barrier of entry that people feel like the list is to "formal" or think 
that their questions are stupid? I'm not convinced that the latter would be solved by 
switching to a forum-style system like Discourse. A less formal chat system in addition 
to the list might be a better way to lower the barrier of entry.

I disagree somewhat with this. I think that if we had a discourse section titled "any 
questions here" or "new user questions" that it *would* lower the barrier to entry 
and make people feel more comfortable.


Hmm, yes, that is a good point.


I have found the Slack (despite the poor threading) system used by Zephyr very useful 
when debugging/developing drivers. It has been a convenient low-latency channel when 
working on the same subsystem as other people in the project and a general "I have 
seen this weird issue, has anyone else seen anything like it?". It's not a complete 
substitute for email lists though.

I feel that while slack might be useful, it's fundamentally different from the 
current users list. While it's gotten much better over the past several years, 
we still frequently answer the same questions over and over again on the 
mailing list because 1) we need to improve our documentation and 2) the mailing 
list isn't easy for most people to search.

I (personally) just can't imagine answering gem5 questions on slack. There's 
too much in my life that demands immediate attention already! But maybe that's 
just me.

I see them as serving different purposes. I wouldn't expect senior community members to hangout in 
an ask me anything channel all the time, maybe during "office hours

[gem5-dev] Re: [Suggestion] Replace gem5-users mailing-list with Discourse

[Andreas Sandberg via gem5-dev]

Hi Bobby,

Can't we solve some of these issues by just moving the mailinglist to a better 
system with good archiving? That should solve both the spam issue and some of 
the usability issues. I have looked at bit at groups.io since it is used in a 
project I'm contributing to in my spare time and it seems like a good hybrid 
between a mailinglist and a forum. They seem to have good support for grouping 
by topic, hash tag filtering, RSS feeds, and plenty of integrations.

I really can't see what a Discourse-style forum would give us that you can't 
get from an email list with a good archive. I generally find forums at least as 
annoying as email archives when going back to look for information about a 
topic. The lack of threading within topics tends to make discussion really hard 
to follow, which usually isn't an issue in a well-behaved email list.

Is the barrier of entry that people feel like the list is to "formal" or think 
that their questions are stupid? I'm not convinced that the latter would be solved by 
switching to a forum-style system like Discourse. A less formal chat system in addition 
to the list might be a better way to lower the barrier of entry.

I have found the Slack (despite the poor threading) system used by Zephyr very useful 
when debugging/developing drivers. It has been a convenient low-latency channel when 
working on the same subsystem as other people in the project and a general "I have 
seen this weird issue, has anyone else seen anything like it?". It's not a complete 
substitute for email lists though.

Cheers,
Andreas

On 06/07/2020 03:34, Bobby Bruce via gem5-dev wrote:
I personally see the problem of people not answering questions to be a fixed constant 
regardless as to what medium we choose. It's a shame, but it's a "people 
problem" which I agree won't be solved by deploying new platforms.

The reason for moving from the mailing-list is the mailing-list just doesn't 
appear to be an appropriate technology for tech support. I get emails every 
other week from someone who struggles to join gem5-users, and it normally turns 
out their gem5-user emails are ending up in spam. It's difficult to search 
through the mail archive to see if your question has been asked previously, 
it's hard to format your messages correctly, impossible to tag or categorize, 
and, I've already had students tell me they feel like reaching out over the 
gem5-users mailing list is awkward and embarrassing for the type of questions 
they want to ask. As a result, they just avoid doing so.

My issue with slack is it's got poor threading, and I'd quite like a good 
archive of answered questions for people to search. Though I'm not opposed to 
it as it has the plus of being popular (as shallow as it may be, I find going 
with the most popular solution to a problem is often the best course-of-action).

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Thu, Jul 2, 2020 at 3:45 PM Gabe Black via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
I haven't used Slack before (yeah, I know, behind the times :-), but I 100% 
agree with that last part. Having the perfect medium won't help if there aren't 
enough people around to actually use it to answer questions.

Gabe

On Thu, Jul 2, 2020 at 9:45 AM Andreas Sandberg via gem5-dev 
mailto:gem5-dev@gem5.org>> wrote:
I would probably be more in favour of a split email+Slack/Teams
approach. Email works well for most discussion, but I like the quick
more informal communication in a chat system. I have generally been very
happy with the way Slack has worked when I have contributed to Zephyr in
my spare time. As long as you have a threading email client, I can't see
any benefits of a forum other than archiving (services like 
groups.io<http://groups.io>
seems to solve that).

I think we are fooling ourselves if we think switching from email to a
different medium is going to solve underlying problem the there is a
small number of experienced users that answer most of the questions on
the lists.

Cheers,
Andreas

On 10/06/2020 16:32, Daniel Gerzhoy via gem5-dev wrote:

I think this is a great idea! Emails threads aren't a great way to do this
just because there's no mechanism for well formatted responses to
particular points in someone's questions, posting code, or things like
"upvoting" responses.

I see Daniel's point about less engagement if we move it to a forum, but I
think that could be alleviated by encouraging people to keep email
notifications up.

Cheers,

Dan

On Wed, Jun 10, 2020 at 5:23 AM Giacomo Travaglini via gem5-dev <
gem5-dev@gem5.org<mailto:gem5-dev@gem5.org>> wrote:


I agree with Daniel and Ciro; it's difficult/annoying to navigate through
old unanswered emails and I presume nobody does that at the moment.
Most of the time if your email doesn't get a quick response as soon as it
gets posted, you can forget about getting

[gem5-dev] Re: mercurial support?

[Andreas Sandberg via gem5-dev]

Hi Gabe,

As far as I know, we aren't keeping the Mercurial server in sync with the git 
repo any more. I can't see any reason to keep Mercurial-related cruft in the 
new repo.

Cheers,
Andreas

On 05/07/2020 02:08, Gabe Black via gem5-dev wrote:
Hi folks. Have we officially dropped support for checking out gem5 through 
mercurial? If so, we should probably delete the various bits and pieces lying 
around which were for that. If not then never mind...

Gabe



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