[gem5-users] Re: How to create serial terminal when creating disk images?

[Ciro Santilli via gem5-users]

This is one of the things I've never had the patience to figure out, some ideas:

  *   investigate in QEMU first as it is much faster
  *   look into busybox's init code


From: Chao Fu via gem5-users 
Sent: Wednesday, November 4, 2020 3:12 PM
To: gem5-users@gem5.org 
Cc: Chao Fu <605636...@qq.com>
Subject: [gem5-users] How to create serial terminal when creating disk images?

Hi,
I've recently been created a disk image for GEM5 FS mode. However, I have 
encountered some problems.

I download ubuntu root file from: 
http://cdimage.ubuntu.com/ubuntu-base/releases/20.04/release/ubuntu-base-20.04.1-base-arm64.tar.gz

And I follow the second method of this website tutorial: 
http://www.gem5.org/documentation/general_docs/fullsystem/disks

Follow the tutorial instructions, I tried to put the following code into 
/etc/init/tty-gem5.conf . However, I found that my operating system root file 
did not have /etc/init directory. But I still created a new file 
/etc/init/tty-gem5.conf.

It is a pity that I encoutered problems when I started this image.

Here is the error message:

[0.697855] Freeing unused kernel memory: 384K
[0.699120] Starting init: /etc/init exists but couldn't execute it (error 
-13)
/bin/sh: 0: can't access tty; job control turned off

How do I create a serial terminal correctly? Is there a problem with the 
operating system files I downloaded?

Thanks in advance!

Kind Regards,

Chao
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[gem5-users] Re: File sizes of simulators generated by test script are much larger than those built by manual scons commands

[Ciro Santilli via gem5-users]

Yes, I had also previously observed that debug symbols make the huge majority 
of the executable's size, and for some reason much more so in .opt than in 
debug (presumably it takes more information to map back optimized code to 
source).

You can confirm that by using strip gem5.opt or gcc- s during build, which 
leads to binaries of the order of 60Mb.

Related thread: https://gem5.atlassian.net/browse/GEM5-572

From: Liao Xiongfei via gem5-users 
Sent: Friday, October 30, 2020 4:38 PM
To: gem5-users@gem5.org 
Cc: Liao Xiongfei 
Subject: [gem5-users] File sizes of simulators generated by test script are 
much larger than those built by manual scons commands


Hi all,



When I ran the test script under $GEM5/tests using command “python main.py run” 
on a machine previously without any gem5 simulator built, the script built 5 
different gem5.opt simulators before running test suites.



However, the file sizes of the simulators are pretty large, shown below. The 
gem5.opt for RISC-V is 4.4GB and failed with error message “cannot allocate 
memory”.

1.8Gbuild/ARM/gem5.opt

858Mbuild/NULL/gem5.opt

4.4Gbuild/RISCV/gem5.opt

1.5Gbuild/X86/gem5.opt

1.5Gbuild/X86_MSI/gem5.opt



On the other hand, the gem5.debug simulation was built using “scons 
build/RISCV/gem5.debug –j 8” and its size is much smaller.

522Mbuild/RISCV/gem5.debug



Are these caused by different compiler or linker settings?



I was surprised by a large number of failed tests because RISCV gem5.opt could 
not run. Hopefully, this could be fixed somehow. Thanks.


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[gem5-users] Re: SE Mode and Std::thread

[Ciro Santilli via gem5-users]

Daniel, if you manage to reproduce on clean develop, please also open an issue 
at https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues I'd also be 
curious to see if it reproduces on se.py (so I could see if it also happens on 
ARM).

We've had some ARM-specific SE issues e.g. at 
https://gem5.atlassian.net/browse/GEM5-537 but this is X86 so I'm not sure. 
With SyscallAll + ExecAll and some patience most bugs can be found. Presumably 
new instructions are being run in an infinite loop, otherwise simulation would 
reach the end of time. So I would try to determine what that minimal loop is 
and why it won't exit.

From: Daniel Gerzhoy via gem5-users 
Sent: Wednesday, October 28, 2020 7:21 PM
To: gem5 users mailing list 
Cc: Daniel Gerzhoy 
Subject: [gem5-users] Re: SE Mode and Std::thread

Looks like this is related to this change:

https://gem5-review.googlesource.com/c/public/gem5/+/8184

I'm a bit behind develop because of custom changes and don't have this patch 
merged yet.
Cherry picking this might work, but merging would probably be the best 
solution, if time consuming.

Cheers,
Dan


On Tue, Oct 27, 2020 at 3:39 PM Daniel Gerzhoy 
mailto:daniel.gerz...@gmail.com>> wrote:
Hey all,

I'm running into a strange issue where threads are not spawning when launched 
with std::thread. It seems to work once, and then I try to launch again using a 
newly allocated thread pointer (after deleting the old one) and it hangs.

Minimal example:

void foo()
{
  printf("Foo alive from tid %lu\n", m5_cpu_id());
  //m5_cpu_id is a pseudo_instruction I added to return tc->cpuId()
}

void main()
{
  printf("Launching foo 1"\n);
  std::thread * mythread = new std::thread(foo,...);
  printf("Done Launching foo 1"\n);

  printf("Joining foo 1"\n);
  myThread->join();
  delete myThread;

  printf("Launching foo 2"\n);
  mythread = new std::thread(foo,...);
  printf("Done Launching foo 2"\n);

  printf("Joining foo 2"\n);
  myThread->join(); //< IT HANGS HERE
  printf("Done Everything!\n");
  delete myThread;
}

__

It works fine with TimingSimpleCPU, but then with DerivO3CPU I get the failure.

Output for  DerivO3CPU:
  Launch 1
  Done Launch 1
  I'm alive on tid 1
  Launch 2
  Done Launch 2

And there it Hangs.

FYI I am using apu_se.py, though with the above minimal example I've managed to 
reproduce the bug with no GPU code (nor even hipcc) involved.

I went back to the original code I found that showed std::thread could be used 
here:
https://www.gem5.org/documentation/learning_gem5/part3/running/

[image.png]

The comment there that -1 is required for SE mode, and then the subsequent 
comment about appeasing SE mode...

What exactly do those comments mean?

I'm going to keep debugging, but if anyone has any suggestions for debug flags 
that could be helpful it would be appreciated. (I'm using SyscallAll and going 
to investigate some of the syscalls SE mode ignores).

I'm wondering if maybe it is calling join() multiple times that might be the 
problem? Though unsure why at this point.

Thanks!

Dan
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[gem5-users] Re: How to use the new libm5.a

[Ciro Santilli via gem5-users]

BTW I pushed a patch exposing m5_exit_addr at: 
https://gem5-review.googlesource.com/c/public/gem5/+/36896

And after that this should work on KVM 
https://gem5-review.googlesource.com/c/public/gem5-resources/+/36677/1

From: Gabe Black via gem5-users 
Sent: Wednesday, October 28, 2020 10:48 PM
To: gem5 users mailing list 
Cc: Gabe Black 
Subject: [gem5-users] Re: How to use the new libm5.a

Hi Wenqi. You do still need to call map_m5_mem(), but as you found, now that 
there isn't one baked in call mechanism in the library you need to call the 
version of the function that will use the invocation mechanism you need. The 
header doesn't have declarations for them all, but if you declare your own with 
the same signature and an _addr suffix, you can call that and use the magic 
address based calling mechanism.

Gabe

On Wed, Oct 28, 2020 at 10:49 AM Wenqi Yin via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Hoa, Gabe,

Thanks for your help! But just want to confirm this: what I did in the past is 
calling map_m5_mem() in my code first and then call specific m5 functions, and 
it seems to work. The guest in running on KvmCPU.

When I am trying to do the same thing with the new libm5.a, it gave an 
exception (Illegal Instruction), however I haven’t looked into the error 
carefully yet, it may just because for some reason the lib is still trying to 
use the magic instruction interface. But before I proceed any further, just 
want to make sure I was using the correct approach to do this.

Best,
Wenqi

On Oct 26, 2020, at 23:30, Gabe Black via gem5-users 
mailto:gem5-users@gem5.org>> wrote:

Hi Wenqi. The updated libm5.a should be used in basically the same way as the 
old version. Just link against the library, include the header file, and call 
into the op you want using the normal function call syntax.

Hoa, the documentation you've linked to is a little out of date. How can it be 
updated?

Gabe

On Sun, Oct 25, 2020 at 9:31 PM Hoa Nguyen via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Wenqi,

We have some documentation about the new m5 utility here:
https://www.gem5.org/documentation/general_docs/m5ops/

The following link is an example of annotating PARSEC:
https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations

Regards,
Hoa Nguyen

On 10/25/20, wqyin--- via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
> Hello all,
>
> I noticed the util/m5 has big changes since this
> commit:26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am
> wondering how should I use this new interface/implementation to call
> m5ops in my program? Shall I also instantiate a default CallType and
> then use it to obtain the dispatch table and finally pass it to
> Command::run? Also is there any examples which use the new
> implementation to annotate any benchmarks running inside gem5? Thanks
>
> Best,
>
> Wenqi
>
>
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[gem5-users] How to use the memory address version of m5ops such as m5_exit_addr in an external C progam?

[Ciro Santilli via gem5-users]

Hi,

I have m5_exit working on a C program at 
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/simple/m5_exit.c#41
 but now I wanted to create one using the memory address version.

We already have a m5_exit_addr symbol defined in the library, but I couldn't 
find it exposed in any headers.

Do I just submit a patch adding all the symbols to include/gem5/m5ops.h, e.g. 
void m5_exit_addr(uint64_t ns_delay); ? Or is there already a way to access 
those that you know of?

If a patch is needed, any clues what would be the best approach? I see that 
currently the magic happens under:

struct DispatchTable
{
#define M5OP(name, func) __typeof__(&::name) name;
M5OP_FOREACH
#undef M5OP

and:

DispatchTable addr_dispatch = {
#define M5OP(name, func) .name = &::M5OP_MERGE_TOKENS(name, _addr),
M5OP_FOREACH
#undef M5OP

so I'm guessing I could add a similar M5OP_FOREACH + __typeof__ hack to 
include/gem5/m5ops.h to avoid repeating each function?

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[gem5-users] Re: track the write syscall in the kernel

[Ciro Santilli via gem5-users]

On full system you can also try to instrument the syscall function symbol, we 
do something analogous for panic detection: 
https://github.com/gem5/gem5/blob/f28b2e773f2ee97bf9c755b33aef9befc052d281/src/arch/arm/linux/fs_workload.cc#L207

From: ABD ALRHMAN ABO ALKHEEL via gem5-users 
Sent: Saturday, October 24, 2020 10:00 PM
To: gem5 users mailing list ; gem5-users 

Cc: ABD ALRHMAN ABO ALKHEEL 
Subject: [gem5-users] track the write syscall in the kernel

Hi All;

I want to track the write syscall in order to do some calculations on the 
written bytes. I just want to know what is the function that does write syscall 
function and how I can the written bytes from it.

Any help would be appreciated.

Thanks

https://github.com/torvalds/linux/blob/master/fs/read_write.c
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[gem5-users] Re: How to use the new libm5.a

[Ciro Santilli via gem5-users]

Hi Wenqi,

Have you tried: 
https://stackoverflow.com/questions/62757008/how-to-use-m5-in-gem5-20/62759204#62759204
 or has something changed since then too? Seems to work on develop just now.

From: wqyin--- via gem5-users 
Sent: Sunday, October 25, 2020 7:36 PM
To: gem5-users@gem5.org 
Cc: wq...@utexas.edu 
Subject: [gem5-users] How to use the new libm5.a


Hello all,

I noticed the util/m5 has big changes since this commit: 
26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am wondering how 
should I use this new interface/implementation to call m5ops in my program? 
Shall I also instantiate a default CallType and then use it to obtain the 
dispatch table and finally pass it to Command::run? Also is there any examples 
which use the new implementation to annotate any benchmarks running inside 
gem5? Thanks

Best,

Wenqi
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[gem5-users] Re: SE Mode crashing with multithread workload

[Ciro Santilli via gem5-users]

One thing to try, that program looks like it needs --num-cpus=5 as it spawns 4 
threads (so main + 4 total).

From: Bobby Bruce via gem5-users 
Sent: Thursday, October 15, 2020 10:13 PM
To: gem5 users mailing list 
Cc: Farhad Yusufali ; Bobby Bruce 

Subject: [gem5-users] Re: SE Mode crashing with multithread workload

Hey Farhad,

I've added a Jira ticket about this bug: 
https://gem5.atlassian.net/browse/GEM5-798.

I'm afraid to say we don't have a solution right now, but we suspect it may be 
similar to this bug: https://gem5.atlassian.net/browse/GEM5-332. You can see 
the comments on this bug for more information.

Now that it's on Jira, and a known bug in gem5, we hope we can get to the 
bottom of this and fix it in a future release. Keep track of the Jira ticket 
for progress on this issue.

We are sorry for the inconvenience this is causing you, but as far as I know, 
no one has a solution at this point in time.

Kind regards,
Bobby

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Thu, Oct 15, 2020 at 8:00 AM Farhad Yusufali via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi all,

Just following up on this. Any help would be appreciated!

Thanks,
Farhad


From: Farhad Yusufali
Sent: October 13, 2020 9:37 PM
To: gem5-users@gem5.org 
mailto:gem5-users@gem5.org>>
Subject: SE Mode crashing with multithread workload

Hi all,

My gem5 version is fa70478413e4650d0058cbfe81fd5ce362101994. I'm trying to run 
a multithreaded workload in SE mode, but it's crashing. Here is my very simple 
workload:


#include 

#include 

using namespace std;


int sum[4];


void* thread(void* sum) {

  for (int i = 0; i < 1000; i++)

*((int*)sum) += i;


  return 0;

}


int main() {

  sum[0] = sum[1] = sum[2] = sum[3] = 0;

  pthread_t threads[4];


  for (int tid = 0; tid < 4; tid++)

  pthread_create([tid], NULL, thread, [tid]);


  for (int tid = 0; tid < 4; tid++)

  pthread_join(threads[tid], NULL);


  cout << sum [0] << " " << sum[1] << " " << sum[2] << " " << sum[3] << endl;

  return 0;

}



When I run it with:

build/X86/gem5.opt --debug-flags=PseudoInst configs/example/se.py --cmd=./multi 
--num-cpus=4 --ruby --cpu-type=DerivO3CPU

I get:
panic: panic condition !clobber occurred: EmulationPageTable::allocate: addr 
0x7778d000 already mapped

I found an existing thread that discusses this but no update was posted: 
https://www.mail-archive.com/gem5-users@gem5.org/msg17926.html

Was this ever resolved?

Thanks,
Farhad
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[gem5-users] Re: Segmentation fault in gem5,

[Ciro Santilli via gem5-users]

* as for Jason's website, he is the sole moderator there, and can freely
delete any comments as he sees fit

On Sat, Oct 3, 2020 at 7:08 AM Ciro Santilli 
wrote:

> The gem5 PMC cannot control Stack Overflow and GItHub accounts of its
> contributors.
>
> If you want those avatars changed, please enter in contact with the
> respective moderators of those communities, e.g.:
>
> -
> https://meta.stackoverflow.com/questions/349131/users-political-display-name-triggering-government-action-against-users-who-vie
> - on GitHub, you can report users on their profile pages:
> https://github.com/cirosantilli
>
> If you have an URL in a gem5-controlled project, please provide it.
>
> The gem5 project could choose to ban users based on their political views,
> but I would not advise them to do so.
>
> Also keep in mind that this could cut both ways. E.g., what if the PMC
> decided to disallow contributions from people who support certain
> governments they disagree with?
>
>
> On Sat, Oct 3, 2020 at 2:32 AM Jason Lowe-Power via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi Tao,
>>
>> Thank you for bringing this to our attention. I will discuss this with
>> the other leaders of the community.
>>
>> Have a good weekend,
>>
>> Jason
>>
>>
>> On Fri, Oct 2, 2020, 6:15 PM Tao Zhang  wrote:
>>
>>> Hi Jason,
>>>
>>> Thanks a lot for posting the code of conduct.
>>>
>>> Being polite is indeed important and respect should be from both sides.
>>>
>>> I couldn't see Ciro's avatar in this email thread. However, if you
>>> search online, go to his github/stackoverflow profile page, or even browse
>>> your own homepage, you would see the avatar. Below is a snapshot from your
>>> homepage. I believe this is what the user 1154063264 referred to.
>>>
>>> Such an avatar is inappropriate and insulting. It definitely violates
>>> the code of conduct.
>>>
>>> Gem5 community is a place for academic and technical discussions. It
>>> should not be abused to express personal political opinions. Let's work
>>> together to keep it away from it.
>>>
>>> Hope you all have a good weekend.
>>>
>>> Thanks,
>>>
>>> [image: Screen Shot 2020-10-02 at 5.41.55 PM.png]
>>>
>>>
>>> -Tao
>>>
>>>
>>> On Fri, Oct 2, 2020 at 10:26 AM Jason Lowe-Power via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> Hi everyone,
>>>>
>>>> A few things:
>>>> 1. Being polite is important! We strive to make the gem5 community
>>>> inclusive and welcoming. :)
>>>> 2. Email can be very impersonal. Adding a greeting and a signature with
>>>> your name helps create a more welcoming environment!
>>>> 3. When asking questions on the mailing list, help us help you. You can
>>>> search the issues (
>>>> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues) to
>>>> see if anything similar has been
>>>> reported. If you can't find any similar issues, we welcome your
>>>> question, but it's most helpful when we can reproduce the problem :).
>>>> 4. The gem5 project has a code of conduct (
>>>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/CODE-OF-CONDUCT.md).
>>>> Specifically it says our standards include "Demonstrating empathy and
>>>> kindness toward other people" and "Being respectful of differing opinions,
>>>> viewpoints, and experiences." This document also details how to report a
>>>> violation of the community code of conduct.
>>>>
>>>> I hope everyone has a great weekend!
>>>>
>>>> Cheers,
>>>> Jason
>>>>
>>>> On Fri, Oct 2, 2020 at 1:25 AM Ciro Santilli via gem5-users <
>>>> gem5-users@gem5.org> wrote:
>>>>
>>>>> Can you provide the URL at which the avatar you refer to is showing?
>>>>>
>>>>> On Fri, Oct 2, 2020 at 6:55 AM 1154063264--- via gem5-users
>>>>>  wrote:
>>>>> >
>>>>> > First of all, I thank him for answering my question. However, as a
>>>>> Chinese, his profile picture does not respect our country. If my behavior
>>>>> affects other members of the community, I am sorry.
>>>>> > ___
>>>>> > gem5-users mailing list -- gem5-users@gem5.org
>>&

[gem5-users] Re: Segmentation fault in gem5,

[Ciro Santilli via gem5-users]

The gem5 PMC cannot control Stack Overflow and GItHub accounts of its
contributors.

If you want those avatars changed, please enter in contact with the
respective moderators of those communities, e.g.:

-
https://meta.stackoverflow.com/questions/349131/users-political-display-name-triggering-government-action-against-users-who-vie
- on GitHub, you can report users on their profile pages:
https://github.com/cirosantilli

If you have an URL in a gem5-controlled project, please provide it.

The gem5 project could choose to ban users based on their political views,
but I would not advise them to do so.

Also keep in mind that this could cut both ways. E.g., what if the PMC
decided to disallow contributions from people who support certain
governments they disagree with?


On Sat, Oct 3, 2020 at 2:32 AM Jason Lowe-Power via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Tao,
>
> Thank you for bringing this to our attention. I will discuss this with the
> other leaders of the community.
>
> Have a good weekend,
>
> Jason
>
>
> On Fri, Oct 2, 2020, 6:15 PM Tao Zhang  wrote:
>
>> Hi Jason,
>>
>> Thanks a lot for posting the code of conduct.
>>
>> Being polite is indeed important and respect should be from both sides.
>>
>> I couldn't see Ciro's avatar in this email thread. However, if you search
>> online, go to his github/stackoverflow profile page, or even browse your
>> own homepage, you would see the avatar. Below is a snapshot from your
>> homepage. I believe this is what the user 1154063264 referred to.
>>
>> Such an avatar is inappropriate and insulting. It definitely violates the
>> code of conduct.
>>
>> Gem5 community is a place for academic and technical discussions. It
>> should not be abused to express personal political opinions. Let's work
>> together to keep it away from it.
>>
>> Hope you all have a good weekend.
>>
>> Thanks,
>>
>> [image: Screen Shot 2020-10-02 at 5.41.55 PM.png]
>>
>>
>> -Tao
>>
>>
>> On Fri, Oct 2, 2020 at 10:26 AM Jason Lowe-Power via gem5-users <
>> gem5-users@gem5.org> wrote:
>>
>>> Hi everyone,
>>>
>>> A few things:
>>> 1. Being polite is important! We strive to make the gem5 community
>>> inclusive and welcoming. :)
>>> 2. Email can be very impersonal. Adding a greeting and a signature with
>>> your name helps create a more welcoming environment!
>>> 3. When asking questions on the mailing list, help us help you. You can
>>> search the issues (
>>> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues) to see
>>> if anything similar has been
>>> reported. If you can't find any similar issues, we welcome your
>>> question, but it's most helpful when we can reproduce the problem :).
>>> 4. The gem5 project has a code of conduct (
>>> https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/CODE-OF-CONDUCT.md).
>>> Specifically it says our standards include "Demonstrating empathy and
>>> kindness toward other people" and "Being respectful of differing opinions,
>>> viewpoints, and experiences." This document also details how to report a
>>> violation of the community code of conduct.
>>>
>>> I hope everyone has a great weekend!
>>>
>>> Cheers,
>>> Jason
>>>
>>> On Fri, Oct 2, 2020 at 1:25 AM Ciro Santilli via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> Can you provide the URL at which the avatar you refer to is showing?
>>>>
>>>> On Fri, Oct 2, 2020 at 6:55 AM 1154063264--- via gem5-users
>>>>  wrote:
>>>> >
>>>> > First of all, I thank him for answering my question. However, as a
>>>> Chinese, his profile picture does not respect our country. If my behavior
>>>> affects other members of the community, I am sorry.
>>>> > ___
>>>> > gem5-users mailing list -- gem5-users@gem5.org
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[gem5-users] Re: Segmentation fault in gem5,

[Ciro Santilli via gem5-users]

Can you provide the URL at which the avatar you refer to is showing?

On Fri, Oct 2, 2020 at 6:55 AM 1154063264--- via gem5-users
 wrote:
>
> First of all, I thank him for answering my question. However, as a Chinese, 
> his profile picture does not respect our country. If my behavior affects 
> other members of the community, I am sorry.
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[gem5-users] Re: Segmentation fault in gem5,

[Ciro Santilli via gem5-users]

Please provide fuller reproduction details.

On Thu, Oct 1, 2020 at 8:39 AM 1154063264--- via gem5-users
 wrote:
>
> I am trying to run parsec in MESI_Three_Level-gem5.opt for ARM architecture 
> in FS mode, but I am getting a segmentation fault.
>
> info: Entering event queue @ 25592214185500.  Starting simulation...
> info: Entering event queue @ 2559222830.  Starting simulation...
> gem5 has encountered a segmentation fault!
>
> --- BEGIN LIBC BACKTRACE ---
> ./build/ARM_MESI_Three_Level/gem5.opt(_Z15print_backtracev+0x30)[0x559591d5f160]
> ./build/ARM_MESI_Three_Level/gem5.opt(+0x1ed2b15)[0x559591d72b15]
> /lib/x86_64-linux-gnu/libpthread.so.0(+0x153c0)[0x7f047e58d3c0]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN9DataBlockaSERKS_+0x12)[0x559591e06e12]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller25u_writeDataFromL2ResponseERP11L1Cache_TBERP13L1Cache_Entrym+0xf2)[0x5595925d51c2]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller18doTransitionWorkerE13L1Cache_Event13L1Cache_StateRS1_RP11L1Cache_TBERP13L1Cache_Entrym+0xe93)[0x5595925e1713]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller12doTransitionE13L1Cache_EventP13L1Cache_EntryP11L1Cache_TBEm+0x591)[0x5595925e1ef1]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller6wakeupEv+0x9c3)[0x5595925e48e3]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10EventQueue10serviceOneEv+0xb9)[0x559591d67159]
> ./build/ARM_MESI_Three_Level/gem5.opt(_Z9doSimLoopP10EventQueue+0xf8)[0x559591d87dc8]
> ./build/ARM_MESI_Three_Level/gem5.opt(_Z8simulatem+0xaed)[0x559591d88bbd]
> ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10RubySystem12memWritebackEv+0xa29)[0x559590b79629]
> ./build/ARM_MESI_Three_Level/gem5.opt(+0x25b8df2)[0x559592458df2]
> ./build/ARM_MESI_Three_Level/gem5.opt(+0x1f3d899)[0x559591ddd899]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x9701)[0x7f047e6b3381]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6e76)[0x7f047e6b0af6]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39]
> /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFlags+0x76)[0x7f047e682846]
> ./build/ARM_MESI_Three_Level/gem5.opt(_Z6m5MainiPPc+0x8b)[0x559591d70a8b]
> --- END LIBC BACKTRACE ---
> Segmentation fault
>
> What can be done here to resolve this?
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[gem5-users] Re: Tracking read()/write() system calls in gem5

[Ciro Santilli via gem5-users]

Also have a look at --debug-flags SyscallBase,SyscallVerbose


On Tue, Sep 22, 2020 at 8:26 PM ABD ALRHMAN ABO ALKHEEL via gem5-users
 wrote:
>
> Hi All, can I track the read()/write() system calls in GEM5 in SE mode? If 
> so, how I can do that? Any help would be appreciated. Thanks
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[gem5-users] Re: Help in Understanding "Simple.py" Config File

[Ciro Santilli via gem5-users]

This gives some pointers on the SimObject Python/C++ interaction which
might clarify things:
https://stackoverflow.com/questions/62969566/attributes-of-system-object-in-gem5/62970092#62970092

On Tue, Aug 25, 2020 at 2:21 PM Dwaipayan Ray via gem5-users
 wrote:
>
> Hello Everyone,
>
> I am very new to gem5 and currently practicing/understanding the part-1 of 
> "learning gem5" documentation.
>
> I am curious to know the following
>
> Which components can be included inside the system? I mean like system.cpu, 
> from where can I find the list of these modules?
> What is the valid set of parameters that can be assigned? E.g., it is 
> mentioned that system.mem_ctrl = DDR3_1600_8x8() can be changed to DDR4. So, 
> how to be aware of these parameters/options?
>
> Please respond and provide me the idea.
>
> Thanks in advance.
> Ray
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[gem5-users] Re: [ARM system] Question about the cleassic cache system

[Ciro Santilli via gem5-users]

I'm not sure about the cache hierarchy issue.

But about Ruby support, I don't think there's any known ARM specific problem, 
and ARM contributors have been specifically pushing Ruby recently, see e.g. see 
Tiago's CHI announcement: https://www.gem5.org/2020/05/29/flexible-cache.html

From: chenboya via gem5-users 
Sent: Friday, August 21, 2020 10:50 AM
To: gem5-users@gem5.org 
Cc: chenboya 
Subject: [gem5-users] [ARM system] Question about the cleassic cache system


Hi, ALL

I'm doing some design space exploration work using GEM5.
My work is exploring the different cache structures, using ARM cores, classic 
cache structure, and use parsec-3.0 to simulate the multi-core performance.
My system has 4-level caches, every level using L2XBar to connect. Use big 
little clusters, every cluster has the L2 cache shared by cores in the cluster.

Now I meet some problems in the cache structure as below:

1. If I connect all the clusters to one L3 cache then connect to one L4 cache, 
then the full system run is OK.

2. If I connect big clusters directly to L4 cache, other clusters connect to 
one L3 cache then connect to L4 cache, will see the error below (in 
system.terminal):

/home/root/parsec-3.0
 [0.831546] Unable to handle kernel paging request at virtual address 
aaecd674a901
 [0.831563] Unable to handle kernel paging request at virtual address 
aaecde551e41
 [0.831573] Unable to handle kernel paging request at virtual address 
aaecde527e41

3. If I connect big clusters to one L3, other clusters to another L3, and these 
two L3 caches connect to L4 cache, will have SAME error.

If change all cores to Atomic CPU, will not have the page fault error.

All the 3 experiments use same image (the aarch64-ubuntu-trusty-headless.img 
add parsec), and use automatically generated dtb file.
When instantiation, the 3 structures can be generated successfully.

So are there any limits about classic mode memory system for ARM? For example, 
cannot support more than one L3 caches or asymmetry hierarchies?
Should I using Ruby to replace it?

In Andreas Hansson's 2015 slides, he said Ruby has some compatibility problems 
for ARM.
FSConfig.py also warns that Ruby on ARM is not working properly yet. Has those 
problems solved now?


-Original Message-
From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org]
Sent: 2020年8月21日 8:23
To: gem5-users@gem5.org
Subject: gem5-users Digest, Vol 169, Issue 52

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gem5-users@gem5.org

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When replying, please edit your Subject line so it is more specific than "Re: 
Contents of gem5-users digest..."

Today's Topics:

   1. Re: KVM does not work  (chenboya)
   2. Re: Functional read failed while using pthread lock in program
  (Jason Lowe-Power)
   3. Packet request send directly to memory without searching in cache
  (Muhammad Aamir)
   4. issues in FS mode with TimingSimpleCPU+Multicore (JASPINDER KAUR)


--

Date: Thu, 20 Aug 2020 14:55:05 +
From: chenboya 
Subject: [gem5-users] Re: KVM does not work
To: "gem5-users@gem5.org" 
Message-ID: 
Content-Type: text/plain; charset="utf-8"

There are some GIC issues about running the KVM mode, fortunately an engineer 
had given the solution.
Here are some discussions about the KVM mode for ARM.

https://gem5.atlassian.net/browse/GEM5-547


-Original Message-
From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org]
Sent: 2020年8月12日 9:46
To: gem5-users@gem5.org
Subject: gem5-users Digest, Vol 169, Issue 31

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Today's Topics:

   1. KVM does not work (毛允飞)
   2. Re: KVM does not work (Giacomo Travaglini)


--

Date: Wed, 12 Aug 2020 16:40:48 +0800
From: 毛允飞 
Subject: [gem5-users] KVM does not work
To: gem5-users@gem5.org
Message-ID:

Content-Type: multipart/alternative;
boundary="c0216705acaa2553"

--c0216705acaa2553
Content-Type: text/plain; charset="UTF-8"

Hi All
I run the fs_bigLITTLE.py script in gem5, but there is no information in the 
m5term console. I don't know what went wrong,

INFO:
Global frequency set at 1 ticks per second
info: Simulated platform: VExpress_GEM5_V1
info: kernel located at:

[gem5-users] Re: Functional read failed while using pthread lock in program

[Ciro Santilli via gem5-users]

Functional reads in Ruby SE are a known and hard to solve problem, see
https://gem5.atlassian.net/browse/GEM5-675 and
https://gem5.atlassian.net/browse/GEM5-676

On Tue, Aug 18, 2020 at 6:33 PM VIPIN PATEL via gem5-users
 wrote:
>
> Hi All,
>
> I using the GEM5 simulator to collect statistics of a micro-benchmark 
> program. I am encountering the functional read access failed for address 
> "0x".
>
> I have attached the source file of the micro-benchmark program. The 
> simulation is running fine for the case "1" and "4" in the switch construct. 
> The error is encountered for the cases "2" and "3" while I am using pthread 
> locks.
>
> I am using the MESI_Two_Level protocol with 4 core configuration( private L1I 
> and L1D cache for each core and shared L2 cache) in SE mode.
>
> I have read the discussion on google group 
> "https://groups.google.com/u/1/g/gem5-gpu-dev/c/Wt43jSYYXag;
> and can infer the issue is generated when we have multiple copies of a block 
> in our system (might be in the transient state) and we tried to perform a 
> store or load to it.
>
> Can you point out the way to fix this?
> Is pthread lock not supported in the gem5? Does the current release of gem5 
> provide a workaround for this?
>
> Any help would be highly appreciated. Thanks in advance.
>
> Regards,
> Vipin
> Research Scholar
> IIT Kanpur
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[gem5-users] Re: Memory Addresses in Gem5

[Ciro Santilli via gem5-users]

On Sat, Aug 15, 2020 at 9:54 PM ABD ALRHMAN ABO ALKHEEL
 wrote:
>
> Hi Ciro,
>
> Could you tell me where can i find the file that does an ifetch for 
> AtomicsimpleCPU in gem5?
>

https://github.com/gem5/gem5/blob/fa70478413e4650d0058cbfe81fd5ce362101994/src/cpu/simple/atomic.cc#L673
up to sendFetch below (find Atomic file source and grep :-) ) Some
notes also under:
https://cirosantilli.com/linux-kernel-module-cheat/#gem5-packet-vs-request


> Also, How to print the data from the packet (I assumed the loaded data is 
> stored in the pkt).
> should I use
> pkt->getRaw()
> or
> pkt->getLE()
> or
> pkt->getBE()
> or
> pkt->setData()
> or
> pkt->writeData()
>

Have a look at the source under Eclipse :-) all of those get the
packet data with small variations, but it is raw binary.

To see it as hex you need to convert binary to ASCII hex first. I want
to push a simple patch for this in the near future, but you can do it
manually easily too for now:
https://stackoverflow.com/a/27173017/895245

> Thanks
>



> 
> From: Ciro Santilli 
> Sent: Wednesday, August 12, 2020 7:18 AM
> To: gem5 users mailing list 
> Cc: Ahmed, Md Rubel ; ABD ALRHMAN ABO ALKHEEL 
> 
> Subject: Re: [gem5-users] Re: Memory Addresses in Gem5
>
> I recommend that you have a look at the source of how AtomicSimpleCPU
> does an ifetch under Eclipse. It should be easy to understand
> everything quickly from there.
>
> The Packet address is physical (which notably what caches and DRAM
> work on), just have a look at the constructor of packet:
>
> Packet(const RequestPtr &_req, MemCmd _cmd)
> :  cmd(_cmd), id((PacketId)_req.get()), req(_req),
>data(nullptr), addr(0), _isSecure(false), size(0),
>_qosValue(0), headerDelay(0), snoopDelay(0),
>payloadDelay(0), senderState(NULL)
> {
> if (req->hasPaddr()) {
> addr = req->getPaddr();
>
> So you have to do translation before. Translation sets the physical
> address on the Request, which contains both _paddr and _vaddr fields.
>
> Another option is to have a look at how some of the memory tests are doing it.
>
> On Wed, Aug 12, 2020 at 1:55 AM ABD ALRHMAN ABO ALKHEEL via gem5-users
>  wrote:
> >
> > Hi,
> >
> > Thank you for your email.
> >
> > Do you have any idea how to construct a packet with a request to read from 
> > the memory address? For instance, let us assume that the address that I 
> > want to read the data from it is (0x2345),  I want to read the 256 bytes of 
> > this address (0x2300-0x23ff)? I want to do that for debugging like this 
> > https://www.gem5.org/_pages/static/scripts/part2/memoryobject/simple_memobj.cc.
> >
> > Any help would be appreciated.
> >
> > Thanks
> >
> > 
> > From: Ahmed, Md Rubel via gem5-users 
> > Sent: Wednesday, August 12, 2020 12:44 AM
> > To: gem5 users mailing list 
> > Cc: Ahmed, Md Rubel 
> > Subject: [gem5-users] Re: Memory Addresses in Gem5
> >
> > Hi,
> >
> > pkt->getAddr()  returns memory address. pkt->print() also returns block 
> > address and offset.
> >
> > Thanks
> > 
> > From: ABD ALRHMAN ABO ALKHEEL via gem5-users 
> > Sent: Tuesday, August 11, 2020 6:32 PM
> > To: gem5 users mailing list ; gem5-users 
> > 
> > Cc: ABD ALRHMAN ABO ALKHEEL 
> > Subject: [gem5-users] Memory Addresses in Gem5
> >
> > Hi All,
> >
> > Does the packet in gem5 have the memory address? for example, does this 
> > pkt->getAddr() return the memory address or not? If so, is that address 
> > physical or virtual?
> >
> > Thanks
> >
> > [EXTERNAL EMAIL] DO NOT CLICK links or attachments unless you recognize the 
> > sender and know the content is safe.
> >
> > ___
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[gem5-users] Re: Restoring from checkpoint in gem5 x86 FS

[Ciro Santilli via gem5-users]

On Sat, Aug 15, 2020 at 6:44 PM Chandrahas Tirumalasetty via
gem5-users  wrote:
>
> Hello,
> I am trying to restore from a checkpoint (created with AtomicSimpleCPU)  with 
> cpu-type DerivO3CPU in my gem5 setup. I have two questions mainly
>
> Is it allowed to create a checkpoint with AtomicSimpleCPU and restore with 
> DerivO3CPU?.

See also:

- 
https://stackoverflow.com/questions/60876259/which-system-characteristics-such-as-number-of-cores-of-cache-configurations-can/60876260#60876260
- 
https://stackoverflow.com/questions/49011096/how-to-switch-cpu-models-in-gem5-after-restoring-a-checkpoint-and-then-observe-t
have a play with --cpu-type and --restore-with-cpu

> The mem_mode which is atomic when using AtomicSimpleCPU seemed to same even 
> after I restore with DerivO3CPU. But my assumption is that after restoring, 
> the mem_mode should change to timing?. Please someone clarify.
>

It should, how did you observe it being atomic? I'd expect DerivO3CPU
not to ever make atomic requests (like Atomic only makes atomic
requests).

>
>
> --
> Chandrahas Tirumalasetty
> PhD student at Dept. of ECE, TAMU
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[gem5-users] Re: Memory Addresses in Gem5

[Ciro Santilli via gem5-users]

I recommend that you have a look at the source of how AtomicSimpleCPU
does an ifetch under Eclipse. It should be easy to understand
everything quickly from there.

The Packet address is physical (which notably what caches and DRAM
work on), just have a look at the constructor of packet:

Packet(const RequestPtr &_req, MemCmd _cmd)
:  cmd(_cmd), id((PacketId)_req.get()), req(_req),
   data(nullptr), addr(0), _isSecure(false), size(0),
   _qosValue(0), headerDelay(0), snoopDelay(0),
   payloadDelay(0), senderState(NULL)
{
if (req->hasPaddr()) {
addr = req->getPaddr();

So you have to do translation before. Translation sets the physical
address on the Request, which contains both _paddr and _vaddr fields.

Another option is to have a look at how some of the memory tests are doing it.

On Wed, Aug 12, 2020 at 1:55 AM ABD ALRHMAN ABO ALKHEEL via gem5-users
 wrote:
>
> Hi,
>
> Thank you for your email.
>
> Do you have any idea how to construct a packet with a request to read from 
> the memory address? For instance, let us assume that the address that I want 
> to read the data from it is (0x2345),  I want to read the 256 bytes of this 
> address (0x2300-0x23ff)? I want to do that for debugging like this 
> https://www.gem5.org/_pages/static/scripts/part2/memoryobject/simple_memobj.cc.
>
> Any help would be appreciated.
>
> Thanks
>
> 
> From: Ahmed, Md Rubel via gem5-users 
> Sent: Wednesday, August 12, 2020 12:44 AM
> To: gem5 users mailing list 
> Cc: Ahmed, Md Rubel 
> Subject: [gem5-users] Re: Memory Addresses in Gem5
>
> Hi,
>
> pkt->getAddr()  returns memory address. pkt->print() also returns block 
> address and offset.
>
> Thanks
> 
> From: ABD ALRHMAN ABO ALKHEEL via gem5-users 
> Sent: Tuesday, August 11, 2020 6:32 PM
> To: gem5 users mailing list ; gem5-users 
> 
> Cc: ABD ALRHMAN ABO ALKHEEL 
> Subject: [gem5-users] Memory Addresses in Gem5
>
> Hi All,
>
> Does the packet in gem5 have the memory address? for example, does this 
> pkt->getAddr() return the memory address or not? If so, is that address 
> physical or virtual?
>
> Thanks
>
> [EXTERNAL EMAIL] DO NOT CLICK links or attachments unless you recognize the 
> sender and know the content is safe.
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[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Ciro Santilli via gem5-users]

We have to understand the root cause to be sure, it often happens that memory 
errors are just hidden by random changes. Let's move all discussion to that 
ticket. I've started dumping some logs for it and linked to the ticket BTW.

From: Sebastian Block 
Sent: Tuesday, August 11, 2020 11:37 AM
To: gem5-users@gem5.org ; Ciro Santilli 

Cc: nd 
Subject: Re: [gem5-users] Error only occurs with higher number of clusters and 
cpus

The error seems to relate to the kernel used. I build a new kernel (gem5: 
Building ARM 
Kernel)
 and now I'm able to simulate even more cpus. The kernel i used is the v4.14 
version.


Am Freitag, 7. August 2020, 20:08:10 MESZ hat Sebastian Block 
 Folgendes geschrieben:



Thank you very much. I will give Ruby a try.
Am Freitag, 7. August 2020, 16:41:12 MESZ hat Ciro Santilli 
 Folgendes geschrieben:


It might be the same as: https://gem5.atlassian.net/browse/GEM5-711 I want to 
investigate that soon hopefully.

If you try Ruby and it fails, please open a separate bug, we want it to work as 
well 

From: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus

Hi all,

My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.
Simulating in atomic mode always works.
While simulating less then 6 cpus works perfectly fine in timing mode, with 
more then 6 the simulation crashes with the error:

panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidate
Memory Usage: 9072952 KBytes
Program aborted at tick 175141645000
--- BEGIN LIBC BACKTRACE ---

At the moment the project uses classic caches. Private L1 and shared L2 caches. 
I didn't test it with L3 caches as the simulation crashes sometimes.
Is it possible that the error occurs because of the classic caches and cache 
coherence?
Might the error vanish when using Ruby?
An L3 cache should also be implemented. Is it difficult to do that in Ruby?

Thank you very much for your help.

Best regards
Sebastian

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[gem5-users] Re: Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

[Ciro Santilli via gem5-users]

Hi Yichao,

How are you counting the instructions? --debug-flags ExecAll? If so, are you 
excluding pseudo instructions with --debug-flags ExecAll,ExecMicro?

From: Liyichao via gem5-users 
Sent: Monday, August 10, 2020 5:29 AM
To: gem5-users@gem5.org 
Cc: Liyichao 
Subject: [gem5-users] 答复: Supplementing experiment Data///答复: How to make 
scheduleInstStop() function to stop simulate at an accurate expected 
instructions counts for one core KVM/ATOMIC/O3 CPU simulation?


Hi All:

 Are there any experts who can help me to explain the features of the 
scheduleInstStop() function?





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发件人: Liyichao
发送时间: 2020年8月7日 12:12
收件人: 'gem5-users@gem5.org' 
主题: Supplementing experiment Data///答复: How to make scheduleInstStop() function 
to stop simulate at an accurate expected instructions counts for one core 
KVM/ATOMIC/O3 CPU simulation?







Hi All:



I use the scheduleInstStop() function to let the m5.simulate() stop at a point 
instrutions as my ROI start, for example: 1(100M) instrutions, but when 
the simulate stop, I print the instructions from last start simulation to the 
end, the count always exceed my specified instrutions(100M), like 100423403, 
about 0.4% exceeded. If I set to 137579444 in O3 cpu, when simulation stop, 
totalInsts() print 121264766,about 12% instruction number error.



The more detail the CPU is or the less expected instruction we set to 
scheduleInstStop() , the more error rate the result is.

Can the scheduleInstStop() function to stop simulate at an accurate instrutions 
count?



Below is my experiment data:

SP means each ROI segment number

WT means weight each SP

KVM FF INSTS means expected fastforward instrutions  set to shceduleInstsStop 
in KVM CPU and KVM FF INSTS REAL means actural instructions when simulation 
stopped.

Thes same as DETAIL WARMUP INSTS and DETAIL WARMUP INSTS REAL, ROI START REAL

DETAIL SIM INSTS REAL means actural instructions when simulation stopped.



SP

ROI START INSTS

ROI INSTS

WT

GEM5 CPU time(s)

KVM FF INSTS REAL

KVM FF INSTS

KVM FF ERROR

DETAIL WARMUP INSTS REAL

DETAIL WARMUP INSTS

DETAIL WARMUP ERROR  RATE

ROI START REAL

ROI START ERROR

ROI START ERROR RATE

DETAIL SIM INSTS REAL

ROI ERROR

ROI ERROR RATE

253

10178192697

7961215

0.0831

235.37

10168198363

10168192697

0.56%

11769096

1000

17.69%

10179967459

1774762

0.01744%

9765795

1804580

22.67%

489

14993215251

28956263

0.0807

480.69

14985233613

14983215251

0.013471%

12670891

1000

26.71%

14997904504

4689253

0.03128%

31630388

2674125

9.24%

745

20961513684

7952028

0.0831

366.16

20951519275

20951513684

0.27%

10930605

1000

9.31%

20962449880

936196

0.00447%

9196796

1244768

15.65%

747

20985389544

7913399

0.0831

368.9

20976588014

20975389544

0.005714%

13508368

1000

35.08%

20990096382

4706838

0.02243%

8729639

816240

10.31%

1535

36747557633

71903019

0.0489

852.12

36737563780

36737557633

0.17%

13915280

1000

39.15%

36751479060

3921427

0.01067%

76114831

4211812

5.86%

1576

39801482033

72581100

0.0489

986.37

39791620332

39791482033

0.000348%

13898089

1000

38.98%

39805518421

4036388

0.01014%

76712281

4131181

5.69%

1630

41397216547

7969257

0.0831

576.6

41387222182

41387216547

0.14%

14108619

1000

41.09%

41401330801

4114254

0.00994%

12213236

4243979

53.25%

1678

41875758899

7945777

0.0831

578.1

41871459914

41865758899

0.013617%

14214926

1000

42.15%

41885674840

9915941

0.02368%

12108036

4162259

52.38%

1884

46344067975

28927369

0.0807

845.82

46334073500

46334067975

0.12%

11344254

1000

13.44%

46345417754

1349779

0.00291%

31850077

2922708

10.10%

1919

47342402174

28905117

0.0807

805.16

47332436420

47332402174

0.72%

12802266

1000

28.02%

47345238686

2836512

0.00599%

31773934

2868817

9.92%

1926

47542229035

28886691

0.0807

787.53

47534320414

47532229035

0.004400%

12709174

1000

27.09%

47547029588

4800553

0.01010%

31731786

2845095

9.85%

[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Ciro Santilli via gem5-users]

It might be the same as: https://gem5.atlassian.net/browse/GEM5-711 I want to 
investigate that soon hopefully.

If you try Ruby and it fails, please open a separate bug, we want it to work as 
well 

From: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus

Hi all,

My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.
Simulating in atomic mode always works.
While simulating less then 6 cpus works perfectly fine in timing mode, with 
more then 6 the simulation crashes with the error:

panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidate
Memory Usage: 9072952 KBytes
Program aborted at tick 175141645000
--- BEGIN LIBC BACKTRACE ---

At the moment the project uses classic caches. Private L1 and shared L2 caches. 
I didn't test it with L3 caches as the simulation crashes sometimes.
Is it possible that the error occurs because of the classic caches and cache 
coherence?
Might the error vanish when using Ruby?
An L3 cache should also be implemented. Is it difficult to do that in Ruby?

Thank you very much for your help.

Best regards
Sebastian

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[gem5-users] Re: gem5 aborted when increase mem-size in FS mode

[Ciro Santilli via gem5-users]

Does it crash immediately? If so, provide to us and look at the
backtrace to try and determine which allocation fails. If that doesn't
help, you can also try techniques mentioned at:
https://stackoverflow.com/questions/6261201/how-to-find-memory-leak-in-a-c-code-project/57877190#57877190

On Thu, Aug 6, 2020 at 2:44 AM syf1997--- via gem5-users
 wrote:
>
> Hi Jason,
>
> Thank you for your reply. I am using the latest version 20.3. I have just 
> double-checked the memory usage info of gem5. It showed that memory usage is 
> about 10GB, while I run gem5 on a 128GB memory server. I don't think my 
> system ran out of memory. I am confused about it.
>
> Yifan Song
>
> -原始邮件-
> 发件人:"Jason Lowe-Power via gem5-users" 
> 发送时间:2020-08-06 01:13:59 (星期四)
> 收件人: "gem5 users mailing list" 
> 抄送: syf1...@mail.ustc.edu.cn, "Jason Lowe-Power" 
> 主题: [gem5-users] Re: gem5 aborted when increase mem-size in FS mode
>
> Hi Yifan,
>
> Is it possible that your system is running out of memory? It's possible this 
> is a gem5 bug (what version are you using?), but I haven't heard of this 
> issue before.
>
> Cheers,
> Jason
>
> On Wed, Aug 5, 2020 at 1:34 AM syf1997--- via gem5-users 
>  wrote:
>>
>> Hi all,
>>
>> I am trying to run my own program (training a tiny vgg16 CNN model using 
>> CPU) in FS mode. I have created my own disk image and installed python3 and 
>> pytorch on it. My command line is as bellow：
>>
>> build/X86/gem5.opt configs/example/fs.py --kernel=binary/vmlinux-5.2.4 
>> --disk-image=disk/linux-x86.img -n 2 --caches --l2cache --mem-size=4GB
>>
>> If I set the mem-size small, like 512MB, 1GB, 2GB, my program could run 
>> normally but would fail due to the small memory. On the other hand, if I 
>> increase the mem-size, my program could not run and gem5 aborted (core 
>> dump). Could anyone give me some advice? Thanks.
>>
>> Best regards,
>>
>> Yifan
>>
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[gem5-users] Re: Current status of gem5 capabilities regarding multicores full system simulation

[Ciro Santilli via gem5-users]

Welcome back Nathanael!

We put great importance on ARM Linux kernel boot, and we try to make it so that 
it either works or at least we have a bug report for it.

I reproduce the problem with VExpress_GEM5_V2 but not VExpress_GEM5_V1, opening 
a but for V2 at: https://gem5.atlassian.net/browse/GEM5-706

Besides that, some notes:

O3_ARM_v7a_3: does not sound like a good idea for aarch64 since v7 in name, not 
sure it has all functional units required.

--dtb-file is not needed anymore unless you are hacking the DTB manually. Just 
remove that option to use DTB auto-generation which is more likely to work.

The newly setup nightlies (thanks Bobby!) contain a two core O3 test that 
passed yesterday: 
https://jenkins.gem5.org/job/Nightly/17/artifact/tests/.testing-results/results.xml



From: Nathanael Premillieu via gem5-users 
Sent: Monday, July 27, 2020 6:52 PM
To: gem5-users@gem5.org 
Cc: Nathanael Premillieu 
Subject: [gem5-users] Current status of gem5 capabilities regarding multicores 
full system simulation


Hi all,



After a few years away, I’m back to gem5. I have to say a lot of things have 
changed, for the better, thank you all!



I’m trying to assess what is the current state of gem5 regarding simulating 
configurations with multiples cores in a full system environment with the 
different cpu models.

Especially with the Arm architecture and the classic memory model in a full 
system simulation using the O3CPU model. And what happens if you add SMT on top 
of that.

I’ve looked at this page: https://www.gem5.org/documentation/benchmark_status/, 
but from what I can infer, those results are only valid for X86.



I’ve tried for example to boot linux (using the kernel provided here: 
http://dist.gem5.org/dist/current/arm/aarch-system-201901106.tar.bz2 and the 
disk image here: 
http://dist.gem5.org/dist/current/arm/disks/aarch64-ubuntu-trusty-headless.img.bz2)
 but without success.

But I don’t know if I’m doing something wrong or if I’m trying to do something 
that is unsupported for the moment.



I’m using gem5 version v20.0.0.2 and here is my command line:

$ build/ARM/gem5.opt configs/example/fs.py --kernel=binaries/vmlinux.arm64 
--machine-type=VExpress_GEM5_V2 
--dtb-file=system/arm/dt/armv8_gem5_v2_4cpu.dtb 
--disk-image=aarch64-ubuntu-trusty-headless.img --cpu-type=O3_ARM_v7a_3 
--caches --l2cache -n 4



I get the following error: Assertion `reqLookupResult.it->first == line_addr' 
failed.



Global frequency set at 1 ticks per second

warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (512 Mbytes)

info: kernel located at: binaries/vmlinux.arm64

warn: Highest ARM exception-level set to AArch32 but the workload is for 
AArch64. Assuming you wanted these to match.

system.vncserver: Listening for connections on port 5900

system.terminal: Listening for connections on port 3456

system.realview.uart1.device: Listening for connections on port 3457

system.realview.uart2.device: Listening for connections on port 3458

system.realview.uart3.device: Listening for connections on port 3459

0: system.remote_gdb: listening for remote gdb on port 7000

0: system.remote_gdb: listening for remote gdb on port 7001

0: system.remote_gdb: listening for remote gdb on port 7002

0: system.remote_gdb: listening for remote gdb on port 7003

info: Using bootloader at address 0x10

info: Using kernel entry physical address at 0x8008

info: Loading DTB file: system/arm/dt/armv8_gem5_v2_4cpu.dtb at address 
0x8800

 REAL SIMULATION 

warn: Existing EnergyCtrl, but no enabled DVFSHandler found.

info: Entering event queue @ 0.  Starting simulation...

warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0

warn:   instruction 'csdb' unimplemented

warn: Gicv3Distributor::write(): setting ARE to 0 is not supported!

gem5.opt: build/ARM/mem/snoop_filter.cc:165: void 
SnoopFilter::finishRequest(bool, Addr, bool): Assertion 
`reqLookupResult.it->first == line_addr' failed.

Program aborted at tick 12946004000



I get the same error using only one core (–n 1). I’ve also tried with the 
current state of the develop branch (commit v20.0.0.3-290-gcef72adab) and I get 
the same error.



Thanks,

Nathanael
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[gem5-users] Re: Fwd: How calculate power in gem5?

[Ciro Santilli via gem5-users]

Hi, is this different from:
https://www.mail-archive.com/gem5-users@gem5.org/msg18093.html If not,
please don't repost so soon, and ping previous thread instead. I'm
preparing to learn/ask around if no one replies.

On Sun, Jul 26, 2020 at 9:08 AM faridehziaee via gem5-users
 wrote:
>
>
>
> Hi All,
>
> In my project , I need to compute power and performance from output of gem5 
> with dvfs.
> How can I  do them or which tools can I use for them?
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[gem5-users] Re: Resume checkpoint generation from another checkpoint

[Ciro Santilli via gem5-users]

Why wouldn't it work :-)? Have you tried/how it fails? How did
execution terminate Ctrl + C or a guest event?

On Sat, Jul 25, 2020 at 7:13 AM as3mx--- via gem5-users
 wrote:
>
> Hi
>
> I wanted to know if it is possible to resume the checkpoint generation from 
> the last checkpoint generated. For example, assume we have a simpoint.txt 
> file which has 6 simpoints. Due to some reason, the execution terminates and 
> only 4 checkpoints are generated. Is it possible to restore from checkpoint 4 
> and generate checkpoints 5 and 6 instead of executing from the beginning?
>
> Thanks
> ___
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[gem5-users] Re: Need help in compiling the kernel

[Ciro Santilli via gem5-users]

To compile kernel see e.g.: 
https://raspberrypi.stackexchange.com/questions/192/how-do-i-cross-compile-the-kernel-on-a-ubuntu-host
 but replace arm with arm64 and the compile with the aarch64 one for 64-bit 
arm. All other ISAs are analogous.

The ARM configs are in-tree of the official arm gem5 kernel fork e.g.: 
https://gem5.googlesource.com/arm/linux/+/refs/heads/gem5/v4.15/arch/arm64/configs/gem5_defconfig

The patch at https://www.mail-archive.com/gem5-users@gem5.org/msg06169.html 
contains changes to arch/arm, so it will only work for arm. You could try to 
port. The question then is why it wasn't merged. Maybe CC. Andreas Sandberg.

Possibly related Q to your request: 
https://stackoverflow.com/questions/54133479/accessing-logical-software-thread-id-in-gem5


From: Saideepak Bejawada via gem5-users 
Sent: Wednesday, July 22, 2020 9:32 AM
To: gem5-users@gem5.org 
Cc: Saideepak Bejawada 
Subject: [gem5-users] Need help in compiling the kernel

Hi all,

I am trying to get the PID information from Processinfo: :pid . I got stuck at 
the panic which says 'thread info not compiled into kernel'. I have been 
looking into older posts regarding this.

https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ/#MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ
https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG/#U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG

They say we have to recompile the kernel adding the thread info structure into 
it. I have never compiled a kernel before. Can anyone help me on how to do this?

I found a patch here for the kernel:
https://www.mail-archive.com/gem5-users@gem5.org/msg06169.html
It says it is for ARM. Will the kernel patches be specific for ISAs? Also, how 
can I apply this patch?
Any comments are welcome.
Thanks for your time.

Thanks,
Saideepak.
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[gem5-users] Re: How to use eclipse or any other IDE to debug user code in GEM5

[Ciro Santilli via gem5-users]

https://stackoverflow.com/questions/61656709/how-to-setup-eclipse-ide-for-gem5-development

On Mon, Jul 20, 2020 at 12:25 PM Muhammad Aamir via gem5-users
 wrote:
>
> Hi everyone,
>
> I have been following this 
> tutorial(http://www.m5sim.org/wiki/images/b/b2/Tsinghua%27s_Presentation_for_gem5_Workshop_2012.pdf)
>  to integrate GEM5 to the eclipse debugger but I am not able to do it, maybe 
> because the tutorial is quite old.
>
> It would be really helpful if someone could teach or elaborate the steps on 
> how to configure an IDE to use with GEM5. Or send me a link on how to 
> integrate it.
>
> Thanks.
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[gem5-users] Re: Benchmark terminating early

[Ciro Santilli via gem5-users]

SE I suppose? It seems that the benchmark ends normally with an exit
syscall, I would start by looking at --debug-flags SyscallBase to
double check that.

Then if that is the case, the only explanation is that some value is
getting corrupted somewhere due to a gem5 bug. So I would try to: 1)
compare traces from an Atomic and O3 run 2) GDB into the GDB stub to
see what leads to that exit being called.


On Fri, Jul 10, 2020 at 5:15 PM Alex Freij via gem5-users
 wrote:
>
> Hello all,
>
> I'm running a single core X86 o3 sim with SPEC2006 benchmarks, and have run 
> into a scenario where some of the benchmarks are terminating early. Using the 
> "DRAM" debug flag, I see this message upon termination:
>
> Exiting @ tick 67067500 because exiting with last active thread context
> 67067500: system.mem_ctrls_0: Computing stats due to a dump callback
> 67067500: system.mem_ctrls_1: Computing stats due to a dump callback
>
> Does anyone know of any way to properly debug the root cause of this issue? I 
> have also used the Exec and ExecAll flags, but not much more information was 
> provided.
>
> Thank you,
>
> - Alex
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On Fri, Jul 10, 2020 at 5:15 PM Alex Freij via gem5-users
 wrote:
>
> Hello all,
>
> I'm running a single core X86 o3 sim with SPEC2006 benchmarks, and have run 
> into a scenario where some of the benchmarks are terminating early. Using the 
> "DRAM" debug flag, I see this message upon termination:
>
> Exiting @ tick 67067500 because exiting with last active thread context
> 67067500: system.mem_ctrls_0: Computing stats due to a dump callback
> 67067500: system.mem_ctrls_1: Computing stats due to a dump callback
>
> Does anyone know of any way to properly debug the root cause of this issue? I 
> have also used the Exec and ExecAll flags, but not much more information was 
> provided.
>
> Thank you,
>
> - Alex
> ___
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[gem5-users] Re: Using hack_back_ckpt for checkpoint restoring

[Ciro Santilli via gem5-users]

Related: 
https://stackoverflow.com/questions/58886672/bad-function-call-m5-event-simulateargs-kwargs-when-running-full-system-b

On Fri, Jul 10, 2020 at 1:44 AM Aditya Narayan via gem5-users
 wrote:
>
> Hi,
>
> I am running into issues when using the script "hack_back_ckpt.rcS" to create 
> a checkpoint at the end of the disk image boot. I am running parsec2.1 
> applications within the disk.
> My script is as follows:
> 1. I am creating a checkpoint at the end of linux boot using the 
> "hack_back_ckpt.rcS" script
>
> >> build/X86/gem5.opt configs/example/fs.py 
> >> --kernel=kernel/x86_64-vmlinux-2.6.28.4-smp 
> >> --disk-image=disk_image/x86root-parsec.img --checkpoint-dir=checkpoint 
> >> --script=rcS/hack_back_ckpt.rcS --caches --l2cache --l1i_size=32kB 
> >> --l1d_size=32kB --l1d_assoc=2  --l1i_assoc=2 --l2_assoc=8 --l2_size=2MB 
> >> --num-cpus=8 --mem-type=HBM_1000_4H_1x128
>
> 2. Now I am running "canneal" application as follows. I am restoring with 
> "AtomicSimpleCPU" and using "DerivO3CPU" for the simulation
>
> >> build/X86/gem5.opt configs/example/fs.py 
> >> --kernel=kernel/x86_64-vmlinux-2.6.28.4-smp 
> >> --disk-image=disk_image/x86root-parsec.img 
> >> --script=rcS/canneal/canneal_8c_simmedium.rcS --checkpoint-restore=1 
> >> --checkpoint-dir=checkpoint --mem-type=HBM_1000_4H_1x128 --caches 
> >> --l2cache --l1i_size=32kB --l1d_size=32kB --l1d_assoc=2 --l1i_assoc=2 
> >> --l2_assoc=8 --l2_size=2MB -I 10 
> >> --restore-with-cpu=AtomicSimpleCPU --cpu-type=DerivO3CPU
>
> I get an error stating
>
> Traceback (most recent call last):
>
>   File "", line 1, in 
>
>   File "build/X86/python/m5/main.py", line 457, in main
>
>   File "/projectnb/hetero-sys/gem5_final/configs/example/fs.py", line 384, in 
> 
>
> Simulation.run(options, root, test_sys, FutureClass)
>
>   File "/projectnb2/hetero-sys/gem5_final/configs/common/Simulation.py", line 
> 726, in run
>
> exit_event = benchCheckpoints(options, maxtick, cptdir)
>
>   File "/projectnb2/hetero-sys/gem5_final/configs/common/Simulation.py", line 
> 269, in benchCheckpoints
>
> exit_event = m5.simulate(maxtick - m5.curTick())
>
>   File "build/X86/python/m5/simulate.py", line 180, in simulate
>
> RuntimeError: bad_function_call
>
>
> I understand the curTick() is going above maxtick. What might cause this to 
> happen? Is there any problem with how I am using hack_back_ckpt.rcS script to 
> run the FS simulations?
>
> Thanks,
> Aditya
>
>
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[gem5-users] Re: dump out the register value of each instruction

[Ciro Santilli via gem5-users]

One option might be to --debug-flags Registers and look up to latest
register modification. See also --debug-help.


On Thu, Jul 9, 2020 at 6:19 PM Shougang Yuan via gem5-users
 wrote:
>
> Hi, All,
>
> I want to dump out the source register and destination register value of each 
> instruction. Suppose I have one instruction MOV_R_M : ld   rax, DS:[rdx + 
> 0x20]. How can I dump out the value of register rax and rdx.
>
> From the debug trace like Exec or ExecAll. I can see that the result or the 
> destination register is dumped out, but the source register values are not. 
> So is there a way to dump out the values of these registers in the pipeline.
>
> Best regards.
> Shougang
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[gem5-users] Re: ARM full-system simulation error during checkpoint: rcu_preempt detected stalls on CPUs/tasks

[Ciro Santilli via gem5-users]

I'm not aware of this, please provide further reproduction details on JIRA 
(which kernel, full gem5 CLIs, gem5 git version) and we'll have a look.


From: Choe, Jiwon via gem5-users 
Sent: Wednesday, July 8, 2020 5:35 PM
To: gem5 users mailing list 
Cc: Choe, Jiwon 
Subject: [gem5-users] ARM full-system simulation error during checkpoint: 
rcu_preempt detected stalls on CPUs/tasks

Hi,

I am currently running a 32-bit ARM full-system simulation. After I boot up the 
OS on the simulated system, I take a checkpoint.

This worked fine before, but after I made some changes to the DRAM controller 
code, the checkpoint stalls and I get this error message in the simulated 
console:

INFO: rcu_preempt detected stalls on CPUs/tasks: { 2} (detected by 0, t=2102 
jiffies, g=4294967009, c=4294967008, q=255)

(A huge log of CPU backtraces follow this error message.)

Has anyone run into similar issues before? I am a bit lost on where to start 
debugging.

Thanks,
Jiwon
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[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

[Ciro Santilli via gem5-users]

Shehab, sorry for the delay, I had to check a few things about this,

First, are you aware that there is a not-yet-merged patch that implements a two 
level TLB at: 
https://github.com/giactra/gem5/commit/3022ecc8a06a9182b2cf1936941901a785c1b21d 
?

It hasn't been merged because we noticed that it broke Linux boot I think. But 
we would like to merge it in the following months.

I'm not sure why Ruby vs classic would matter since the TLB sits behind caches 
anyways? I believe that model will work for either classic or Ruby.

From: Shehab Elsayed via gem5-users 
Sent: Tuesday, June 23, 2020 12:20 AM
To: gem5 users mailing list 
Cc: Shehab Elsayed 
Subject: [gem5-users] 2 level TLB in ARM Full System with Ruby

Hello All,

I was wondering if there is a way to simulate a system with 2 levels of TLBs in 
full system simulation with ruby for ARM?

I have seen other examples that use the classical memory model and use a cache 
as the second level TLB. Is there something similar that can be done in Ruby 
memory system. Can I use a standalone RubyCache as the second level TLB?

Thank you very much in advance.

Best Regards,
Shehab
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[gem5-users] Re: What is miscellaneous register

[Ciro Santilli via gem5-users]

Also, in ARM more specifically, you can see miscregs at
https://github.com/gem5/gem5/blob/cc3e12b504c20b3bc78db52059d3f4f9b02dfbe8/src/arch/arm/miscregs.hh#L56

Most are what the ARM manuals call "System Registers", but a few
others are just convenient ways to implement other ISA features like
e.g. MISCREG_LOCKADDR for LLSC.

On Wed, Jul 8, 2020 at 4:31 AM Gabe Black via gem5-users
 wrote:
>
> A long time ago when gem5 just supported Alpha, there were three types of 
> registers, integers, floats, and everything else. The "everything else" were 
> essentially control registers, or in other words registers which had side 
> effects from accessing them. They were called "Misc" for miscellaneous since 
> they were the left overs if you took away the ints and the floats. There are 
> more types of registers now, but the control registers are still called 
> "Misc".
>
> Gabe
>
> On Tue, Jul 7, 2020 at 2:01 PM Shougang Yuan via gem5-users 
>  wrote:
>>
>> Hi, All,
>>
>> I have one question regarding the miscellaneous register. IN the O3 cpu 
>> model, it mentioned the miscellaneous register(or misc register) a lot of 
>> times. So what's the exact meaning of this register? Can anyone give some 
>> hints?
>>
>> Best regards.
>> Yuan
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[gem5-users] Fwd: How to check ...

[Ciro Santilli via gem5-users]

Forwarding reply to mailing list.

-- Forwarded message -
From: Anuj Falcon 
Date: Fri, Jul 3, 2020 at 8:05 AM
Subject: Re: [gem5-users] How to check ...
To: Ciro Santilli 


Below is the link to the GEM5 model. (Public)
https://gitlab.com/shaktiproject/tools/core-models-gem5

On Fri, Jul 3, 2020 at 12:16 PM Anuj Falcon  wrote:
>
> It's a regular inorder 5 stage pipeline model designed to mimic the 
> microarchitectural states of actual C-class processor mentioned here.
>
> https://gitlab.com/shaktiproject/cores/c-class
>
>
> Has fetch, decode(modified), execute, memaccess, writeback connected through 
> pipe like structures containing FIFOs, with operand forward.
>
> Working on BPU and Fault handling.
>
> Currently tested only with RISCV ISA in baremetal full system simulation. I 
> am trying to get the code to public asap.
>
> On Fri, 3 Jul, 2020, 12:05 PM Ciro Santilli,  wrote:
>>
>> Describe your model briefly here/discuss on a review request if you
>> already have code? :-)
>>
>> On Thu, Jul 2, 2020 at 11:39 PM Anuj Falcon via gem5-users
>>  wrote:
>> >
>> > How to know if my CPU model qualifies to be upstreamed with the rest of 
>> > the CPU models in gem 5 ?
>> > ___
>> > gem5-users mailing list -- gem5-users@gem5.org
>> > To unsubscribe send an email to gem5-users-le...@gem5.org
>> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s



-- 
-
J ANUJ
-
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[gem5-users] Re: How to check ...

[Ciro Santilli via gem5-users]

Describe your model briefly here/discuss on a review request if you
already have code? :-)

On Thu, Jul 2, 2020 at 11:39 PM Anuj Falcon via gem5-users
 wrote:
>
> How to know if my CPU model qualifies to be upstreamed with the rest of the 
> CPU models in gem 5 ?
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[gem5-users] Re: How to modify the simulator to load shared libs

[Ciro Santilli via gem5-users]

Hmmm, it is there on develop:
https://github.com/gem5/gem5/blob/96fce476785a834f102ae69a895e661cf08e47cd/configs/common/Options.py#L402

On Tue, Jun 9, 2020 at 4:31 PM Shougang Yuan  wrote:
>
> I tried as you said, but the error message is "error: no such option: 
> --redirects", and I check the options.py file in the configs/common 
> directory, it seems that this option has been deprecated? Or is there 
> anything I misunderstand?
>
> Best regards.
> Shougang
>
> On Tue, Jun 9, 2020 at 10:40 AM Ciro Santilli  wrote:
>>
>> --redirects /lib64=/path/to/where/you/symlinked/everything
>>
>> The linker will search in /lib64 normally, then gem5 will redirect
>> that file read to the path with all symlinks.
>>
>> On Tue, Jun 9, 2020 at 3:26 PM Shougang Yuan  wrote:
>> >
>> > Hi, Crio,
>> >
>> > Could you please give more hints about redirect /lib64 or that directory? 
>> > I can understand syslink the needed shared library into a directory, and 
>> > after that, you mean I need to redirect the lib64 to this directory or?
>> >
>> > Best regards.
>> > Shougang
>> >
>> > On Tue, Jun 9, 2020 at 2:36 AM Ciro Santilli  
>> > wrote:
>> >>
>> >> One thing to try if you are desperate: symlink every needed shared
>> >> library into a directory, and then redirect /lib64 or that directory.
>> >> I'm pretty sure this should work.
>> >>
>> >> I'm not sure why LD_LIBRARY_PATH does not work. I would dig dieeper
>> >> and try to understand that, theoretically it feels like it should
>> >> work.
>> >>
>> >>
>> >> On Mon, Jun 8, 2020 at 6:05 PM Shougang Yuan via gem5-users
>> >>  wrote:
>> >> >
>> >> > Hi, All,
>> >> >
>> >> > I am currently trying to run some benchmarks that need some shared 
>> >> > libs. If I run these benchmarks on physical machines, I need to reset 
>> >> > LD_LIBRARY_PATH to load these libs.
>> >> >
>> >> > But when I run the benchmarks with gem5, I tried to use --env options 
>> >> > and --redirects options to set LD_LIBRARY_PATH, and these two options 
>> >> > seem to not work with LD_LIBRARY_PATH correctly.
>> >> >
>> >> > So how can I modify the simulator to load these shared libs. I am fine 
>> >> > to modify the simulator infrastructures. So can anyone give some hints 
>> >> > about this? Thanks a lot.
>> >> >
>> >> > Best regards.
>> >> > Shougang
>> >> > ___
>> >> > gem5-users mailing list -- gem5-users@gem5.org
>> >> > To unsubscribe send an email to gem5-users-le...@gem5.org
>> >> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: How to modify the simulator to load shared libs

[Ciro Santilli via gem5-users]

--redirects /lib64=/path/to/where/you/symlinked/everything

The linker will search in /lib64 normally, then gem5 will redirect
that file read to the path with all symlinks.

On Tue, Jun 9, 2020 at 3:26 PM Shougang Yuan  wrote:
>
> Hi, Crio,
>
> Could you please give more hints about redirect /lib64 or that directory? I 
> can understand syslink the needed shared library into a directory, and after 
> that, you mean I need to redirect the lib64 to this directory or?
>
> Best regards.
> Shougang
>
> On Tue, Jun 9, 2020 at 2:36 AM Ciro Santilli  wrote:
>>
>> One thing to try if you are desperate: symlink every needed shared
>> library into a directory, and then redirect /lib64 or that directory.
>> I'm pretty sure this should work.
>>
>> I'm not sure why LD_LIBRARY_PATH does not work. I would dig dieeper
>> and try to understand that, theoretically it feels like it should
>> work.
>>
>>
>> On Mon, Jun 8, 2020 at 6:05 PM Shougang Yuan via gem5-users
>>  wrote:
>> >
>> > Hi, All,
>> >
>> > I am currently trying to run some benchmarks that need some shared libs. 
>> > If I run these benchmarks on physical machines, I need to reset 
>> > LD_LIBRARY_PATH to load these libs.
>> >
>> > But when I run the benchmarks with gem5, I tried to use --env options and 
>> > --redirects options to set LD_LIBRARY_PATH, and these two options seem to 
>> > not work with LD_LIBRARY_PATH correctly.
>> >
>> > So how can I modify the simulator to load these shared libs. I am fine to 
>> > modify the simulator infrastructures. So can anyone give some hints about 
>> > this? Thanks a lot.
>> >
>> > Best regards.
>> > Shougang
>> > ___
>> > gem5-users mailing list -- gem5-users@gem5.org
>> > To unsubscribe send an email to gem5-users-le...@gem5.org
>> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: How to modify the simulator to load shared libs

[Ciro Santilli via gem5-users]

One thing to try if you are desperate: symlink every needed shared
library into a directory, and then redirect /lib64 or that directory.
I'm pretty sure this should work.

I'm not sure why LD_LIBRARY_PATH does not work. I would dig dieeper
and try to understand that, theoretically it feels like it should
work.


On Mon, Jun 8, 2020 at 6:05 PM Shougang Yuan via gem5-users
 wrote:
>
> Hi, All,
>
> I am currently trying to run some benchmarks that need some shared libs. If I 
> run these benchmarks on physical machines, I need to reset LD_LIBRARY_PATH to 
> load these libs.
>
> But when I run the benchmarks with gem5, I tried to use --env options and 
> --redirects options to set LD_LIBRARY_PATH, and these two options seem to not 
> work with LD_LIBRARY_PATH correctly.
>
> So how can I modify the simulator to load these shared libs. I am fine to 
> modify the simulator infrastructures. So can anyone give some hints about 
> this? Thanks a lot.
>
> Best regards.
> Shougang
> ___
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[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

[Ciro Santilli via gem5-users]

OK, the previous --redirects idea makes no sense, nevermind, I wish I
could edit emails.

On Mon, Jun 8, 2020 at 4:39 PM Ciro Santilli  wrote:
>
> --redirects can be used multiple times. But not 100% sure it will be
> able to replace LD_LIBRARY_PATH. Just one thing worth trying along
> --redirects /path/in/ld/libray/path=/usr/lib --env does change env
> vars, but not 100% sure is it enough to make LD_LIBRARY_PATH work. In
> theory it might, but not sure.
>
> On Mon, Jun 8, 2020 at 4:04 PM Shougang Yuan  wrote:
> >
> > I do see that forum, but I need to add multiple shared libs with 
> > "LD_LIBRARY_PATH" environment variable, can I use multiple redirects to add 
> > it multiple times? I mean, Can I use it like "--redirects 
> > LD_LIBRARY_PATH=/some/path; --redirects LD_LIBRARY_PATH=/some/path" ?
> >
> > And also, I noticed someone in gem5 mailing list mentioned that --env 
> > option in se.py can help with this. I tried to add LD_LIBRARY_PATH in a txt 
> > file and feed this file into simulator with --env option. but the error is 
> > still can not find this lib. Do you have any hints about this?
> >
> > Best regards.
> > Shougang
> >
> > On Mon, Jun 8, 2020 at 10:42 AM Ciro Santilli  
> > wrote:
> >>
> >> Have you tried --redirects as mentioned at
> >> https://stackoverflow.com/questions/5054/how-to-run-a-dynamically-linked-executable-syscall-emulation-mode-se-py-in-gem5/50696098#50696098
> >> ?
> >>
> >> On Mon, Jun 8, 2020 at 2:31 PM Shougang Yuan  wrote:
> >> >
> >> > In syscall emulation mode. I tried to use --env option with myse.py, but 
> >> > it still shows the same error.
> >> >
> >> > On Mon, Jun 8, 2020 at 3:39 AM Ciro Santilli  
> >> > wrote:
> >> >>
> >> >> Syscall emulation or full system?
> >> >>
> >> >> On Sun, Jun 7, 2020 at 10:01 PM Shougang Yuan via gem5-users
> >> >>  wrote:
> >> >> >
> >> >> > HI, All,
> >> >> >
> >> >> > I am trying to run some benchmarks that need some shared libs, and 
> >> >> > these shared libs are imported by setting the environment variables 
> >> >> > "LD_LIBRARY_PATH" if I run it on physical machines. But if I run the 
> >> >> > benchmarks with gem5, the error message is "error while loading 
> >> >> > shared libraries: libs.so.1: cannot open shared object file: No such 
> >> >> > file or directory".
> >> >> >
> >> >> > Any hints about how to solve this issue? Thanks a lot.
> >> >> >
> >> >> > Best regards.
> >> >> > Shougang
> >> >> > ___
> >> >> > gem5-users mailing list -- gem5-users@gem5.org
> >> >> > To unsubscribe send an email to gem5-users-le...@gem5.org
> >> >> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

[Ciro Santilli via gem5-users]

--redirects can be used multiple times. But not 100% sure it will be
able to replace LD_LIBRARY_PATH. Just one thing worth trying along
--redirects /path/in/ld/libray/path=/usr/lib --env does change env
vars, but not 100% sure is it enough to make LD_LIBRARY_PATH work. In
theory it might, but not sure.

On Mon, Jun 8, 2020 at 4:04 PM Shougang Yuan  wrote:
>
> I do see that forum, but I need to add multiple shared libs with 
> "LD_LIBRARY_PATH" environment variable, can I use multiple redirects to add 
> it multiple times? I mean, Can I use it like "--redirects 
> LD_LIBRARY_PATH=/some/path; --redirects LD_LIBRARY_PATH=/some/path" ?
>
> And also, I noticed someone in gem5 mailing list mentioned that --env option 
> in se.py can help with this. I tried to add LD_LIBRARY_PATH in a txt file and 
> feed this file into simulator with --env option. but the error is still can 
> not find this lib. Do you have any hints about this?
>
> Best regards.
> Shougang
>
> On Mon, Jun 8, 2020 at 10:42 AM Ciro Santilli  wrote:
>>
>> Have you tried --redirects as mentioned at
>> https://stackoverflow.com/questions/5054/how-to-run-a-dynamically-linked-executable-syscall-emulation-mode-se-py-in-gem5/50696098#50696098
>> ?
>>
>> On Mon, Jun 8, 2020 at 2:31 PM Shougang Yuan  wrote:
>> >
>> > In syscall emulation mode. I tried to use --env option with myse.py, but 
>> > it still shows the same error.
>> >
>> > On Mon, Jun 8, 2020 at 3:39 AM Ciro Santilli  
>> > wrote:
>> >>
>> >> Syscall emulation or full system?
>> >>
>> >> On Sun, Jun 7, 2020 at 10:01 PM Shougang Yuan via gem5-users
>> >>  wrote:
>> >> >
>> >> > HI, All,
>> >> >
>> >> > I am trying to run some benchmarks that need some shared libs, and 
>> >> > these shared libs are imported by setting the environment variables 
>> >> > "LD_LIBRARY_PATH" if I run it on physical machines. But if I run the 
>> >> > benchmarks with gem5, the error message is "error while loading shared 
>> >> > libraries: libs.so.1: cannot open shared object file: No such file or 
>> >> > directory".
>> >> >
>> >> > Any hints about how to solve this issue? Thanks a lot.
>> >> >
>> >> > Best regards.
>> >> > Shougang
>> >> > ___
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>> >> > To unsubscribe send an email to gem5-users-le...@gem5.org
>> >> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

[Ciro Santilli via gem5-users]

Have you tried --redirects as mentioned at
https://stackoverflow.com/questions/5054/how-to-run-a-dynamically-linked-executable-syscall-emulation-mode-se-py-in-gem5/50696098#50696098
?

On Mon, Jun 8, 2020 at 2:31 PM Shougang Yuan  wrote:
>
> In syscall emulation mode. I tried to use --env option with myse.py, but it 
> still shows the same error.
>
> On Mon, Jun 8, 2020 at 3:39 AM Ciro Santilli  wrote:
>>
>> Syscall emulation or full system?
>>
>> On Sun, Jun 7, 2020 at 10:01 PM Shougang Yuan via gem5-users
>>  wrote:
>> >
>> > HI, All,
>> >
>> > I am trying to run some benchmarks that need some shared libs, and these 
>> > shared libs are imported by setting the environment variables 
>> > "LD_LIBRARY_PATH" if I run it on physical machines. But if I run the 
>> > benchmarks with gem5, the error message is "error while loading shared 
>> > libraries: libs.so.1: cannot open shared object file: No such file or 
>> > directory".
>> >
>> > Any hints about how to solve this issue? Thanks a lot.
>> >
>> > Best regards.
>> > Shougang
>> > ___
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>> > To unsubscribe send an email to gem5-users-le...@gem5.org
>> > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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[gem5-users] Re: How to add shared libs that used by benchmarks to the simulator

[Ciro Santilli via gem5-users]

Syscall emulation or full system?

On Sun, Jun 7, 2020 at 10:01 PM Shougang Yuan via gem5-users
 wrote:
>
> HI, All,
>
> I am trying to run some benchmarks that need some shared libs, and these 
> shared libs are imported by setting the environment variables 
> "LD_LIBRARY_PATH" if I run it on physical machines. But if I run the 
> benchmarks with gem5, the error message is "error while loading shared 
> libraries: libs.so.1: cannot open shared object file: No such file or 
> directory".
>
> Any hints about how to solve this issue? Thanks a lot.
>
> Best regards.
> Shougang
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[gem5-users] Re: Newly copied files are truncated in gem5 FS mode

[Ciro Santilli via gem5-users]

Are you mounting and modifying the disk on the host while gem5 is
using it at the same time? That likey cannot work because the Linux
kernel representation of guest and host will differ. Also gem5 does
not write back to disk.

The file sharing mechanisms I know to modify guest visible files from
host easily are:

- use a Secondary disk
https://stackoverflow.com/questions/50862906/how-to-attach-multiple-disk-images-in-a-simulation-with-gem5-fs-py/60210181#60210181
- 9P summarized at: https://cirosantilli.com/linux-kernel-module-cheat/#9p
- you could also do it with m5 readfile





On Thu, Jun 4, 2020 at 3:38 PM VAUMOURIN, GREGORY via gem5-users
 wrote:
>
> Hi guys,
>
>
>
> I did not use gem5 for a long time and I try to get back at it. I am also new 
> to full system simulations.
>
> I am facing a problem when I try to copy files on on my gem5 image disk and 
> access them through my gem5 simulation.
>
>
>
> I have an ubuntu 16 img for ARM 64bits that boots and I can checkpoint and 
> simulate and everythings looks OK. But when I try to add new files to it, the 
> new files are not visible within my gem5 simulation or sometimes they appears 
> but are truncated
>
> To add new files, I mount it on a loop device on the host computer which is 
> not ARM, it is a RHEL7 with x86_64 architecture like this
>
> sudo mount -o loop,offset=65536 gem5-ubuntu16.04-aarch64-20190523.img  mountpoint>
>
>
>
> When I open my simulation in interactive mode, and stat my copied file:
>
> root@aarch64-gem5:/home/test# stat ./stream_armclang_sve.exe
>
> stat ./stream_armclang_sve.exe
>
> File: './stream_armclang_sve.exe'
>
> Size: 5   Blocks: 8  IO Block: 4096   regular file
>
> Device: 801h/2049d  Inode: 405148  Links: 1
>
>
>
> And when I do the same operation on my host computer:
>
> File: './stream_armclang_sve.exe'
>
> Size: 379 Blocks: 7392   IO Block: 4096   regular file
>
> Device: 702h/1794d  Inode: 405148  Links: 1
>
>
>
> Inode is the same but the size of the file is different, and I get a strange 
> error while trying to execute it.
>
> It looks like there is a difference between the host OS and the simulated OS 
> in gem5 in the way they read/write the disk image that I am not sure how to 
> solve
>
>
>
> My command to launch is as follow, I am starting from a checkpoint:
>
> ./build/ARM/gem5.opt \
>
> --outdir=m5out/stream_sve_16core_HBM2 \
>
> configs/example/fs.py \
>
> -r 1 \
>
> --checkpoint-dir= \
>
> --cpu-type=AtomicCPU \
>
> --restore-with-cpu= AtomicCPU \
>
> --arm-iset=aarch64 \
>
> --machine-type=VExpress_GEM5_V1 \
>
> --kernel=linuximage/vmlinux \
>
> --disk=
>
> --machine-type=VExpress_GEM5_V1 \
>
> --num-cpus=16 \
>
> --num-dirs=8 \
>
> …
>
>
>
> I was wondering what is your best practices to transfer files to the img disk 
> and any help is welcome !
>
> Thanks for your patience =)
>
>
>
> Gregory .V
>
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[gem5-users] Re: Running Gem5/Ruby tests

[Ciro Santilli via gem5-users]

It does look like your host's library is not compatible with whatever
was used to compile that C hello world.

You can't in general download and run dynamically linked programs
built for other toolchains, you either have to build it yourself
(often the easiest thing to do) or somehow obtain a compatible
toolchain.

On Tue, Jun 2, 2020 at 4:53 PM Javed Osmany via gem5-users
 wrote:
>
> Hello
>
>
>
> Looking in /usr/lib64 on my system, it shows:
>
>
>
> [j00533938@lhrplinux1 lib64]$ pwd
>
> /usr/lib64
>
> [j00533938@lhrplinux1 lib64]$ /bin/ls -al libstdc*
>
> lrwxrwxrwx 1 root root 19 Sep 26  2019 libstdc++.so.6 -> 
> libstdc++.so.6.0.19
>
> -rwxr-xr-x 1 root root 991616 Aug  6  2019 libstdc++.so.6.0.19
>
>
>
> Just wondering if this is an issue with not linking to the correct version of 
> libstdc++.so
>
>
>
> Tks in advance.
>
>
>
>
>
> JO
>
>
>
>
>
> From: Javed Osmany
> Sent: 02 June 2020 16:11
> To: gem5 users mailing list 
> Cc: Javed Osmany 
> Subject: Running Gem5/Ruby tests
>
>
>
> Hello
>
>
>
> I am trying to get started running some very simple tests on Gem5/Ruby. 
> However, I am getting errors:
>
>
>
> [j00533938@lhrplinux1 gem5]$ ./build/X86_MSI/gem5.opt 
> configs/example/se.py --ruby --cpu_type=timing -c 
> tests/test-progs/hello/bin/x86/linux/hello
>
> ./build/X86_MSI/gem5.opt: /lib64/libstdc++.so.6: version `CXXABI_1.3.8' not 
> found (required by ./build/X86_MSI/gem5.opt)
>
> ./build/X86_MSI/gem5.opt: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.20' not 
> found (required by ./build/X86_MSI/gem5.opt)
>
>
>
>
>
> [j00533938@lhrplinux1 gem5]$ ./build/X86/gem5.opt configs/example/se.py 
> --ruby --cpu_type=timing -c tests/test-progs/hello/bin/x86/linux/hello
>
> ./build/X86/gem5.opt: /lib64/libstdc++.so.6: version `CXXABI_1.3.8' not found 
> (required by ./build/X86/gem5.opt)
>
> ./build/X86/gem5.opt: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.20' not 
> found (required by ./build/X86/gem5.opt)
>
>
>
>
>
> ./build/X86_MSI/gem5.opt configs/learning_gem5/part3/simple_ruby.py
>
> ./build/X86_MSI/gem5.opt: /lib64/libstdc++.so.6: version `CXXABI_1.3.8' not 
> found (required by ./build/X86_MSI/gem5.opt)
>
> ./build/X86_MSI/gem5.opt: /lib64/libstdc++.so.6: version `GLIBCXX_3.4.20' not 
> found (required by ./build/X86_MSI/gem5.opt)
>
>
>
>
>
> Any pointers to fix the above issues, greatly appreciated.
>
>
>
> Thanks in advance.
>
>
>
> JO
>
>
>
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[gem5-users] Re: Any way to add randomization into full system simulation?

[Ciro Santilli via gem5-users]

Maybe you want to look into: m5 readfile, 9P or use two disks as
mentioned at: 
https://cirosantilli.com/linux-kernel-module-cheat/#gem5-restore-new-script

On Sun, May 17, 2020 at 9:20 PM HENG ZHUO via gem5-users
 wrote:
>
> Hi,
>
> I am trying to run some benchmark on ARM full system simulation. Already use 
> AtomicSimpleCPU to do the bootup and everything to speed up warmup, but 
> still, ROI is few seconds of machine time, which takes up to few days to 
> simulate. Also, for statistical confidence reasons, repeated run with same 
> configs is wanted. With knowing that gem5 is deterministic, just re-restore 
> with the same checkpoints will just give me same results. I want to launch 
> multiple (for example 10) copies of same gem5 commands. Is there anyway in 
> gem5, which allows insetting randomization between runs? For instance, can I 
> somehow change the random seed in the full system, but after restoring from 
> the same checkpoint? Or, I will have to just generate different checkpoints.
>
> Any suggestions/help is appreciated!
>
> Best,
> Heng
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[gem5-users] Re: Traces of instructions only.

[Ciro Santilli via gem5-users]

There is no stupid question around here, ask away :-)

On Wed, May 6, 2020 at 10:33 PM Øivind Harket Bakke via gem5-users
 wrote:
>
> Dear Santilli,
>
> that fixed everything except my embarrassment.
> Thank you very much, really appriciated!
>
> Best regards,
> Øivind
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[gem5-users] Re: Traces of instructions only.

[Ciro Santilli via gem5-users]

Maybe did you mean to use -ExecMicro to remove microops rather than
-ExecMacro? E.g. one STP generates 4 microops as shown at:
https://cirosantilli.com/linux-kernel-module-cheat/#gem5-execall-trace-format



On Wed, May 6, 2020 at 8:54 PM Øivind Harket Bakke via gem5-users
 wrote:
>
> Hi all,
>
> I'm currently trying to export traces from a simulation, but I'm only 
> interested in the instructions that are being simulated. I compare the stats 
> file (# of simulated instructions) to the traces and they don't match in 
> size. I've tried to figure out which are the excessive lines in order filter 
> them out. So my question is as follows: How would I proceed to get traces of 
> the instructions only?
>
> Here's the command I run:
> ./build/ARM/gem5.opt --debug-flags=Exec,-ExecMacro --debug-file=trace.out -d 
> configs/Forschung/arm/1G-500M/ configs/Forschung/arm/starter_se.py 
> --cpu="hpi_nL" --cpu-freq="1GHz" tests/test-progs/hello/bin/arm/linux/hello
>
> For clearification, the config file is a copy of the one in arm examples, 
> just adding a HPI model without L2 caches.(hpi_nL)
> I've checked out the --debug-help option, but as far as I could tell, there 
> were no flags to remove from Exec or other flags to enable in order to reach 
> my goal.
>
>
> Thanks in advance,
> Øivind Harket Bakke
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[gem5-users] Re: How to use GUEST BINARIES in fs?

[Ciro Santilli via gem5-users]

OK, also quick grep in kernel code and we can see that -8 and -13 are
the same as exec syscall error numbers:

#define ENOEXEC 8 /* Exec format error */
#define EACCES 13 /* Permission denied */

not 100% sure what those mean, but worth looking into as well.

On Sat, Apr 25, 2020 at 7:13 PM Ciro Santilli  wrote:
>
> No worries. I would mount the image on host and ensure that the init
> you think is there is actually there, and that it seems to be right
> filetype (ISA is ARM, is executable, etc.). And ensure that you are
> pointing to it with init= kernel CLI parameter. If you don't
> understand from that, GDB step debug the kernel at that point and then
> it will be easy to see which inits the kernel is trying and why it
> skips yours.
>
> On Sat, Apr 25, 2020 at 5:46 PM Taiyu Zhou <645505...@qq.com> wrote:
> >
> > Hi Ciro.
> > I tried to build my own vmlinux( linux4.3 ),and follow 
> > http://www.lowepower.com/jason/setting-up-gem5-full-system.html to make my 
> > own ubuntu-16 disk image.I think the ubuntu-16 disk image is too large, 
> > because it will use 100% of my memory and crash my os finally when booting. 
> > So I try to use disk image "aarch64-ubuntu-trusty-headless.img.bz2”. But 
> > when use m5term to connect  it will reports that
> >
> > Starting init: /sbin/init exists but couldn’t execute it (error -8)
> > Starting init: /etc/init exists but couldn’t execute it (error -13)
> > Starting init: /bin/sh exists but couldn’t execute it (error -8)
> > Kernel panic  -not syncing: No working init found.
> >
> > Have you seen this error before?
> > Thank you for your patience reply.
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[gem5-users] Re: How to use GUEST BINARIES in fs?

[Ciro Santilli via gem5-users]

No worries. I would mount the image on host and ensure that the init
you think is there is actually there, and that it seems to be right
filetype (ISA is ARM, is executable, etc.). And ensure that you are
pointing to it with init= kernel CLI parameter. If you don't
understand from that, GDB step debug the kernel at that point and then
it will be easy to see which inits the kernel is trying and why it
skips yours.

On Sat, Apr 25, 2020 at 5:46 PM Taiyu Zhou <645505...@qq.com> wrote:
>
> Hi Ciro.
> I tried to build my own vmlinux( linux4.3 ),and follow 
> http://www.lowepower.com/jason/setting-up-gem5-full-system.html to make my 
> own ubuntu-16 disk image.I think the ubuntu-16 disk image is too large, 
> because it will use 100% of my memory and crash my os finally when booting. 
> So I try to use disk image "aarch64-ubuntu-trusty-headless.img.bz2”. But when 
> use m5term to connect  it will reports that
>
> Starting init: /sbin/init exists but couldn’t execute it (error -8)
> Starting init: /etc/init exists but couldn’t execute it (error -13)
> Starting init: /bin/sh exists but couldn’t execute it (error -8)
> Kernel panic  -not syncing: No working init found.
>
> Have you seen this error before?
> Thank you for your patience reply.
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[gem5-users] Re: How to use GUEST BINARIES in fs?

[Ciro Santilli via gem5-users]

You could download from:
http://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries
section "Latest Linux Disk Images (recommended)"

Personally I normally use Buildroot:
https://github.com/cirosantilli/linux-kernel-module-cheat/tree/d0aac8d6f90477db394945127b621df7023a3a24#gem5-buildroot-setup-getting-started


On Sat, Apr 25, 2020 at 4:15 PM Taiyu Zhou <645505...@qq.com> wrote:
>
> Hi Ciro.
> Thanks for you help.
> I’ve set the M5_PATH and tried to use full path but it still not work for me. 
> It's really strange.
> And by the way, how you create a disk image. I follow the tutorial in 
> http://www.lowepower.com/jason/creating-disk-images-for-gem5.html. To create 
> a blank disk image by “ util/gem5img.py init ubuntu-14.04.img 4096 “.But it 
> can’t work because the sfdisk command.
>
> "
> %> /sbin/sfdisk --no-reread -D -C 8322 -H 16 -S 63 /dev/loop17
> /sbin/sfdisk: invalid option -- ‘D'
> “
> Thanks a lot.
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[gem5-users] Re: How to use GUEST BINARIES in fs?

[Ciro Santilli via gem5-users]

Can you also try to use the full path to vmlinux.arm64 instead of just
basename? I suspect it is currently searching for it on M5_PATH
(because not slashes in the path) and finding some broken image there.
Better still, get rid of M5_PATH altogether if possible.

My full non minimized CLI with gem5 b1623cb2087873f64197e503ab8894b5e4d4c7b4 is:

M5_OVERRIDE_PY_SOURCE=true \
  
/home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/master3/build/ARM/gem5.opt
\
  --debug-file trace.txt \
  --listener-mode on \
  --outdir 
/home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/m5out
\
  
/home/ciro/bak/git/linux-kernel-module-cheat/data/gem5/master3/configs/example/fs.py
\
  --kernel /mnt/hd/gem5-images/aarch-system-201901106/binaries/vmlinux.arm64 \
  --num-cpus 1 \
  --script 
/home/ciro/bak/git/linux-kernel-module-cheat/out/run/gem5/aarch64/0/readfile
\
  --disk-image 
/home/ciro/bak/git/linux-kernel-module-cheat/out/buildroot/build/default/aarch64/images/rootfs.ext2
\
  --machine-type VExpress_GEM5_V1 \
  --command-line 'earlyprintk=pl011,0x1c09 lpj=19988480 rw
loglevel=8 mem=256MB root=/dev/sda console_msg_format=syslog nokaslr
norandmaps panic=-1 printk.devkmsg=on printk.time=y rw console=ttyAMA0
- lkmc_home=/lkmc' \
  --param 'system.workload.panic_on_panic = True' \
  --bootloader 
/home/ciro/bak/git/linux-kernel-module-cheat/out/gem5/master3/system/binaries/boot.arm64
\
  --mem-size 256MB \
;

On Sat, Apr 25, 2020 at 1:49 PM Taiyu Zhou via gem5-users
 wrote:
>
> Hi Ciro.
> Thanks for you reply.Could you show me the script  you run on 
> vmlinux.arm64 and your config?
> Because I think I don’t run on right command.
> I run
> "./build/X86/gem5.opt configs/example/fs.py --kernel=vmlinux.arm64 
> --disk-image=aarch64-ubuntu-trusty-headless.img" gem5 reports that
> fatal: could not load kernel symbols
>
> But when I run
> “./build/X86/gem5.opt configs/example/fs.py --kernel=boot.arm64 
> --disk-image=aarch64-ubuntu-trusty-headless.img"
>
> It works ,but not a system. I use m5term connect to it .It just show a line
> " m5 slave terminal: Terminal 0 "
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[gem5-users] Re: How to use GUEST BINARIES in fs?

[Ciro Santilli via gem5-users]

I don't know exactly what is going on, but I've tested
aarch-system-201901106/binaries/vmlinux.arm64 in fs.py and it worked
fine.

So the exact same script works with the old kernel but not new one?
Are you sure that the kernel exists at that path? Also try to GDB/PDB
debug it a bit.

On Sat, Apr 25, 2020 at 5:51 AM Taiyu Zhou via gem5-users
 wrote:
>
> Hi guys!
> I am trying to run gem5 in fs mode and I follow this tutorial 
> http://learning.gem5.org/book/part5/fs_config.html. But the kernel in this 
> tutorial is too old ( 2.6.22.9). So I try to download the newer ones in 
> http://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries. I 
> think it just simply change the config file to point to the newer image and 
> kernel.
>
> self.kernel = 'aarch-system-201901106/binaries/vmlinux.arm64'
>
> self.setDiskImage('disks/aarch64-ubuntu-trusty-headless.img')
>
>
> But It can’t work.Gem5 reports that
>
>  fatal: could not load kernel symbols
>
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[gem5-users] Re: increasing disk image size for full system simulation

[Ciro Santilli via gem5-users]

Try libguestfs-tools:
https://askubuntu.com/questions/107228/how-to-resize-virtual-machine-disk/481887#481887

It is the easiest method. I think it boots QEMU, mounts the image, and
does the resizing operations for you.

You may need to add sudo to commands due to this bug:
https://askubuntu.com/questions/1046828/how-to-run-libguestfs-tools-tools-such-as-virt-make-fs-without-sudo

I've just tested it on a Ubuntu 19.10 host and Ubuntu 18.04 Ubuntu
server image after server setup mentioned at:
https://askubuntu.com/questions/884534/how-to-run-ubuntu-desktop-on-qemu/1046792#1046792
(replacing all qcow2 with raw)

On Wed, Apr 22, 2020 at 5:23 PM Choe, Jiwon via gem5-users
 wrote:
>
> Hi all,
>
> This might not be exactly gem5-related, but I was wondering if anyone on this 
> mailing list has done this before and could help me out.
>
> I'm trying to increase the .img disk image size, and I thought I had made 
> some progress by using "qemu-img resize" and "parted" linux commands. But 
> when I try to use this image, I get an error saying: "EXT2-fs (sda1): error: 
> read_inode_bitmap: Cannot read inode bitmap".
>
> When I run e2fsck on the image, I get the following message:
> The filesystem size (according to the superblock) is 1048416 blocks
> The physical size of the device is 524128 blocks
> Either the superblock or the partition table is likely to be corrupt!
>
> Has anyone successfully managed to increase a disk image size? Or would you 
> recommend that I just create a fresh new disk image with a larger size?
>
> Thanks,
> Jiwon
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