Mesa (master): radv: fix a GPU hang when MRTs are sparse
Module: Mesa
Branch: master
Commit: 06d3c65098097675a34035da3043a71061fad17b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06d3c65098097675a34035da3043a71061fad17b
Author: Samuel Pitoiset
Date: Fri Jun 1 16:22:32 2018 +0200
radv: fix a GPU hang when MRTs are sparse
When the i-th target format is set, all previous target formats
must be non-zero to avoid hangs. In other words, without this
if a fragment shader exports mrt0, mrt2 and mrt3, the GPU hangs
because the target format of mrt1 is zero.
This fixes DXVK GPU hangs with "Seven: The Days Long Gone",
"GTA V" and probably more games.
Cc: "18.0" 18.1"
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_pipeline.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 375f7c357d..b8b425aca9 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -504,6 +504,7 @@ radv_pipeline_compute_spi_color_formats(struct
radv_pipeline *pipeline,
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
unsigned col_format = 0;
+ unsigned num_targets;
for (unsigned i = 0; i < (blend->single_cb_enable ? 1 :
subpass->color_count); ++i) {
unsigned cf;
@@ -528,6 +529,15 @@ radv_pipeline_compute_spi_color_formats(struct
radv_pipeline *pipeline,
if (blend->mrt0_is_dual_src)
col_format |= (col_format & 0xf) << 4;
blend->spi_shader_col_format = col_format;
+
+ /* If the i-th target format is set, all previous target formats must
+* be non-zero to avoid hangs.
+*/
+ num_targets = (util_last_bit(blend->spi_shader_col_format) + 3) / 4;
+ for (unsigned i = 0; i < num_targets; i++) {
+ if (!(blend->spi_shader_col_format & (0xf << (i * 4
+ blend->spi_shader_col_format |=
V_028714_SPI_SHADER_32_R << (i * 4);
+ }
}
static bool
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: make is_comparison() a non-static helper function
Module: Mesa
Branch: master
Commit: e44f90eccfaec2a1b1e813f93497bb498181dd2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e44f90eccfaec2a1b1e813f93497bb498181dd2f
Author: Samuel Pitoiset
Date: Wed May 30 14:21:41 2018 +0200
nir: make is_comparison() a non-static helper function
Rename and change the prototype for consistency regarding
nir_tex_instr_is_query(). This function will be used in the
following patch.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir.h | 24
src/compiler/nir/nir_opt_move_comparisons.c | 26 +-
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index f6086bd6c0..5a1f79515a 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1374,6 +1374,30 @@ nir_tex_instr_is_query(const nir_tex_instr *instr)
}
}
+static inline bool
+nir_alu_instr_is_comparison(const nir_alu_instr *instr)
+{
+ switch (instr->op) {
+ case nir_op_flt:
+ case nir_op_fge:
+ case nir_op_feq:
+ case nir_op_fne:
+ case nir_op_ilt:
+ case nir_op_ult:
+ case nir_op_ige:
+ case nir_op_uge:
+ case nir_op_ieq:
+ case nir_op_ine:
+ case nir_op_i2b:
+ case nir_op_f2b:
+ case nir_op_inot:
+ case nir_op_fnot:
+ return true;
+ default:
+ return false;
+ }
+}
+
static inline nir_alu_type
nir_tex_instr_src_type(const nir_tex_instr *instr, unsigned src)
{
diff --git a/src/compiler/nir/nir_opt_move_comparisons.c
b/src/compiler/nir/nir_opt_move_comparisons.c
index 617c2ca998..5da57dc921 100644
--- a/src/compiler/nir/nir_opt_move_comparisons.c
+++ b/src/compiler/nir/nir_opt_move_comparisons.c
@@ -51,30 +51,6 @@
*/
static bool
-is_comparison(nir_op op)
-{
- switch (op) {
- case nir_op_flt:
- case nir_op_fge:
- case nir_op_feq:
- case nir_op_fne:
- case nir_op_ilt:
- case nir_op_ult:
- case nir_op_ige:
- case nir_op_uge:
- case nir_op_ieq:
- case nir_op_ine:
- case nir_op_i2b:
- case nir_op_f2b:
- case nir_op_inot:
- case nir_op_fnot:
- return true;
- default:
- return false;
- }
-}
-
-static bool
move_comparison_source(nir_src *src, nir_block *block, nir_instr *before)
{
if (!src->is_ssa)
@@ -84,7 +60,7 @@ move_comparison_source(nir_src *src, nir_block *block,
nir_instr *before)
if (src_instr->block == block &&
src_instr->type == nir_instr_type_alu &&
- is_comparison(nir_instr_as_alu(src_instr)->op)) {
+ nir_alu_instr_is_comparison(nir_instr_as_alu(src_instr))) {
exec_node_remove(&src_instr->node);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: implement the GLSL equivalent of if simplication in nir_opt_if
Module: Mesa
Branch: master
Commit: e3e929f8c342b32dc8f5296adf8fb337866fa40a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3e929f8c342b32dc8f5296adf8fb337866fa40a
Author: Samuel Pitoiset
Date: Wed May 30 14:21:42 2018 +0200
nir: implement the GLSL equivalent of if simplication in nir_opt_if
This pass turns:
if (cond) {
} else {
do_work();
}
into:
if (!cond) {
do_work();
} else {
}
Here's the vkpipeline-db stats (from affected shaders) on Polaris10:
Totals from affected shaders:
SGPRS: 17272 -> 17296 (0.14 %)
VGPRS: 18712 -> 18740 (0.15 %)
Spilled SGPRs: 1179 -> 1142 (-3.14 %)
Code Size: 1503364 -> 1515176 (0.79 %) bytes
Max Waves: 916 -> 911 (-0.55 %)
This pass only affects Serious Sam 2017 (Vulkan) on my side. The
stats are not really good for now. Some shaders look quite dumb
but this will be improved with further NIR passes, like ifs
combination.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir_opt_if.c | 97 ---
1 file changed, 92 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index 68dacea770..b03657a424 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -22,6 +22,7 @@
*/
#include "nir.h"
+#include "nir/nir_builder.h"
#include "nir_control_flow.h"
/**
@@ -201,7 +202,89 @@ opt_peel_loop_initial_if(nir_loop *loop)
}
static bool
-opt_if_cf_list(struct exec_list *cf_list)
+is_block_empty(nir_block *block)
+{
+ return nir_cf_node_is_last(&block->cf_node) &&
+ exec_list_is_empty(&block->instr_list);
+}
+
+/**
+ * This optimization turns:
+ *
+ * if (cond) {
+ * } else {
+ * do_work();
+ * }
+ *
+ * into:
+ *
+ * if (!cond) {
+ * do_work();
+ * } else {
+ * }
+ */
+static bool
+opt_if_simplification(nir_builder *b, nir_if *nif)
+{
+ /* Only simplify if the then block is empty and the else block is not. */
+ if (!is_block_empty(nir_if_first_then_block(nif)) ||
+ is_block_empty(nir_if_first_else_block(nif)))
+ return false;
+
+ /* Make sure the condition is a comparison operation. */
+ nir_instr *src_instr = nif->condition.ssa->parent_instr;
+ if (src_instr->type != nir_instr_type_alu)
+ return false;
+
+ nir_alu_instr *alu_instr = nir_instr_as_alu(src_instr);
+ if (!nir_alu_instr_is_comparison(alu_instr))
+ return false;
+
+ /* Insert the inverted instruction and rewrite the condition. */
+ b->cursor = nir_after_instr(&alu_instr->instr);
+
+ nir_ssa_def *new_condition =
+ nir_inot(b, &alu_instr->dest.dest.ssa);
+
+ nir_if_rewrite_condition(nif, nir_src_for_ssa(new_condition));
+
+ /* Grab pointers to the last then/else blocks for fixing up the phis. */
+ nir_block *then_block = nir_if_last_then_block(nif);
+ nir_block *else_block = nir_if_last_else_block(nif);
+
+ /* Walk all the phis in the block immediately following the if statement and
+* swap the blocks.
+*/
+ nir_block *after_if_block =
+ nir_cf_node_as_block(nir_cf_node_next(&nif->cf_node));
+
+ nir_foreach_instr(instr, after_if_block) {
+ if (instr->type != nir_instr_type_phi)
+ continue;
+
+ nir_phi_instr *phi = nir_instr_as_phi(instr);
+
+ foreach_list_typed(nir_phi_src, src, node, &phi->srcs) {
+ if (src->pred == else_block) {
+src->pred = then_block;
+ } else if (src->pred == then_block) {
+src->pred = else_block;
+ }
+ }
+ }
+
+ /* Finally, move the else block to the then block. */
+ nir_cf_list tmp;
+ nir_cf_extract(&tmp, nir_before_cf_list(&nif->else_list),
+nir_after_cf_list(&nif->else_list));
+ nir_cf_reinsert(&tmp, nir_before_cf_list(&nif->then_list));
+ nir_cf_delete(&tmp);
+
+ return true;
+}
+
+static bool
+opt_if_cf_list(nir_builder *b, struct exec_list *cf_list)
{
bool progress = false;
foreach_list_typed(nir_cf_node, cf_node, node, cf_list) {
@@ -211,14 +294,15 @@ opt_if_cf_list(struct exec_list *cf_list)
case nir_cf_node_if: {
nir_if *nif = nir_cf_node_as_if(cf_node);
- progress |= opt_if_cf_list(&nif->then_list);
- progress |= opt_if_cf_list(&nif->else_list);
+ progress |= opt_if_cf_list(b, &nif->then_list);
+ progress |= opt_if_cf_list(b, &nif->else_list);
+ progress |= opt_if_simplification(b, nif);
break;
}
case nir_cf_node_loop: {
nir_loop *loop = nir_cf_node_as_loop(cf_node);
- progress |= opt_if_cf_list(&loop->body);
+ progress |= opt_if_cf_list(b, &loop->body);
progress |= opt_peel_loo
Mesa (master): nir: optimize iand(ieq(a, 0), ieq(b, 0)) to ieq(ior(a, b), 0)
Module: Mesa
Branch: master
Commit: 70f9e2589e6be7857c9c874aa1967e8b8608db88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70f9e2589e6be7857c9c874aa1967e8b8608db88
Author: Samuel Pitoiset
Date: Wed May 30 10:48:31 2018 +0200
nir: optimize iand(ieq(a, 0), ieq(b, 0)) to ieq(ior(a, b), 0)
Totals from affected shaders:
SGPRS: 80 -> 80 (0.00 %)
VGPRS: 48 -> 48 (0.00 %)
Code Size: 2120 -> 2096 (-1.13 %) bytes
Max Waves: 16 -> 16 (0.00 %)
Only two Rise of Tomb Raider shaders are affected on my side.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Ian Romanick
---
src/compiler/nir/nir_opt_algebraic.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 21b9acecbe..ba788f221a 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -282,6 +282,8 @@ optimizations = [
(('iand', ('uge(is_used_once)', a, b), ('uge', a, c)), ('uge', a, ('umax',
b, c))),
(('iand', ('uge(is_used_once)', a, c), ('uge', b, c)), ('uge', ('umin', a,
b), c)),
+ (('iand', ('ieq', 'a@32', 0), ('ieq', 'b@32', 0)), ('ieq', ('ior', 'a@32',
'b@32'), 0)),
+
# These patterns can result when (a < b || a < c) => (a < min(b, c))
# transformations occur before constant propagation and loop-unrolling.
(('~flt', a, ('fmax', b, a)), ('flt', a, b)),
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix emitting descriptor pointers with LLVM < 7
Module: Mesa
Branch: master
Commit: 02c7916298e8e29b130735bd30e97c57d40a197f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02c7916298e8e29b130735bd30e97c57d40a197f
Author: Samuel Pitoiset
Date: Wed May 30 11:15:12 2018 +0200
radv: fix emitting descriptor pointers with LLVM < 7
This was terribly wrong, I forced use of 32-bit pointers when
emitting shader descriptor pointers. This fixes GPU hangs with
LLVM 5&6 because 32-bit pointers are only supported with LLVM 7.
Fixes: 88d1ed0f81 ("radv: emit shader descriptor pointers consecutively")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8f351b52c9..6ff1f1a6cb 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -624,12 +624,14 @@ radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer,
struct radv_userdata_info *loc = &locs->descriptor_sets[start];
unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
- radv_emit_shader_pointer_head(cs, sh_offset, count, true);
+ radv_emit_shader_pointer_head(cs, sh_offset, count,
+ HAVE_32BIT_POINTERS);
for (int i = 0; i < count; i++) {
struct radv_descriptor_set *set =
descriptors_state->sets[start + i];
- radv_emit_shader_pointer_body(device, cs, set->va,
true);
+ radv_emit_shader_pointer_body(device, cs, set->va,
+ HAVE_32BIT_POINTERS);
}
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: split radv_emit_shader_pointer()
Module: Mesa
Branch: master
Commit: 288fe7ec714f0920e870d0551bdaccf277e12a59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=288fe7ec714f0920e870d0551bdaccf277e12a59
Author: Samuel Pitoiset
Date: Fri May 25 14:59:19 2018 +0200
radv: split radv_emit_shader_pointer()
This will allow to emit consecutive shader pointers for
reducing the number of emitted SET_SH_REG packets, which
is recommended.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_private.h | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e2fa58d8d1..e554fc7acc 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1131,13 +1131,17 @@ bool radv_get_memory_fd(struct radv_device *device,
int *pFD);
static inline void
-radv_emit_shader_pointer(struct radv_device *device,
-struct radeon_winsys_cs *cs,
-uint32_t sh_offset, uint64_t va, bool global)
+radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+ unsigned sh_offset, bool use_32bit_pointers)
{
- bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
-
radeon_set_sh_reg_seq(cs, sh_offset, use_32bit_pointers ? 1 : 2);
+}
+
+static inline void
+radv_emit_shader_pointer_body(struct radv_device *device,
+ struct radeon_winsys_cs *cs,
+ uint64_t va, bool use_32bit_pointers)
+{
radeon_emit(cs, va);
if (use_32bit_pointers) {
@@ -1148,6 +1152,17 @@ radv_emit_shader_pointer(struct radv_device *device,
}
}
+static inline void
+radv_emit_shader_pointer(struct radv_device *device,
+struct radeon_winsys_cs *cs,
+uint32_t sh_offset, uint64_t va, bool global)
+{
+ bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
+
+ radv_emit_shader_pointer_head(cs, sh_offset, use_32bit_pointers);
+ radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
+}
+
static inline struct radv_descriptor_state *
radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allow radv_emit_shader_pointer_head() to emit more pointers
Module: Mesa
Branch: master
Commit: 21baf33a942fafaccfaf9c802d0148f31b1b36ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21baf33a942fafaccfaf9c802d0148f31b1b36ef
Author: Samuel Pitoiset
Date: Fri May 25 14:59:20 2018 +0200
radv: allow radv_emit_shader_pointer_head() to emit more pointers
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_private.h | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e554fc7acc..708cacf770 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1132,9 +1132,11 @@ bool radv_get_memory_fd(struct radv_device *device,
static inline void
radv_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
- unsigned sh_offset, bool use_32bit_pointers)
+ unsigned sh_offset, unsigned pointer_count,
+ bool use_32bit_pointers)
{
- radeon_set_sh_reg_seq(cs, sh_offset, use_32bit_pointers ? 1 : 2);
+ radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count *
(use_32bit_pointers ? 1 : 2), 0));
+ radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
}
static inline void
@@ -1159,7 +1161,7 @@ radv_emit_shader_pointer(struct radv_device *device,
{
bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
- radv_emit_shader_pointer_head(cs, sh_offset, use_32bit_pointers);
+ radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: emit shader descriptor pointers consecutively
Module: Mesa
Branch: master
Commit: 88d1ed0f818930fd37ea012893405f21ef1b78ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88d1ed0f818930fd37ea012893405f21ef1b78ea
Author: Samuel Pitoiset
Date: Fri May 25 14:59:21 2018 +0200
radv: emit shader descriptor pointers consecutively
This reduces the number of SET_SH_REG packets which are emitted
for applications that use more than one descriptor set per stage.
We should be able to emit more SET_SH_REG packets consecutively
(like push constants and vertex buffers for the vertex stage),
but this will be improved later.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 104 +--
1 file changed, 57 insertions(+), 47 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3e3dbf6a85..8f351b52c9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -595,6 +595,46 @@ radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer,
}
static void
+radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_pipeline *pipeline,
+ struct radv_descriptor_state *descriptors_state,
+ gl_shader_stage stage)
+{
+ struct radv_device *device = cmd_buffer->device;
+ struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ uint32_t sh_base = pipeline->user_data_0[stage];
+ struct radv_userdata_locations *locs =
+ &pipeline->shaders[stage]->info.user_sgprs_locs;
+ unsigned mask;
+
+ mask = descriptors_state->dirty & descriptors_state->valid;
+
+ for (int i = 0; i < MAX_SETS; i++) {
+ struct radv_userdata_info *loc = &locs->descriptor_sets[i];
+ if (loc->sgpr_idx != -1 && !loc->indirect)
+ continue;
+ mask &= ~(1 << i);
+ }
+
+ while (mask) {
+ int start, count;
+
+ u_bit_scan_consecutive_range(&mask, &start, &count);
+
+ struct radv_userdata_info *loc = &locs->descriptor_sets[start];
+ unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
+
+ radv_emit_shader_pointer_head(cs, sh_offset, count, true);
+ for (int i = 0; i < count; i++) {
+ struct radv_descriptor_set *set =
+ descriptors_state->sets[start + i];
+
+ radv_emit_shader_pointer_body(device, cs, set->va,
true);
+ }
+ }
+}
+
+static void
radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
{
@@ -1423,47 +1463,6 @@ radv_cmd_buffer_flush_dynamic_state(struct
radv_cmd_buffer *cmd_buffer)
}
static void
-emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
- int idx,
- uint64_t va,
- gl_shader_stage stage)
-{
- struct radv_userdata_info *desc_set_loc =
&pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
- uint32_t base_reg = pipeline->user_data_0[stage];
-
- if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
- return;
-
- assert(!desc_set_loc->indirect);
- assert(desc_set_loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
-
- radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
-base_reg + desc_set_loc->sgpr_idx * 4, va,
false);
-}
-
-static void
-radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
- VkShaderStageFlags stages,
- struct radv_descriptor_set *set,
- unsigned idx)
-{
- if (cmd_buffer->state.pipeline) {
- radv_foreach_stage(stage, stages) {
- if (cmd_buffer->state.pipeline->shaders[stage])
- emit_stage_descriptor_set_userdata(cmd_buffer,
cmd_buffer->state.pipeline,
- idx, set->va,
- stage);
- }
- }
-
- if (cmd_buffer->state.compute_pipeline && (stages &
VK_SHADER_STAGE_COMPUTE_BIT))
- emit_stage_descriptor_set_userdata(cmd_buffer,
cmd_buffer->state.compute_pipeline,
- idx, set->va,
- MESA_SHADER_COMPUTE);
-}
-
-static void
radv_flush_pus
Mesa (master): radv: run the EarlyCSEMemSSA LLVM pass
Module: Mesa Branch: master Commit: 45eb24fedf5b790237263d79d72cd1e433931b87 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45eb24fedf5b790237263d79d72cd1e433931b87 Author: Samuel Pitoiset Date: Thu May 24 22:55:54 2018 +0200 radv: run the EarlyCSEMemSSA LLVM pass It's recommended by the instruction combining pass, and RadeonSI also runs it. This pass used to segfault with one shader of F12017 in the past, but it no longer crashes. Maybe the LLVM IR generated by RADV has changed. Polaris10: Totals from affected shaders: SGPRS: 441352 -> 441648 (0.07 %) VGPRS: 310888 -> 300784 (-3.25 %) Spilled SGPRs: 13576 -> 12983 (-4.37 %) Code Size: 22560328 -> 22420544 (-0.62 %) bytes Max Waves: 40755 -> 41366 (1.50 %) Vega10: Totals from affected shaders: SGPRS: 442848 -> 442000 (-0.19 %) VGPRS: 310396 -> 300460 (-3.20 %) Spilled SGPRs: 13708 -> 12906 (-5.85 %) Code Size: 22479428 -> 22336216 (-0.64 %) bytes Max Waves: 45783 -> 46506 (1.58 %) Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index b174c027d9..a56f017e25 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -2982,6 +2982,8 @@ static void ac_llvm_finalize_module(struct radv_shader_context *ctx) LLVMAddLICMPass(passmgr); LLVMAddAggressiveDCEPass(passmgr); LLVMAddCFGSimplificationPass(passmgr); + /* This is recommended by the instruction combining pass. */ + LLVMAddEarlyCSEMemSSAPass(passmgr); LLVMAddInstructionCombiningPass(passmgr); /* Run the pass */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_dump_pipeline_state() helper
Module: Mesa
Branch: master
Commit: de06dfa9ea05ab5d06efb20223a858eb42d02683
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de06dfa9ea05ab5d06efb20223a858eb42d02683
Author: Samuel Pitoiset
Date: Thu May 24 13:09:13 2018 +0200
radv: add radv_dump_pipeline_state() helper
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 5cdbf5bea9..c84e3be25b 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -526,6 +526,15 @@ radv_dump_shaders(struct radv_pipeline *pipeline,
}
static void
+radv_dump_pipeline_state(struct radv_pipeline *pipeline,
+VkShaderStageFlagBits active_stages, FILE *f)
+{
+ radv_dump_shaders(pipeline, active_stages, f);
+ radv_dump_annotated_shaders(pipeline, active_stages, f);
+ radv_dump_descriptors(pipeline, f);
+}
+
+static void
radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
struct radv_pipeline *compute_pipeline, FILE *f)
{
@@ -536,9 +545,7 @@ radv_dump_graphics_state(struct radv_pipeline
*graphics_pipeline,
active_stages = graphics_pipeline->active_stages;
- radv_dump_shaders(graphics_pipeline, active_stages, f);
- radv_dump_annotated_shaders(graphics_pipeline, active_stages, f);
- radv_dump_descriptors(graphics_pipeline, f);
+ radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
}
static void
@@ -549,9 +556,7 @@ radv_dump_compute_state(struct radv_pipeline
*compute_pipeline, FILE *f)
if (!compute_pipeline)
return;
- radv_dump_shaders(compute_pipeline, active_stages, f);
- radv_dump_annotated_shaders(compute_pipeline, active_stages, f);
- radv_dump_descriptors(compute_pipeline, f);
+ radv_dump_pipeline_state(compute_pipeline, active_stages, f);
}
static struct radv_pipeline *
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix dumping compute shader on the graphics queue
Module: Mesa
Branch: master
Commit: 66e38654c9fef548b9f5a77f0d376aea57b89b50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=66e38654c9fef548b9f5a77f0d376aea57b89b50
Author: Samuel Pitoiset
Date: Thu May 24 13:09:14 2018 +0200
radv: fix dumping compute shader on the graphics queue
The graphics pipeline can be NULL.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index c84e3be25b..5a9b43644e 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -540,12 +540,15 @@ radv_dump_graphics_state(struct radv_pipeline
*graphics_pipeline,
{
VkShaderStageFlagBits active_stages;
- if (!graphics_pipeline)
- return;
-
- active_stages = graphics_pipeline->active_stages;
+ if (graphics_pipeline) {
+ active_stages = graphics_pipeline->active_stages;
+ radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
+ }
- radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
+ if (compute_pipeline) {
+ active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+ radv_dump_pipeline_state(compute_pipeline, active_stages, f);
+ }
}
static void
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: rework how shaders are dumped when generating a hang report
Module: Mesa
Branch: master
Commit: 6f0530ecfe9cfe4349dab197397df92dd967c50c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f0530ecfe9cfe4349dab197397df92dd967c50c
Author: Samuel Pitoiset
Date: Thu May 24 13:09:12 2018 +0200
radv: rework how shaders are dumped when generating a hang report
Use a flag for the active stages instead.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.c | 41 +++--
1 file changed, 15 insertions(+), 26 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 72c7c39fcb..5cdbf5bea9 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -442,28 +442,22 @@ radv_dump_annotated_shader(struct radv_shader_variant
*shader,
static void
radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
- struct radv_shader_variant *compute_shader,
- FILE *f)
+ VkShaderStageFlagBits active_stages, FILE *f)
{
struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
unsigned num_waves = ac_get_wave_info(waves);
- unsigned mask;
fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
"\n\n", num_waves);
/* Dump annotated active graphics shaders. */
- mask = pipeline->active_stages;
- while (mask) {
- int stage = u_bit_scan(&mask);
+ while (active_stages) {
+ int stage = u_bit_scan(&active_stages);
radv_dump_annotated_shader(pipeline->shaders[stage],
stage, waves, num_waves, f);
}
- radv_dump_annotated_shader(compute_shader, MESA_SHADER_COMPUTE, waves,
- num_waves, f);
-
/* Print waves executing shaders that are not currently bound. */
unsigned i;
bool found = false;
@@ -521,47 +515,42 @@ radv_dump_shader(struct radv_pipeline *pipeline,
static void
radv_dump_shaders(struct radv_pipeline *pipeline,
- struct radv_shader_variant *compute_shader, FILE *f)
+ VkShaderStageFlagBits active_stages, FILE *f)
{
- unsigned mask;
-
/* Dump active graphics shaders. */
- mask = pipeline->active_stages;
- while (mask) {
- int stage = u_bit_scan(&mask);
+ while (active_stages) {
+ int stage = u_bit_scan(&active_stages);
radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
}
-
- radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
}
static void
radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
struct radv_pipeline *compute_pipeline, FILE *f)
{
- struct radv_shader_variant *compute_shader =
- compute_pipeline ?
compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
+ VkShaderStageFlagBits active_stages;
if (!graphics_pipeline)
return;
- radv_dump_shaders(graphics_pipeline, compute_shader, f);
- radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
+ active_stages = graphics_pipeline->active_stages;
+
+ radv_dump_shaders(graphics_pipeline, active_stages, f);
+ radv_dump_annotated_shaders(graphics_pipeline, active_stages, f);
radv_dump_descriptors(graphics_pipeline, f);
}
static void
radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
{
+ VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+
if (!compute_pipeline)
return;
- radv_dump_shaders(compute_pipeline,
- compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
- radv_dump_annotated_shaders(compute_pipeline,
-
compute_pipeline->shaders[MESA_SHADER_COMPUTE],
- f);
+ radv_dump_shaders(compute_pipeline, active_stages, f);
+ radv_dump_annotated_shaders(compute_pipeline, active_stages, f);
radv_dump_descriptors(compute_pipeline, f);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove unused parameter in radv_dump_annotated_shader()
Module: Mesa
Branch: master
Commit: 8c406f0b4d904867058deb4e19acd69fd2c38c91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c406f0b4d904867058deb4e19acd69fd2c38c91
Author: Samuel Pitoiset
Date: Thu May 24 13:09:11 2018 +0200
radv: remove unused parameter in radv_dump_annotated_shader()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index e55489d71d..72c7c39fcb 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -369,11 +369,9 @@ static void si_add_split_disasm(const char *disasm,
}
static void
-radv_dump_annotated_shader(struct radv_pipeline *pipeline,
- struct radv_shader_variant *shader,
- gl_shader_stage stage,
- struct ac_wave_info *waves, unsigned num_waves,
- FILE *f)
+radv_dump_annotated_shader(struct radv_shader_variant *shader,
+ gl_shader_stage stage, struct ac_wave_info *waves,
+ unsigned num_waves, FILE *f)
{
uint64_t start_addr, end_addr;
unsigned i;
@@ -459,12 +457,12 @@ radv_dump_annotated_shaders(struct radv_pipeline
*pipeline,
while (mask) {
int stage = u_bit_scan(&mask);
- radv_dump_annotated_shader(pipeline, pipeline->shaders[stage],
+ radv_dump_annotated_shader(pipeline->shaders[stage],
stage, waves, num_waves, f);
}
- radv_dump_annotated_shader(pipeline, compute_shader,
- MESA_SHADER_COMPUTE, waves, num_waves, f);
+ radv_dump_annotated_shader(compute_shader, MESA_SHADER_COMPUTE, waves,
+ num_waves, f);
/* Print waves executing shaders that are not currently bound. */
unsigned i;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: call nir_lower_io_to_temporaries for VS, GS, TES and FS
Module: Mesa
Branch: master
Commit: 38a8c5903be787b203ec6586e6ce5f9cc8a5a6cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38a8c5903be787b203ec6586e6ce5f9cc8a5a6cf
Author: Samuel Pitoiset
Date: Wed May 23 14:31:56 2018 +0200
radv: call nir_lower_io_to_temporaries for VS, GS, TES and FS
Do not lower FS inputs because this moves all load_var
instructions at beginning of shaders and because
interp_var_at_sample (and friends) seem broken. That might
be eventually enabled later on if we really want to preload
all FS inputs at beginning.
Polaris10:
Totals from affected shaders:
SGPRS: 54072 -> 54264 (0.36 %)
VGPRS: 38580 -> 38124 (-1.18 %)
Spilled SGPRs: 652 -> 652 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 2128116 -> 2127380 (-0.03 %) bytes
Max Waves: 8048 -> 8086 (0.47 %)
Vega10:
Totals from affected shaders:
SGPRS: 52616 -> 52656 (0.08 %)
VGPRS: 37536 -> 37116 (-1.12 %)
Spilled SGPRs: 828 -> 828 (0.00 %)
Code Size: 2043756 -> 2042672 (-0.05 %) bytes
Max Waves: 9176 -> 9254 (0.85 %)
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7ed5d2a421..84ad215ccb 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -278,6 +278,16 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_lower_vars_to_ssa(nir);
+ if (nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_GEOMETRY) {
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir), true, true);
+ } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
+ nir->info.stage == MESA_SHADER_FRAGMENT) {
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir), true, false);
+ }
+
nir_split_var_copies(nir);
nir_lower_var_copies(nir);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: call nir_split_var_copies() before nir_lower_var_copies()
Module: Mesa
Branch: master
Commit: ded150958740e47cb7bc4ba868289b88268f666c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ded150958740e47cb7bc4ba868289b88268f666c
Author: Samuel Pitoiset
Date: Wed May 23 14:31:55 2018 +0200
radv: call nir_split_var_copies() before nir_lower_var_copies()
This doesn't nothing special currently because we don't create
any copy_var instructions, but this is needed for the next patch.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6ccbe81eff..7ed5d2a421 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -277,7 +277,10 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_lower_tex(nir, &tex_options);
nir_lower_vars_to_ssa(nir);
+
+ nir_split_var_copies(nir);
nir_lower_var_copies(nir);
+
nir_lower_global_vars_to_local(nir);
nir_remove_dead_variables(nir, nir_var_local);
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: set amdgpu-32bit-address-high-bits LLVM attribute
Module: Mesa
Branch: master
Commit: d8a61d32322b2a12bb431d217c5798d8234d6c13
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8a61d32322b2a12bb431d217c5798d8234d6c13
Author: Samuel Pitoiset
Date: Wed May 16 16:02:04 2018 +0200
radv: set amdgpu-32bit-address-high-bits LLVM attribute
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 6 ++
src/amd/vulkan/radv_shader.c | 1 +
src/amd/vulkan/radv_shader.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 2d91ded7fe..3f32f62cdc 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -511,6 +511,12 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef
module,
}
}
+ if (options->address32_hi) {
+ ac_llvm_add_target_dep_function_attr(main_function,
+
"amdgpu-32bit-address-high-bits",
+options->address32_hi);
+ }
+
if (max_workgroup_size) {
ac_llvm_add_target_dep_function_attr(main_function,
"amdgpu-max-work-group-size",
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7589d9c88a..6ccbe81eff 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -482,6 +482,7 @@ shader_variant_create(struct radv_device *device,
device->instance->debug_flags &
RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info;
options->tess_offchip_block_dw_size =
device->tess_offchip_block_dw_size;
+ options->address32_hi = device->physical_device->rad_info.address32_hi;
if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 679fa44279..05de188e3f 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -123,6 +123,7 @@ struct radv_nir_compiler_options {
enum radeon_family family;
enum chip_class chip_class;
uint32_t tess_offchip_block_dw_size;
+ uint32_t address32_hi;
};
enum radv_ud_index {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv/winsys: allow to allocate BOs in the 32-bit addr space
Module: Mesa
Branch: master
Commit: fe2649d3ad7dbf47000f2e1403c3c279d09f7dc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe2649d3ad7dbf47000f2e1403c3c279d09f7dc0
Author: Samuel Pitoiset
Date: Wed May 16 15:34:52 2018 +0200
radv/winsys: allow to allocate BOs in the 32-bit addr space
This introduces a new flag called RADEON_FLAG_32BIT.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_radeon_winsys.h | 1 +
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_radeon_winsys.h
b/src/amd/vulkan/radv_radeon_winsys.h
index 7f19934ab8..2ebd18cf90 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -57,6 +57,7 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
RADEON_FLAG_READ_ONLY = (1 << 7),
+ RADEON_FLAG_32BIT = (1 << 8),
};
enum radeon_bo_usage { /* bitfield */
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index f33cf02815..25764d93f6 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -306,7 +306,8 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
size, alignment, 0, &va, &va_handle,
- AMDGPU_VA_RANGE_HIGH);
+ (flags & RADEON_FLAG_32BIT ?
AMDGPU_VA_RANGE_32_BIT : 0) |
+ AMDGPU_VA_RANGE_HIGH);
if (r)
goto error_va_alloc;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add set_loc_shader_ptr() helper
Module: Mesa
Branch: master
Commit: b654ef5808e12a877f4645cf1394f56f954d0a50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b654ef5808e12a877f4645cf1394f56f954d0a50
Author: Samuel Pitoiset
Date: Fri May 18 10:57:02 2018 +0200
radv: add set_loc_shader_ptr() helper
This helper will hep for switching to 32-bit GPU pointers.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 3f32f62cdc..9e42983cd1 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -567,6 +567,12 @@ set_loc_shader(struct radv_shader_context *ctx, int idx,
uint8_t *sgpr_idx,
}
static void
+set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
+{
+ set_loc_shader(ctx, idx, sgpr_idx, 2);
+}
+
+static void
set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
uint32_t indirect_offset)
{
@@ -797,8 +803,8 @@ set_global_input_locs(struct radv_shader_context *ctx,
gl_shader_stage stage,
ctx->descriptor_sets[i] = NULL;
}
} else {
- set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
- user_sgpr_idx, 2);
+ set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
+ user_sgpr_idx);
for (unsigned i = 0; i < num_sets; ++i) {
if ((ctx->shader_info->info.desc_set_used_mask & (1 <<
i)) &&
@@ -816,7 +822,7 @@ set_global_input_locs(struct radv_shader_context *ctx,
gl_shader_stage stage,
}
if (ctx->shader_info->info.loads_push_constants) {
- set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
+ set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
}
}
@@ -830,8 +836,8 @@ set_vs_specific_input_locs(struct radv_shader_context *ctx,
(stage == MESA_SHADER_VERTEX ||
(has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
if (ctx->shader_info->info.vs.has_vertex_buffers) {
- set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
- user_sgpr_idx, 2);
+ set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
+ user_sgpr_idx);
}
unsigned vs_num = 2;
@@ -1129,8 +1135,8 @@ static void create_function(struct radv_shader_context
*ctx,
user_sgpr_idx = 0;
if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
- set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
- &user_sgpr_idx, 2);
+ set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
+ &user_sgpr_idx);
if (ctx->options->supports_spill) {
ctx->ring_offsets = ac_build_intrinsic(&ctx->ac,
"llvm.amdgcn.implicit.buffer.ptr",
LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add support for 32-bit pointers in user data SGPRs
Module: Mesa
Branch: master
Commit: 36a4d6d08164344cbb4766944b3c45b2b223cf22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36a4d6d08164344cbb4766944b3c45b2b223cf22
Author: Samuel Pitoiset
Date: Wed May 16 17:40:47 2018 +0200
radv: add support for 32-bit pointers in user data SGPRs
We still use 64-bit GPU pointers for all ring buffers because
llvm.amdgcn.implicit.buffer.ptr doesn't seem to support 32-bit
GPU pointers for now. This can be improved later anyways.
Vega10:
Totals from affected shaders:
SGPRS: 1008722 -> 1026710 (1.78 %)
VGPRS: 706580 -> 707136 (0.08 %)
Spilled SGPRs: 22555 -> 22209 (-1.53 %)
Spilled VGPRs: 75 -> 75 (0.00 %)
Code Size: 34819208 -> 35202140 (1.10 %) bytes
Max Waves: 175423 -> 175086 (-0.19 %)
Polaris10:
Totals from affected shaders:
SGPRS: 1029849 -> 1036517 (0.65 %)
VGPRS: 709984 -> 708872 (-0.16 %)
Spilled SGPRs: 22672 -> 22309 (-1.60 %)
Spilled VGPRs: 82 -> 66 (-19.51 %)
Scratch size: 76 -> 60 (-21.05 %) dwords per thread
Code Size: 34915336 -> 35309752 (1.13 %) bytes
Max Waves: 151221 -> 151677 (0.30 %)
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 13 +++--
src/amd/vulkan/radv_device.c | 6 --
src/amd/vulkan/radv_nir_to_llvm.c | 24 +++-
src/amd/vulkan/radv_private.h | 18 ++
4 files changed, 40 insertions(+), 21 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3636b2c8d9..5ab577b4c5 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -586,11 +586,12 @@ radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer,
uint32_t base_reg = pipeline->user_data_0[stage];
if (loc->sgpr_idx == -1)
return;
- assert(loc->num_sgprs == 2);
+
+ assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
assert(!loc->indirect);
- radv_emit_shader_pointer(cmd_buffer->cs,
-base_reg + loc->sgpr_idx * 4, va);
+ radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
+base_reg + loc->sgpr_idx * 4, va, false);
}
static void
@@ -1442,10 +1443,10 @@ emit_stage_descriptor_set_userdata(struct
radv_cmd_buffer *cmd_buffer,
return;
assert(!desc_set_loc->indirect);
- assert(desc_set_loc->num_sgprs == 2);
+ assert(desc_set_loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
- radv_emit_shader_pointer(cmd_buffer->cs,
-base_reg + desc_set_loc->sgpr_idx * 4, va);
+ radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
+base_reg + desc_set_loc->sgpr_idx * 4, va,
false);
}
static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d6abab338e..61b4fba23f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1963,7 +1963,8 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
- radv_emit_shader_pointer(cs, regs[i], va);
+ radv_emit_shader_pointer(queue->device, cs, regs[i],
+va, true);
}
} else {
uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1974,7 +1975,8 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B530_SPI_SHADER_USER_DATA_LS_0};
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
- radv_emit_shader_pointer(cs, regs[i], va);
+ radv_emit_shader_pointer(queue->device, cs, regs[i],
+va, true);
}
}
}
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9e42983cd1..c2cc5038b8 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -569,7 +569,10 @@ set_loc_shader(struct radv_shader_context *ctx, int idx,
uint8_t *sgpr_idx,
static void
set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
{
- set_loc_shader(ctx, idx, sgpr_idx, 2);
+ bool use_32bit_pointers = HAVE_32BIT_POINTERS &&
+ idx != AC_UD_SCRATCH_RING_OFFSETS;
+
+ set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
}
static void
@@ -580,7 +583,7 @@ set_loc_desc(struct radv_shader_context *ctx, int idx,
uint8_t *sgpr_idx,
&ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
assert(ud_info);
- set_loc(ud_info
Mesa (master): radv: allocate the upload BO in the 32-bit addr space
Module: Mesa
Branch: master
Commit: 0d1406ad12c7d47fe8deccd58ecb1727754b1891
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d1406ad12c7d47fe8deccd58ecb1727754b1891
Author: Samuel Pitoiset
Date: Wed May 16 17:32:38 2018 +0200
radv: allocate the upload BO in the 32-bit addr space
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a8359ac092..3636b2c8d9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -347,7 +347,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer,
new_size, 4096,
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS|
- RADEON_FLAG_NO_INTERPROCESS_SHARING);
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ RADEON_FLAG_32BIT);
if (!bo) {
cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv/winsys: request high address
Module: Mesa Branch: master Commit: b60e0ee789e52417005bde45d95e051624502450 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b60e0ee789e52417005bde45d95e051624502450 Author: Samuel Pitoiset Date: Fri May 18 13:59:46 2018 +0200 radv/winsys: request high address This is needed for 32-bit GPU pointers. Ported from RadeonSI. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c index 8ed3e53e2d..f33cf02815 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c @@ -38,7 +38,6 @@ #include "util/u_atomic.h" - static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo); static int @@ -306,7 +305,8 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, } r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - size, alignment, 0, &va, &va_handle, 0); + size, alignment, 0, &va, &va_handle, + AMDGPU_VA_RANGE_HIGH); if (r) goto error_va_alloc; @@ -424,7 +424,8 @@ radv_amdgpu_winsys_bo_from_ptr(struct radeon_winsys *_ws, goto error; if (amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - size, 1 << 12, 0, &va, &va_handle, 0)) + size, 1 << 12, 0, &va, &va_handle, + AMDGPU_VA_RANGE_HIGH)) goto error_va_alloc; if (amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP)) @@ -480,7 +481,8 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, goto error_query; r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - result.alloc_size, 1 << 20, 0, &va, &va_handle, 0); + result.alloc_size, 1 << 20, 0, &va, &va_handle, + AMDGPU_VA_RANGE_HIGH); if (r) goto error_query; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix computation of user sgprs for 32-bit pointers
Module: Mesa
Branch: master
Commit: 75e919c0454dcc759dce69c46717356980f18fd8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75e919c0454dcc759dce69c46717356980f18fd8
Author: Samuel Pitoiset
Date: Mon May 21 16:57:54 2018 +0200
radv: fix computation of user sgprs for 32-bit pointers
With 32-bit pointers we only need one user SGPR per desc set.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 39692e99fd..b174c027d9 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -694,8 +694,10 @@ static void allocate_user_sgprs(struct radv_shader_context
*ctx,
uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
+ uint32_t num_desc_set =
+ util_bitcount(ctx->shader_info->info.desc_set_used_mask);
- if (remaining_sgprs / 2 <
util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
+ if (remaining_sgprs / (HAVE_32BIT_POINTERS ? 1 : 2) < num_desc_set) {
user_sgpr_info->indirect_all_descriptor_sets = true;
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: drop user_sgpr_info::sgpr_count
Module: Mesa
Branch: master
Commit: c5536fc8130f96d3990536852c129ae52a0e8351
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5536fc8130f96d3990536852c129ae52a0e8351
Author: Samuel Pitoiset
Date: Mon May 21 16:57:53 2018 +0200
radv: drop user_sgpr_info::sgpr_count
It's only used inside allocate_user_sgprs().
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index c2cc5038b8..39692e99fd 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -588,7 +588,6 @@ set_loc_desc(struct radv_shader_context *ctx, int idx,
uint8_t *sgpr_idx,
struct user_sgpr_info {
bool need_ring_offsets;
- uint8_t sgpr_count;
bool indirect_all_descriptor_sets;
};
@@ -635,6 +634,8 @@ static void allocate_user_sgprs(struct radv_shader_context
*ctx,
bool needs_view_index,
struct user_sgpr_info *user_sgpr_info)
{
+ uint8_t user_sgpr_count = 0;
+
memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
/* until we sort out scratch/global buffers always assign ring offsets
for gs/vs/es */
@@ -651,25 +652,25 @@ static void allocate_user_sgprs(struct
radv_shader_context *ctx,
/* 2 user sgprs will nearly always be allocated for scratch/rings */
if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
- user_sgpr_info->sgpr_count += 2;
+ user_sgpr_count += 2;
}
switch (stage) {
case MESA_SHADER_COMPUTE:
if (ctx->shader_info->info.cs.uses_grid_size)
- user_sgpr_info->sgpr_count += 3;
+ user_sgpr_count += 3;
break;
case MESA_SHADER_FRAGMENT:
- user_sgpr_info->sgpr_count +=
ctx->shader_info->info.ps.needs_sample_positions;
+ user_sgpr_count +=
ctx->shader_info->info.ps.needs_sample_positions;
break;
case MESA_SHADER_VERTEX:
if (!ctx->is_gs_copy_shader)
- user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
+ user_sgpr_count += count_vs_user_sgprs(ctx);
break;
case MESA_SHADER_TESS_CTRL:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX)
- user_sgpr_info->sgpr_count +=
count_vs_user_sgprs(ctx);
+ user_sgpr_count += count_vs_user_sgprs(ctx);
}
break;
case MESA_SHADER_TESS_EVAL:
@@ -677,7 +678,7 @@ static void allocate_user_sgprs(struct radv_shader_context
*ctx,
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX) {
- user_sgpr_info->sgpr_count +=
count_vs_user_sgprs(ctx);
+ user_sgpr_count += count_vs_user_sgprs(ctx);
}
}
break;
@@ -686,19 +687,16 @@ static void allocate_user_sgprs(struct
radv_shader_context *ctx,
}
if (needs_view_index)
- user_sgpr_info->sgpr_count++;
+ user_sgpr_count++;
if (ctx->shader_info->info.loads_push_constants)
- user_sgpr_info->sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
+ user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
- uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
+ uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
if (remaining_sgprs / 2 <
util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
- user_sgpr_info->sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2;
user_sgpr_info->indirect_all_descriptor_sets = true;
- } else {
- user_sgpr_info->sgpr_count +=
util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allocate descriptor BOs in the 32-bit addr space
Module: Mesa Branch: master Commit: 14a7547c0865b93b210df6a8f47cc793be6689b8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=14a7547c0865b93b210df6a8f47cc793be6689b8 Author: Samuel Pitoiset Date: Wed May 16 17:32:57 2018 +0200 radv: allocate descriptor BOs in the 32-bit addr space Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_descriptor_set.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 9d783b8b6d..27dd5b08e2 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -594,7 +594,8 @@ VkResult radv_CreateDescriptorPool( pool->bo = device->ws->buffer_create(device->ws, bo_size, 32, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING | -RADEON_FLAG_READ_ONLY); +RADEON_FLAG_READ_ONLY | +RADEON_FLAG_32BIT); pool->mapped_ptr = (uint8_t*)device->ws->buffer_map(pool->bo); } pool->size = bo_size; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix centroid interpolation
Module: Mesa
Branch: master
Commit: 73df16dcee79e2281c8d8a830dbbe6655359c82d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73df16dcee79e2281c8d8a830dbbe6655359c82d
Author: Samuel Pitoiset
Date: Mon May 21 11:15:51 2018 +0200
radv: fix centroid interpolation
It's legal to set the centroid and sample interpolation modes
when MSAA disabled. So, we have to initialize the centroid
inputs because the hardware doesn't.
This fixes rendering issues with DXVK and The Witness, World of
Warcraft, Trackmania and probably more games.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106315
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102390
CC: 18.0 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9b9619b877..2d91ded7fe 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2075,9 +2075,6 @@ static void
prepare_interp_optimize(struct radv_shader_context *ctx,
struct nir_shader *nir)
{
- if (!ctx->options->key.fs.multisample)
- return;
-
bool uses_center = false;
bool uses_centroid = false;
nir_foreach_variable(variable, &nir->inputs) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: pass radv_nir_compiler_options directly to create_llvm_function()
Module: Mesa
Branch: master
Commit: 03c4816093b5ca1f72436fdb9576893690cfdd0e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03c4816093b5ca1f72436fdb9576893690cfdd0e
Author: Samuel Pitoiset
Date: Fri May 18 10:43:06 2018 +0200
radv: pass radv_nir_compiler_options directly to create_llvm_function()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 1384bf0bdb..9b9619b877 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -480,7 +480,7 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef
module,
unsigned num_return_elems,
struct arg_info *args,
unsigned max_workgroup_size,
-bool unsafe_math)
+const struct radv_nir_compiler_options *options)
{
LLVMTypeRef main_function_type, ret_type;
LLVMBasicBlockRef main_function_body;
@@ -516,7 +516,7 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef
module,
"amdgpu-max-work-group-size",
max_workgroup_size);
}
- if (unsafe_math) {
+ if (options->unsafe_math) {
/* These were copied from some LLVM test. */
LLVMAddTargetDependentFunctionAttr(main_function,
"less-precise-fpmad",
@@ -1106,8 +1106,7 @@ static void create_function(struct radv_shader_context
*ctx,
ctx->main_function = create_llvm_function(
ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
- ctx->max_workgroup_size,
- ctx->options->unsafe_math);
+ ctx->max_workgroup_size, ctx->options);
set_llvm_calling_convention(ctx->main_function, stage);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_emit_shader_pointer() helper
Module: Mesa
Branch: master
Commit: fcba3934fc138d6b9bfa911bd6c8f1155f577b58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcba3934fc138d6b9bfa911bd6c8f1155f577b58
Author: Samuel Pitoiset
Date: Thu May 17 14:08:43 2018 +0200
radv: add radv_emit_shader_pointer() helper
For future work (support for 32-bit GPU pointers).
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 13 ++---
src/amd/vulkan/radv_device.c | 8 ++--
src/amd/vulkan/radv_private.h| 10 ++
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ca687494a..a8359ac092 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer,
return;
assert(loc->num_sgprs == 2);
assert(!loc->indirect);
- radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
- radeon_emit(cmd_buffer->cs, va);
- radeon_emit(cmd_buffer->cs, va >> 32);
+
+ radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + loc->sgpr_idx * 4, va);
}
static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct
radv_cmd_buffer *cmd_buffer,
assert(!desc_set_loc->indirect);
assert(desc_set_loc->num_sgprs == 2);
- radeon_set_sh_reg_seq(cmd_buffer->cs,
- base_reg + desc_set_loc->sgpr_idx * 4, 2);
- radeon_emit(cmd_buffer->cs, va);
- radeon_emit(cmd_buffer->cs, va >> 32);
+
+ radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + desc_set_loc->sgpr_idx * 4, va);
}
static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7067f5b01d..c52b3a591f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1963,9 +1963,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
- radeon_set_sh_reg_seq(cs, regs[i], 2);
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
+ radv_emit_shader_pointer(cs, regs[i], va);
}
} else {
uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1976,9 +1974,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B530_SPI_SHADER_USER_DATA_LS_0};
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
- radeon_set_sh_reg_seq(cs, regs[i], 2);
- radeon_emit(cs, va);
- radeon_emit(cs, va >> 32);
+ radv_emit_shader_pointer(cs, regs[i], va);
}
}
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 304ed17f01..adfd75c2a8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -59,6 +59,7 @@
#include "ac_surface.h"
#include "radv_descriptor_set.h"
#include "radv_extensions.h"
+#include "radv_cs.h"
#include
@@ -1128,6 +1129,15 @@ bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
+static inline void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+uint32_t sh_offset, uint64_t va)
+{
+ radeon_set_sh_reg_seq(cs, sh_offset, 2);
+ radeon_emit(cs, va);
+ radeon_emit(cs, va >> 32);
+}
+
static inline struct radv_descriptor_state *
radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add some helpers for cleaning up radv_get_preamble_cs()
Module: Mesa
Branch: master
Commit: 9b2c310a70c5be08debae3ed5054a5619914ef5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b2c310a70c5be08debae3ed5054a5619914ef5d
Author: Samuel Pitoiset
Date: Thu May 17 10:11:44 2018 +0200
radv: add some helpers for cleaning up radv_get_preamble_cs()
Because this function looks a bit ugly to me.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 214 ++-
1 file changed, 128 insertions(+), 86 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 51b44cc222..7067f5b01d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1861,6 +1861,128 @@ radv_get_hs_offchip_param(struct radv_device *device,
uint32_t *max_offchip_buff
return hs_offchip_param;
}
+static void
+radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+ struct radeon_winsys_bo *esgs_ring_bo,
+ uint32_t esgs_ring_size,
+ struct radeon_winsys_bo *gsvs_ring_bo,
+ uint32_t gsvs_ring_size)
+{
+ if (!esgs_ring_bo && !gsvs_ring_bo)
+ return;
+
+ if (esgs_ring_bo)
+ radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
+
+ if (gsvs_ring_bo)
+ radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
+
+ if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+ radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
+ radeon_emit(cs, esgs_ring_size >> 8);
+ radeon_emit(cs, gsvs_ring_size >> 8);
+ } else {
+ radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
+ radeon_emit(cs, esgs_ring_size >> 8);
+ radeon_emit(cs, gsvs_ring_size >> 8);
+ }
+}
+
+static void
+radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs
*cs,
+ unsigned hs_offchip_param, unsigned tf_ring_size,
+ struct radeon_winsys_bo *tess_rings_bo)
+{
+ uint64_t tf_va;
+
+ if (!tess_rings_bo)
+ return;
+
+ tf_va = radv_buffer_get_va(tess_rings_bo);
+
+ radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
+
+ if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+ radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
+ S_030938_SIZE(tf_ring_size / 4));
+ radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
+ tf_va >> 8);
+ if (queue->device->physical_device->rad_info.chip_class >=
GFX9) {
+ radeon_set_uconfig_reg(cs,
R_030944_VGT_TF_MEMORY_BASE_HI,
+ S_030944_BASE_HI(tf_va >> 40));
+ }
+ radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
+ hs_offchip_param);
+ } else {
+ radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
+ S_008988_SIZE(tf_ring_size / 4));
+ radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
+ tf_va >> 8);
+ radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+hs_offchip_param);
+ }
+}
+
+static void
+radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs
*cs,
+ struct radeon_winsys_bo *compute_scratch_bo)
+{
+ uint64_t scratch_va;
+
+ if (!compute_scratch_bo)
+ return;
+
+ scratch_va = radv_buffer_get_va(compute_scratch_bo);
+
+ radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
+
+ radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
+ radeon_emit(cs, scratch_va);
+ radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
+ S_008F04_SWIZZLE_ENABLE(1));
+}
+
+static void
+radv_emit_global_shader_pointers(struct radv_queue *queue,
+struct radeon_winsys_cs *cs,
+struct radeon_winsys_bo *descriptor_bo)
+{
+ uint64_t va;
+
+ if (!descriptor_bo)
+ return;
+
+ va = radv_buffer_get_va(descriptor_bo);
+
+ radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
+
+ if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
+ uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+ R_00B130_SPI_SHADER_USER_DATA_VS_0,
+
Mesa (master): radv: only declare the ESGS rings for pre GFX9 chips
Module: Mesa
Branch: master
Commit: 1fba2e10b3f383953412fb2d6fcf4cd5cff6dea7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fba2e10b3f383953412fb2d6fcf4cd5cff6dea7
Author: Samuel Pitoiset
Date: Tue May 15 22:27:28 2018 +0200
radv: only declare the ESGS rings for pre GFX9 chips
GFX9 uses LDS instead.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 82b1e3637f..dba615025d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3017,9 +3017,16 @@ ac_nir_eliminate_const_vs_outputs(struct
radv_shader_context *ctx)
static void
ac_setup_rings(struct radv_shader_context *ctx)
{
- if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
- (ctx->stage == MESA_SHADER_TESS_EVAL &&
ctx->options->key.tes.as_es)) {
- ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
+ if (ctx->options->chip_class <= VI &&
+ (ctx->stage == MESA_SHADER_GEOMETRY ||
+ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
+ unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ?
RING_ESGS_GS
+ :
RING_ESGS_VS;
+ LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
+
+ ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
+ ctx->ring_offsets,
+ offset);
}
if (ctx->is_gs_copy_shader) {
@@ -3030,7 +3037,6 @@ ac_setup_rings(struct radv_shader_context *ctx)
uint32_t num_entries = 64;
LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32,
ctx->max_gsvs_emit_size, false);
LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32,
ctx->max_gsvs_emit_size << 16, false);
- ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac,
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder,
ctx->gsvs_ring, ctx->ac.v4i32, "");
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: do not emit unnecessary GS output stores
Module: Mesa
Branch: master
Commit: a6e44d12714871193ef130845b1f8727ffdbf01e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6e44d12714871193ef130845b1f8727ffdbf01e
Author: Samuel Pitoiset
Date: Wed May 16 17:43:22 2018 +0200
radv: do not emit unnecessary GS output stores
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b4af0f2941..05ae709685 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1684,6 +1684,8 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned
stream, LLVMValueRef *addr
/* loop num outputs */
idx = 0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ unsigned output_usage_mask =
+ ctx->shader_info->info.gs.output_usage_mask[i];
LLVMValueRef *out_ptr = &addrs[i * 4];
int length = 4;
int slot = idx;
@@ -1697,8 +1699,13 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned
stream, LLVMValueRef *addr
length = ctx->num_output_clips + ctx->num_output_culls;
if (length > 4)
slot_inc = 2;
+ output_usage_mask = (1 << length) - 1;
}
+
for (unsigned j = 0; j < length; j++) {
+ if (!(output_usage_mask & (1 << j)))
+ continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
out_ptr[j], "");
LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot
* 4 + j) * ctx->gs_max_out_vertices, false);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: do not emit unnecessary ES output stores
Module: Mesa
Branch: master
Commit: 56d53ed1d69e4c365d146cf37ebaf712362e4755
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56d53ed1d69e4c365d146cf37ebaf712362e4755
Author: Samuel Pitoiset
Date: Wed May 16 17:43:23 2018 +0200
radv: do not emit unnecessary ES output stores
GFX9:
Totals from affected shaders:
SGPRS: 472 -> 464 (-1.69 %)
VGPRS: 576 -> 584 (1.39 %)
Code Size: 45432 -> 44324 (-2.44 %) bytes
Max Waves: 40 -> 40 (0.00 %)
VI:
SGPRS: 720 -> 720 (0.00 %)
VGPRS: 728 -> 728 (0.00 %)
Code Size: 45348 -> 43992 (-2.99 %) bytes
Max Waves: 120 -> 120 (0.00 %)
This affects Rise of Tomb Raider and the three Vulkan demos
that use a geometry shader (geometryshader, deferredshadows
and viewportarray).
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 05ae709685..82b1e3637f 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2582,14 +2582,26 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef dw_addr = NULL;
LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
+ unsigned output_usage_mask;
int param_index;
int length = 4;
if (!(ctx->output_mask & (1ull << i)))
continue;
- if (i == VARYING_SLOT_CLIP_DIST0)
+ if (ctx->stage == MESA_SHADER_VERTEX) {
+ output_usage_mask =
+ ctx->shader_info->info.vs.output_usage_mask[i];
+ } else {
+ assert(ctx->stage == MESA_SHADER_TESS_EVAL);
+ output_usage_mask =
+ ctx->shader_info->info.tes.output_usage_mask[i];
+ }
+
+ if (i == VARYING_SLOT_CLIP_DIST0) {
length = ctx->num_output_clips + ctx->num_output_culls;
+ output_usage_mask = (1 << length) - 1;
+ }
param_index = shader_io_get_unique_index(i);
@@ -2598,14 +2610,22 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
LLVMConstInt(ctx->ac.i32,
param_index * 4, false),
"");
}
+
for (j = 0; j < length; j++) {
+ if (!(output_usage_mask & (1 << j)))
+ continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
out_ptr[j], "");
out_val = LLVMBuildBitCast(ctx->ac.builder, out_val,
ctx->ac.i32, "");
if (ctx->ac.chip_class >= GFX9) {
- ac_lds_store(&ctx->ac, dw_addr,
+ LLVMValueRef dw_addr_offset =
+ LLVMBuildAdd(ctx->ac.builder, dw_addr,
+LLVMConstInt(ctx->ac.i32,
+ j, false),
"");
+
+ ac_lds_store(&ctx->ac, dw_addr_offset,
LLVMBuildLoad(ctx->ac.builder,
out_ptr[j], ""));
- dw_addr = LLVMBuildAdd(ctx->ac.builder,
dw_addr, ctx->ac.i32_1, "");
} else {
ac_build_buffer_store_dword(&ctx->ac,
ctx->esgs_ring,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allow to print GPU info with RADV_DEBUG=info
Module: Mesa
Branch: master
Commit: d349d4bd24aef5b76d5ebb999f55416a14b039f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d349d4bd24aef5b76d5ebb999f55416a14b039f1
Author: Samuel Pitoiset
Date: Wed May 16 15:52:37 2018 +0200
radv: allow to print GPU info with RADV_DEBUG=info
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 9dda9b6b0c..b6993cee1c 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -45,6 +45,7 @@ enum {
RADV_DEBUG_PREOPTIR = 0x8000,
RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x1,
RADV_DEBUG_NO_OUT_OF_ORDER = 0x2,
+ RADV_DEBUG_INFO = 0x4,
};
enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e24b8c2a76..778887bd58 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -329,6 +329,9 @@ radv_physical_device_init(struct radv_physical_device
*device,
goto fail;
}
+ if ((device->instance->debug_flags & RADV_DEBUG_INFO))
+ ac_print_gpu_info(&device->rad_info);
+
return VK_SUCCESS;
fail:
@@ -391,6 +394,7 @@ static const struct debug_control radv_debug_options[] = {
{"preoptir", RADV_DEBUG_PREOPTIR},
{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
{"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
+ {"info", RADV_DEBUG_INFO},
{NULL, 0}
};
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove the radv_finishme() when compiling shaders
Module: Mesa
Branch: master
Commit: 6211799aff761282d07b0ce3efde88e67caeb04a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6211799aff761282d07b0ce3efde88e67caeb04a
Author: Samuel Pitoiset
Date: Thu May 17 09:56:48 2018 +0200
radv: remove the radv_finishme() when compiling shaders
Having an entrypoint different than "main" doesn't mean we
have multiple shaders per module.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 1968758a39..7589d9c88a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -163,10 +163,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags)
{
- if (strcmp(entrypoint_name, "main") != 0) {
- radv_finishme("Multiple shaders per module not really
supported");
- }
-
nir_shader *nir;
nir_function *entry_point;
if (module->nir) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: only pass the global BO list at submit time if enabled
Module: Mesa
Branch: master
Commit: 507402ada6dbe56daca49c1f9bdba3b445132e50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=507402ada6dbe56daca49c1f9bdba3b445132e50
Author: Samuel Pitoiset
Date: Thu May 17 11:36:09 2018 +0200
radv: only pass the global BO list at submit time if enabled
That way the winsys might use a faster path when the global
BO list is NULL.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 2ce0c9dbd0..e24b8c2a76 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2472,6 +2472,8 @@ VkResult radv_QueueSubmit(
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j +=
advance) {
struct radeon_winsys_cs *initial_preamble = (do_flush
&& !j) ? initial_flush_preamble_cs : initial_preamble_cs;
+ const struct radv_winsys_bo_list *bo_list = NULL;
+
advance = MIN2(max_cs_submission,
pSubmits[i].commandBufferCount - j);
@@ -2481,12 +2483,14 @@ VkResult radv_QueueSubmit(
sem_info.cs_emit_wait = j == 0;
sem_info.cs_emit_signal = j + advance ==
pSubmits[i].commandBufferCount;
- if (unlikely(queue->device->use_global_bo_list))
+ if (unlikely(queue->device->use_global_bo_list)) {
pthread_mutex_lock(&queue->device->bo_list.mutex);
+ bo_list = &queue->device->bo_list.list;
+ }
ret = queue->device->ws->cs_submit(ctx,
queue->queue_idx, cs_array + j,
advance,
initial_preamble, continue_preamble_cs,
- &sem_info,
&queue->device->bo_list.list,
+ &sem_info, bo_list,
can_patch, base_fence);
if (unlikely(queue->device->use_global_bo_list))
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove radv_device::llvm_supports_spill
Module: Mesa
Branch: master
Commit: 1e86eaf7d83e73b0287722a868718eb18675ce08
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e86eaf7d83e73b0287722a868718eb18675ce08
Author: Samuel Pitoiset
Date: Thu May 17 09:56:47 2018 +0200
radv: remove radv_device::llvm_supports_spill
It's always true.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 2 --
src/amd/vulkan/radv_private.h | 1 -
src/amd/vulkan/radv_shader.c | 5 +
3 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a7f4a5ab7b..2ce0c9dbd0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1454,8 +1454,6 @@ VkResult radv_CreateDevice(
device->always_use_syncobj =
device->physical_device->rad_info.has_syncobj_wait_for_submit;
#endif
- device->llvm_supports_spill = true;
-
/* The maximum number of scratch waves. Scratch space isn't divided
* evenly between CUs. The number is only a function of the number of
CUs.
* We can decrease the constant to decrease the scratch buffer size.
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e3eed887fa..304ed17f01 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -624,7 +624,6 @@ struct radv_device {
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
bool always_use_syncobj;
- bool llvm_supports_spill;
bool has_distributed_tess;
bool pbb_allowed;
bool dfsm_allowed;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index dfe63d60d4..1968758a39 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -376,9 +376,6 @@ radv_fill_shader_variant(struct radv_device *device,
struct radv_shader_info *info = &variant->info.info;
unsigned vgpr_comp_cnt = 0;
- if (scratch_enabled && !device->llvm_supports_spill)
- radv_finishme("shader scratch support only available with LLVM
4.0");
-
variant->code_size = binary->code_size;
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
S_00B12C_SCRATCH_EN(scratch_enabled);
@@ -554,7 +551,7 @@ radv_shader_variant_create(struct radv_device *device,
options.key = *key;
options.unsafe_math = !!(device->instance->debug_flags &
RADV_DEBUG_UNSAFE_MATH);
- options.supports_spill = device->llvm_supports_spill;
+ options.supports_spill = true;
return shader_variant_create(device, module, shaders, shader_count,
shaders[shader_count - 1]->info.stage,
&options, false, code_out, code_size_out);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add generated files to .gitignore(s)
Module: Mesa Branch: master Commit: bd0b6b9f17d401aa70eac279a3541d8e2a96ae0f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd0b6b9f17d401aa70eac279a3541d8e2a96ae0f Author: Dieter Nützel Date: Sun May 13 23:10:07 2018 +0200 radv: add generated files to .gitignore(s) Signed-off-by: Dieter Nützel Reviewed-by: Samuel Pitoiset --- src/amd/vulkan/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/.gitignore b/src/amd/vulkan/.gitignore index 7c02e42bb0..1aabfc08a9 100644 --- a/src/amd/vulkan/.gitignore +++ b/src/amd/vulkan/.gitignore @@ -2,6 +2,7 @@ /radv_entrypoints.c /radv_entrypoints.h /radv_extensions.c +/radv_extensions.h /radv_timestamp.h /dev_icd.json /vk_format_table.c ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): spirv: fix visiting inner loops with same break/continue block
Module: Mesa
Branch: master
Commit: 6bde8c560877512852ff49fafa296eb71a5ec14b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bde8c560877512852ff49fafa296eb71a5ec14b
Author: Samuel Pitoiset
Date: Tue May 15 12:00:30 2018 +0200
spirv: fix visiting inner loops with same break/continue block
We should stop walking through the CFG when the inner loop's
break block ends up as the same block as the outer loop's
continue block because we are already going to visit it.
This fixes the following assertion which ends up by crashing
in RADV or ANV:
SPIR-V parsing FAILED:
In file ../src/compiler/spirv/vtn_cfg.c:381
block->node.link.next == NULL
0 bytes into the SPIR-V binary
This also fixes a crash with a camera shader from SteamVR.
v2: make use of vtn_get_branch_type() and add an assertion
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106090
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106504
CC: 18.0 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Jason Ekstrand
---
src/compiler/spirv/vtn_cfg.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index e7d2f9ea61..ad4374112e 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -374,6 +374,19 @@ vtn_cfg_walk_blocks(struct vtn_builder *b, struct
list_head *cf_list,
vtn_cfg_walk_blocks(b, &loop->cont_body, new_loop_cont, NULL, NULL,
new_loop_break, NULL, block);
+ enum vtn_branch_type branch_type =
+vtn_get_branch_type(b, new_loop_break, switch_case, switch_break,
+loop_break, loop_cont);
+
+ if (branch_type != vtn_branch_type_none) {
+/* Stop walking through the CFG when this inner loop's break block
+ * ends up as the same block as the outer loop's continue block
+ * because we are already going to visit it.
+ */
+vtn_assert(branch_type == vtn_branch_type_loop_continue);
+return;
+ }
+
block = new_loop_break;
continue;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: run the shader info pass before emitting the GS copy shader
Module: Mesa Branch: master Commit: ea43d935ab765575994557d1f923b570d4bd9085 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea43d935ab765575994557d1f923b570d4bd9085 Author: Samuel Pitoiset Date: Mon May 14 16:04:34 2018 +0200 radv: run the shader info pass before emitting the GS copy shader For further optimizations. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 47c52dc437..2162ca58e0 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3549,6 +3549,8 @@ radv_compile_gs_copy_shader(LLVMTargetMachineRef tm, ctx.ac.builder = ac_create_builder(ctx.context, float_mode); ctx.stage = MESA_SHADER_VERTEX; + radv_nir_shader_info_pass(geom_shader, options, &shader_info->info); + create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX); ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: scan the geometry shader output usage mask
Module: Mesa
Branch: master
Commit: 560bd9eb67fb24b05816c3afb9a47794eddb61aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=560bd9eb67fb24b05816c3afb9a47794eddb61aa
Author: Samuel Pitoiset
Date: Mon May 14 16:04:35 2018 +0200
radv: scan the geometry shader output usage mask
For reducing the number of parameters that are exported by
the GS copy shader.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.h | 3 +++
src/amd/vulkan/radv_shader_info.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b711cba80c..679fa44279 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -159,6 +159,9 @@ struct radv_shader_info {
} vs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ } gs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;
struct {
bool force_persample;
diff --git a/src/amd/vulkan/radv_shader_info.c
b/src/amd/vulkan/radv_shader_info.c
index a436bd7534..b45b4c0c95 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -134,6 +134,12 @@ gather_intrinsic_store_var_info(const nir_shader *nir,
instr->const_index[0] << comp;
}
break;
+ case MESA_SHADER_GEOMETRY:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->gs.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
case MESA_SHADER_TESS_EVAL:
for (unsigned i = 0; i < attrib_count; i++) {
info->tes.output_usage_mask[idx + i +
const_offset] |=
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: reduce the number of parameters export by the GS copy shader
Module: Mesa
Branch: master
Commit: 97b179570c092632589dba1bd0ed49ec3b4d5cd5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97b179570c092632589dba1bd0ed49ec3b4d5cd5
Author: Samuel Pitoiset
Date: Mon May 14 16:04:36 2018 +0200
radv: reduce the number of parameters export by the GS copy shader
By using the geometry shader output usage mask.
This improves all Vulkan demos that use a geometry shader
(ie. geometryshader, deferredshadows, viewportarray).
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 2162ca58e0..b4af0f2941 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2493,10 +2493,9 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
output_usage_mask =
ctx->shader_info->info.tes.output_usage_mask[i];
} else {
- /* Enable all channels for the GS copy shader because
-* we don't know the output usage mask currently.
-*/
- output_usage_mask = 0xf;
+ assert(ctx->is_gs_copy_shader);
+ output_usage_mask =
+ ctx->shader_info->info.gs.output_usage_mask[i];
}
radv_export_param(ctx, param_count, values, output_usage_mask);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: check that layout isn't NULL in radv_nir_shader_info_pass()
Module: Mesa Branch: master Commit: 7cbc6f2621f6d91b7bb201b9539ebff0f903828a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cbc6f2621f6d91b7bb201b9539ebff0f903828a Author: Samuel Pitoiset Date: Mon May 14 16:04:33 2018 +0200 radv: check that layout isn't NULL in radv_nir_shader_info_pass() An upcoming patch will run the shader info pass on the geometry shader just before emitting the GS copy shader. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_shader_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index aa06efc9dc..a436bd7534 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -424,7 +424,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); - if (options->layout->dynamic_offset_count) + if (options->layout && options->layout->dynamic_offset_count) info->loads_push_constants = true; nir_foreach_variable(variable, &nir->inputs) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allow to dump the GS copy shader with RADV_DEBUG="shaders"
Module: Mesa
Branch: master
Commit: 8ade3e46845ed51b17bc0ff129f3e1eeea589a36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ade3e46845ed51b17bc0ff129f3e1eeea589a36
Author: Samuel Pitoiset
Date: Fri May 11 16:36:02 2018 +0200
radv: allow to dump the GS copy shader with RADV_DEBUG="shaders"
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_pipeline.c | 2 +-
src/amd/vulkan/radv_shader.c | 2 +-
src/amd/vulkan/radv_shader.h | 9 ++---
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d443f8271e..e6ac0721dc 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1984,7 +1984,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i]))
+ if (modules[i] && radv_can_dump_shader(device, modules[i],
false))
nir_print_shader(nir[i], stderr);
}
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index fde6309c97..dfe63d60d4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -484,7 +484,7 @@ shader_variant_create(struct radv_device *device,
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
- options->dump_shader = radv_can_dump_shader(device, module);
+ options->dump_shader = radv_can_dump_shader(device, module,
gs_copy_shader);
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags &
RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 182b69849c..12878307ec 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -329,11 +329,14 @@ radv_shader_dump_stats(struct radv_device *device,
static inline bool
radv_can_dump_shader(struct radv_device *device,
-struct radv_shader_module *module)
+struct radv_shader_module *module,
+bool is_gs_copy_shader)
{
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ return false;
+
/* Only dump non-meta shaders, useful for debugging purposes. */
- return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
- module && !module->nir;
+ return (module && !module->nir) || is_gs_copy_shader;
}
static inline bool
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: move {load,store}_var intrinsics scanning in different functions
Module: Mesa
Branch: master
Commit: 553418af1ecbaed04e24197caaf1febd575fec41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=553418af1ecbaed04e24197caaf1febd575fec41
Author: Samuel Pitoiset
Date: Thu May 10 17:15:41 2018 +0200
radv: move {load,store}_var intrinsics scanning in different functions
These are going to be crazy and we are probably going to add
more scan stuff in the future. Also use switch cases instead.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_shader_info.c | 127 --
1 file changed, 80 insertions(+), 47 deletions(-)
diff --git a/src/amd/vulkan/radv_shader_info.c
b/src/amd/vulkan/radv_shader_info.c
index 1fb350faed..aa06efc9dc 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -88,6 +88,83 @@ static void get_deref_offset(nir_deref_var *deref, unsigned
*const_out)
}
static void
+gather_intrinsic_load_var_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX: {
+ nir_deref_var *dvar = instr->variables[0];
+ nir_variable *var = dvar->var;
+
+ if (var->data.mode == nir_var_shader_in) {
+ unsigned idx = var->data.location;
+ uint8_t mask =
nir_ssa_def_components_read(&instr->dest.ssa);
+
+ info->vs.input_usage_mask[idx] |=
+ mask << var->data.location_frac;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+}
+
+static void
+gather_intrinsic_store_var_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ nir_deref_var *dvar = instr->variables[0];
+ nir_variable *var = dvar->var;
+
+ if (var->data.mode == nir_var_shader_out) {
+ unsigned attrib_count = glsl_count_attribute_slots(var->type,
false);
+ unsigned idx = var->data.location;
+ unsigned comp = var->data.location_frac;
+ unsigned const_offset = 0;
+
+ get_deref_offset(dvar, &const_offset);
+
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->vs.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->tes.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
+ case MESA_SHADER_TESS_CTRL: {
+ unsigned param = shader_io_get_unique_index(idx);
+ const struct glsl_type *type = var->type;
+
+ if (!var->data.patch)
+ type = glsl_get_array_element(var->type);
+
+ unsigned slots =
+ var->data.compact ?
DIV_ROUND_UP(glsl_get_length(type), 4)
+ :
glsl_count_attribute_slots(type, false);
+
+ if (idx == VARYING_SLOT_CLIP_DIST0)
+ slots = (nir->info.clip_distance_array_size +
+nir->info.cull_distance_array_size >
4) ? 2 : 1;
+
+ mark_tess_output(info, var->data.patch, param, slots);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+}
+
+static void
gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
struct radv_shader_info *info)
{
@@ -197,55 +274,11 @@ gather_intrinsic_info(const nir_shader *nir, const
nir_intrinsic_instr *instr,
info->ps.writes_memory = true;
break;
case nir_intrinsic_load_var:
- if (nir->info.stage == MESA_SHADER_VERTEX) {
- nir_deref_var *dvar = instr->variables[0];
- nir_variable *var = dvar->var;
-
- if (var->data.mode == nir_var_shader_in) {
- unsigned idx = var->data.location;
- uint8_t mask =
-
nir_ssa_def_c
Mesa (master): radv: remove useless check in radv_create_shaders()
Module: Mesa
Branch: master
Commit: ece398277cf1de5ac4debfd9855909fd1bafb239
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ece398277cf1de5ac4debfd9855909fd1bafb239
Author: Samuel Pitoiset
Date: Fri May 11 16:36:52 2018 +0200
radv: remove useless check in radv_create_shaders()
radv_can_dump_shader() already handles if module is NULL.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e6ac0721dc..3d242e05bf 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1984,7 +1984,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i],
false))
+ if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: minor cleanups in radv_fill_shader_variant()
Module: Mesa
Branch: master
Commit: 3a410f0afcfe8c26290782141a08ff962956ef3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a410f0afcfe8c26290782141a08ff962956ef3a
Author: Samuel Pitoiset
Date: Fri May 11 09:46:46 2018 +0200
radv: minor cleanups in radv_fill_shader_variant()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_shader.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 27b3fbed16..07634870d4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -371,6 +371,7 @@ radv_fill_shader_variant(struct radv_device *device,
gl_shader_stage stage)
{
bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
+ struct radv_shader_info *info = &variant->info.info;
unsigned vgpr_comp_cnt = 0;
if (scratch_enabled && !device->llvm_supports_spill)
@@ -378,9 +379,9 @@ radv_fill_shader_variant(struct radv_device *device,
variant->code_size = binary->code_size;
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
- S_00B12C_SCRATCH_EN(scratch_enabled);
+S_00B12C_SCRATCH_EN(scratch_enabled);
- variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
+ variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
S_00B848_DX10_CLAMP(1) |
S_00B848_FLOAT_MODE(variant->config.float_mode);
@@ -391,10 +392,11 @@ radv_fill_shader_variant(struct radv_device *device,
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
break;
case MESA_SHADER_TESS_CTRL:
- if (device->physical_device->rad_info.chip_class >= GFX9)
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
- else
+ } else {
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+ }
break;
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
@@ -402,8 +404,7 @@ radv_fill_shader_variant(struct radv_device *device,
break;
case MESA_SHADER_FRAGMENT:
break;
- case MESA_SHADER_COMPUTE: {
- struct radv_shader_info *info = &variant->info.info;
+ case MESA_SHADER_COMPUTE:
variant->rsrc2 |=
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
@@ -413,7 +414,6 @@ radv_fill_shader_variant(struct radv_device *device,
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx)
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
- }
default:
unreachable("unsupported shader type");
break;
@@ -421,7 +421,6 @@ radv_fill_shader_variant(struct radv_device *device,
if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_GEOMETRY) {
- struct radv_shader_info *info = &variant->info.info;
unsigned es_type = variant->info.gs.es_type;
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
@@ -436,23 +435,25 @@ radv_fill_shader_variant(struct radv_device *device,
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
* VGPR[0:4] are always loaded.
*/
- if (info->uses_invocation_id)
+ if (info->uses_invocation_id) {
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
- else if (info->uses_prim_id)
+ } else if (info->uses_prim_id) {
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
- else if (variant->info.gs.vertices_in >= 3)
+ } else if (variant->info.gs.vertices_in >= 3) {
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
- else
+ } else {
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+ }
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type ==
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
- stage == MESA_SHADER_TESS_CTRL)
+
Mesa (master): radv: move ac_build_if_state on top of radv_nir_to_llvm.c
Module: Mesa
Branch: master
Commit: efc10949cc9259da25dafd4965ba5e58cd99a181
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=efc10949cc9259da25dafd4965ba5e58cd99a181
Author: Samuel Pitoiset
Date: Fri May 11 09:37:11 2018 +0200
radv: move ac_build_if_state on top of radv_nir_to_llvm.c
These helpers will be needed for future work.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_nir_to_llvm.c | 183 +++---
1 file changed, 92 insertions(+), 91 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index e2d241e495..f98940f0d8 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -124,6 +124,98 @@ radv_shader_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
}
+struct ac_build_if_state
+{
+ struct radv_shader_context *ctx;
+ LLVMValueRef condition;
+ LLVMBasicBlockRef entry_block;
+ LLVMBasicBlockRef true_block;
+ LLVMBasicBlockRef false_block;
+ LLVMBasicBlockRef merge_block;
+};
+
+static LLVMBasicBlockRef
+ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
+{
+ LLVMBasicBlockRef current_block;
+ LLVMBasicBlockRef next_block;
+ LLVMBasicBlockRef new_block;
+
+ /* get current basic block */
+ current_block = LLVMGetInsertBlock(ctx->ac.builder);
+
+ /* chqeck if there's another block after this one */
+ next_block = LLVMGetNextBasicBlock(current_block);
+ if (next_block) {
+ /* insert the new block before the next block */
+ new_block = LLVMInsertBasicBlockInContext(ctx->context,
next_block, name);
+ }
+ else {
+ /* append new block after current block */
+ LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
+ new_block = LLVMAppendBasicBlockInContext(ctx->context,
function, name);
+ }
+ return new_block;
+}
+
+static void
+ac_nir_build_if(struct ac_build_if_state *ifthen,
+ struct radv_shader_context *ctx,
+ LLVMValueRef condition)
+{
+ LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
+
+ memset(ifthen, 0, sizeof *ifthen);
+ ifthen->ctx = ctx;
+ ifthen->condition = condition;
+ ifthen->entry_block = block;
+
+ /* create endif/merge basic block for the phi functions */
+ ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
+
+ /* create/insert true_block before merge_block */
+ ifthen->true_block =
+ LLVMInsertBasicBlockInContext(ctx->context,
+ ifthen->merge_block,
+ "if-true-block");
+
+ /* successive code goes into the true block */
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
+}
+
+/**
+ * End a conditional.
+ */
+static void
+ac_nir_build_endif(struct ac_build_if_state *ifthen)
+{
+ LLVMBuilderRef builder = ifthen->ctx->ac.builder;
+
+ /* Insert branch to the merge block from current block */
+ LLVMBuildBr(builder, ifthen->merge_block);
+
+ /*
+* Now patch in the various branch instructions.
+*/
+
+ /* Insert the conditional branch instruction at the end of entry_block
*/
+ LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
+ if (ifthen->false_block) {
+ /* we have an else clause */
+ LLVMBuildCondBr(builder, ifthen->condition,
+ ifthen->true_block, ifthen->false_block);
+ }
+ else {
+ /* no else clause */
+ LLVMBuildCondBr(builder, ifthen->condition,
+ ifthen->true_block, ifthen->merge_block);
+ }
+
+ /* Resume building code at end of the ifthen->merge_block */
+ LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
+}
+
+
static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
{
switch (ctx->stage) {
@@ -2502,97 +2594,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
}
}
-struct ac_build_if_state
-{
- struct radv_shader_context *ctx;
- LLVMValueRef condition;
- LLVMBasicBlockRef entry_block;
- LLVMBasicBlockRef true_block;
- LLVMBasicBlockRef false_block;
- LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
- LLVMBasicBlockRef current_block;
- LLVMBasicBlockRef next_block;
- LLVMBasicBlockRef new_block;
-
- /* get current basic block */
- current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
- /* check if there's
Mesa (master): radv: move handling nosisched option in a better place
Module: Mesa
Branch: master
Commit: 0defc5554780a444c9e2009178dc88f97740a174
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0defc5554780a444c9e2009178dc88f97740a174
Author: Samuel Pitoiset
Date: Wed May 9 23:52:53 2018 +0200
radv: move handling nosisched option in a better place
It's a per-application optimization, so it makes more sense
to do that in radv_handle_per_app_options().
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 08795dd6b6..a7f4a5ab7b 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -428,10 +428,12 @@ radv_handle_per_app_options(struct radv_instance
*instance,
if (!strcmp(name, "Talos - Linux - 32bit") ||
!strcmp(name, "Talos - Linux - 64bit")) {
- /* Force enable LLVM sisched for Talos because it looks safe
-* and it gives few more FPS.
-*/
- instance->perftest_flags |= RADV_PERFTEST_SISCHED;
+ if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
+ /* Force enable LLVM sisched for Talos because it looks
+* safe and it gives few more FPS.
+*/
+ instance->perftest_flags |= RADV_PERFTEST_SISCHED;
+ }
}
}
@@ -508,14 +510,6 @@ VkResult radv_CreateInstance(
radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
- if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
- /* Disable sisched when the user requests it, this is mostly
-* useful when the driver force-enable sisched for the given
-* application.
-*/
- instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
- }
-
*pInstance = radv_instance_to_handle(instance);
return VK_SUCCESS;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix multisample image copies
Module: Mesa
Branch: master
Commit: 97d57ef9174111bfe1fa6f85e022af5a3cf2f1ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97d57ef9174111bfe1fa6f85e022af5a3cf2f1ce
Author: Matthew Nicholls
Date: Wed May 2 14:03:52 2018 +0200
radv: fix multisample image copies
Previously before fb077b0728, the LOD parameter was being used in place of the
sample index, which would only copy the first sample to all samples in the
destination image. After that multisample image copies wouldn't copy anything
from my observations.
This fixes some copy_and_blit CTS tests.
v3.1: - set lod to 0 for nir_txf_ms (Samuel)
v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel)
- updated commit description (Samuel)
Fix this properly by copying each sample in a separate radv_CmdDraw and using a
pipeline with the correct rasterizationSamples for the destination image.
Cc: 18.0 18.1
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_blit2d.c | 288 +-
src/amd/vulkan/radv_private.h | 18 +--
2 files changed, 196 insertions(+), 110 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_blit2d.c
b/src/amd/vulkan/radv_meta_blit2d.c
index e163056257..4a718c639d 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -100,7 +100,8 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
struct radv_meta_blit2d_buffer *src_buf,
struct blit2d_src_temps *tmp,
enum blit2d_src_type src_type, VkFormat depth_format,
-VkImageAspectFlagBits aspects)
+VkImageAspectFlagBits aspects,
+uint32_t log2_samples)
{
struct radv_device *device = cmd_buffer->device;
@@ -108,7 +109,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
radv_meta_push_descriptor_set(cmd_buffer,
VK_PIPELINE_BIND_POINT_GRAPHICS,
-
device->meta_state.blit2d.p_layouts[src_type],
+
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
0, /* set */
1, /* descriptorWriteCount */
(VkWriteDescriptorSet[]) {
@@ -123,7 +124,7 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
});
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
-
device->meta_state.blit2d.p_layouts[src_type],
+
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
&src_buf->pitch);
} else {
@@ -131,12 +132,12 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
-
device->meta_state.blit2d.p_layouts[src_type],
+
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
VK_SHADER_STAGE_FRAGMENT_BIT, 16,
4,
&src_img->layer);
radv_meta_push_descriptor_set(cmd_buffer,
VK_PIPELINE_BIND_POINT_GRAPHICS,
-
device->meta_state.blit2d.p_layouts[src_type],
+
device->meta_state.blit2d[log2_samples].p_layouts[src_type],
0, /* set */
1, /* descriptorWriteCount */
(VkWriteDescriptorSet[]) {
@@ -190,10 +191,11 @@ blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
static void
bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
- enum blit2d_src_type src_type, unsigned fs_key)
+ enum blit2d_src_type src_type, unsigned fs_key,
+ uint32_t log2_samples)
{
VkPipeline pipeline =
-
cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
+
cmd_buffer->device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key];
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
@@ -201,10 +203,11 @@ bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
static void
bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
- enum blit2d_src_type src_type)
+ enum blit2d_src_type src_type,
+ uint32_t log2_samples)
{
VkPipeline pipeline =
-
Mesa (master): radv: only disable out-of-order rast for perfect occlusion queries
Module: Mesa
Branch: master
Commit: 1d766b019628107f45ef925ce76a171a73457c48
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d766b019628107f45ef925ce76a171a73457c48
Author: Samuel Pitoiset
Date: Tue Apr 24 17:06:18 2018 +0200
radv: only disable out-of-order rast for perfect occlusion queries
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 18 ++
src/amd/vulkan/radv_query.c | 4 ++--
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index baab8db617..baa28d408b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1334,6 +1334,7 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
{
+ bool has_perfect_queries =
cmd_buffer->state.perfect_occlusion_queries_enabled;
struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
uint32_t pa_sc_mode_cntl_1 =
pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
@@ -1342,11 +1343,12 @@ void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer)
if(!cmd_buffer->state.active_occlusion_queries) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >=
CIK) {
if
(G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
-
pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
+
pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
+ has_perfect_queries) {
/* Re-enable out-of-order rasterization if the
* bound pipeline supports it and if it's has
-* been disabled before starting occlusion
-* queries.
+* been disabled before starting any perfect
+* occlusion queries.
*/
radeon_set_context_reg(cmd_buffer->cs,
R_028A4C_PA_SC_MODE_CNTL_1,
@@ -1359,22 +1361,22 @@ void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer)
} else {
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
uint32_t sample_rate = subpass ?
util_logbase2(subpass->max_sample_count) : 0;
- bool perfect =
cmd_buffer->state.perfect_occlusion_queries_enabled;
if (cmd_buffer->device->physical_device->rad_info.chip_class >=
CIK) {
db_count_control =
- S_028004_PERFECT_ZPASS_COUNTS(perfect) |
+
S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
S_028004_SAMPLE_RATE(sample_rate) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1);
if
(G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
-
pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
+
pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
+ has_perfect_queries) {
/* If the bound pipeline has enabled
* out-of-order rasterization, we should
-* disable it before starting occlusion
-* queries.
+* disable it before starting any perfect
+* occlusion queries.
*/
pa_sc_mode_cntl_1 &=
C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 859a4a1d68..2b2e80f4e5 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1140,12 +1140,12 @@ static void emit_end_query(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->state.active_occlusion_queries--;
if (cmd_buffer->state.active_occlusion_queries == 0) {
+ radv_set_db_count_control(cmd_buffer);
+
/* Reset the perfect occlusion queries hint now that no
* queries are active.
*/
cmd_buffer->state.perfect_occlusion_queries_enabled =
false;
-
- radv_set_db_count_control(cmd_buffer);
}
radeon_emit(cs,
Mesa (master): radv: enable out-of-order rasterization by default
Module: Mesa
Branch: master
Commit: 0737c1e3a603e13ce9764ff5432e332b233c4b9d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0737c1e3a603e13ce9764ff5432e332b233c4b9d
Author: Samuel Pitoiset
Date: Tue Apr 24 17:06:19 2018 +0200
radv: enable out-of-order rasterization by default
As the implementation is conservative, we can now enable it
by default. It can be disabled with RADV_DEBUG=nooutoforder.
Don't expect much more than 1% of improvements, but the gain
seems consistent.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 03f218fcda..9dda9b6b0c 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -44,6 +44,7 @@ enum {
RADV_DEBUG_NO_SISCHED= 0x4000,
RADV_DEBUG_PREOPTIR = 0x8000,
RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x1,
+ RADV_DEBUG_NO_OUT_OF_ORDER = 0x2,
};
enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 629957afec..ef32c37464 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -315,7 +315,7 @@ radv_physical_device_init(struct radv_physical_device
*device,
device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
device->rad_info.max_se >= 2;
device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
- (device->instance->perftest_flags &
RADV_PERFTEST_OUT_OF_ORDER);
+ !(device->instance->debug_flags &
RADV_DEBUG_NO_OUT_OF_ORDER);
device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
(device->instance->perftest_flags &
RADV_PERFTEST_DCC_MSAA);
@@ -390,6 +390,7 @@ static const struct debug_control radv_debug_options[] = {
{"nosisched", RADV_DEBUG_NO_SISCHED},
{"preoptir", RADV_DEBUG_PREOPTIR},
{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
+ {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
{NULL, 0}
};
@@ -405,7 +406,6 @@ static const struct debug_control radv_perftest_options[] =
{
{"sisched", RADV_PERFTEST_SISCHED},
{"localbos", RADV_PERFTEST_LOCAL_BOS},
{"binning", RADV_PERFTEST_BINNING},
- {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{NULL, 0}
};
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: compute the number of subpass attachments correctly
Module: Mesa
Branch: master
Commit: d8db5986cee83078e46895d695d698db87507019
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8db5986cee83078e46895d695d698db87507019
Author: Samuel Pitoiset
Date: Fri Apr 27 10:53:13 2018 +0200
radv: compute the number of subpass attachments correctly
Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.
Cc: 18.0 18.1
Reviewed-by: Bas Nieuwenhuizen
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index d059af54f9..a7d54d7d61 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b/src/amd/vulkan/radv_pass.c
@@ -87,8 +87,8 @@ VkResult radv_CreateRenderPass(
subpass_attachment_count +=
desc->inputAttachmentCount +
desc->colorAttachmentCount +
- /* Count colorAttachmentCount again for
resolve_attachments */
- desc->colorAttachmentCount;
+ (desc->pResolveAttachments ? desc->colorAttachmentCount
: 0) +
+ (desc->pDepthStencilAttachment != NULL);
}
if (subpass_attachment_count) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: fix texture query LOD for 1D textures on GFX9
Module: Mesa
Branch: master
Commit: d38425ce872c4a00cfb691ae9dceca6a07afc516
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d38425ce872c4a00cfb691ae9dceca6a07afc516
Author: Samuel Pitoiset
Date: Wed Apr 25 18:15:52 2018 +0200
ac: fix texture query LOD for 1D textures on GFX9
1D textures are allocated as 2D which means we only need
one coordinate for texture query LOD.
Fixes: 625dcbbc456 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 900c1c4afe..e4ae6ef49a 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1309,6 +1309,14 @@ static LLVMValueRef build_tex_intrinsic(struct
ac_nir_context *ctx,
}
}
+ /* Fixup for GFX9 which allocates 1D textures as 2D. */
+ if (instr->op == nir_texop_lod && ctx->ac.chip_class >= GFX9) {
+ if ((args->dim == ac_image_2darray ||
+args->dim == ac_image_2d) && !args->coords[1]) {
+ args->coords[1] = ctx->ac.i32_0;
+ }
+ }
+
args->attributes = AC_FUNC_ATTR_READNONE;
return ac_build_image_opcode(&ctx->ac, args);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix DCC enablement since partial MSAA implementation
Module: Mesa
Branch: master
Commit: a6fbefa67b5b0ed1ee42a9034ee74dfaed1c389a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6fbefa67b5b0ed1ee42a9034ee74dfaed1c389a
Author: Samuel Pitoiset
Date: Wed Apr 25 10:56:15 2018 +0200
radv: fix DCC enablement since partial MSAA implementation
dcc_msaa_allowed is always false on GFX9+ and only true on VI
if RADV_PERFTEST=dccmsaa is set. This means DCC was disabled
in some situations where it should not.
This is likely going to fix a performance regression.
Fixes: 2f63b3dd09 ("radv: enable DCC for MSAA 2x textures on VI under an
option")
Cc: 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 348f4c7b34..793f861f4f 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -133,12 +133,12 @@ radv_use_dcc_for_image(struct radv_device *device,
if (create_info->scanout)
return false;
- /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet. */
- if (pCreateInfo->samples > 2)
- return false;
-
- /* TODO: Enable DCC for MSAA textures. */
- if (!device->physical_device->dcc_msaa_allowed)
+ /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
+* 2x can be enabled with an option.
+*/
+ if (pCreateInfo->samples > 2 ||
+ (pCreateInfo->samples == 2 &&
+!device->physical_device->dcc_msaa_allowed))
return false;
/* Determine if the formats are DCC compatible. */
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: set ac_surf_info::num_channels correctly
Module: Mesa
Branch: master
Commit: d7ffe3b384f4d1c15a9364768cf405d416522e60
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7ffe3b384f4d1c15a9364768cf405d416522e60
Author: Samuel Pitoiset
Date: Wed Apr 25 11:22:17 2018 +0200
radv: set ac_surf_info::num_channels correctly
num_channels has been introduced since "ac/surface: don't set
the display flag for obviously unsupported cases".
Based on RadeonSI.
Fixes: e29facff315 ("ac/surface: don't set the display flag for obviously
unsupported cases (v2)")
Cc: 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 2 +-
src/amd/vulkan/vk_format.h | 7 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 793f861f4f..a6f3628c8f 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -968,7 +968,7 @@ radv_image_create(VkDevice _device,
image->info.samples = pCreateInfo->samples;
image->info.array_size = pCreateInfo->arrayLayers;
image->info.levels = pCreateInfo->mipLevels;
- image->info.num_channels = 4; /* TODO: set this correctly */
+ image->info.num_channels =
vk_format_get_nr_components(pCreateInfo->format);
image->vk_format = pCreateInfo->format;
image->tiling = pCreateInfo->tiling;
diff --git a/src/amd/vulkan/vk_format.h b/src/amd/vulkan/vk_format.h
index 43265ed3d9..b8cb4f4ed3 100644
--- a/src/amd/vulkan/vk_format.h
+++ b/src/amd/vulkan/vk_format.h
@@ -488,4 +488,11 @@ vk_to_non_srgb_format(VkFormat format)
}
}
+static inline unsigned
+vk_format_get_nr_components(VkFormat format)
+{
+ const struct vk_format_description *desc =
vk_format_description(format);
+ return desc->nr_channels;
+}
+
#endif /* VK_FORMAT_H */
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: fix the number of coordinates for ac_image_get_lod and arrays
Module: Mesa
Branch: master
Commit: d136a5fad9c7e67c1362453388914ecc60420883
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d136a5fad9c7e67c1362453388914ecc60420883
Author: Samuel Pitoiset
Date: Mon Apr 23 17:05:10 2018 +0200
ac: fix the number of coordinates for ac_image_get_lod and arrays
This fixes crashes for the following CTS:
dEQP-VK.glsl.texture_functions.query.texturequerylod.*
Cubemaps are the same as 2D arrays.
Fixes: 625dcbbc456 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_llvm_build.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 02739f9da9..f21a5d2623 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1521,6 +1521,20 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
LLVMValueRef addr;
unsigned num_addr = 0;
+ if (a->opcode == ac_image_get_lod) {
+ switch (a->dim) {
+ case ac_image_1darray:
+ num_coords = 1;
+ break;
+ case ac_image_2darray:
+ case ac_image_cube:
+ num_coords = 2;
+ break;
+ default:
+ break;
+ }
+ }
+
if (a->offset)
args[num_addr++] = ac_to_integer(ctx, a->offset);
if (a->bias)
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac/nir: add missing round_slice for 1D arrays
Module: Mesa
Branch: master
Commit: 84fef802fb16cef68ec358cbfed1cac9c3bfa410
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84fef802fb16cef68ec358cbfed1cac9c3bfa410
Author: Samuel Pitoiset
Date: Mon Apr 23 14:46:26 2018 +0200
ac/nir: add missing round_slice for 1D arrays
This fixes a bunch of CTS fails with 1D arrays:
dEQP-VK.glsl.texture_functions.texture*.sampler1darray_*
Fixes: 625dcbbc456 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 72c773522f..34efb2b9fe 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3397,6 +3397,13 @@ static void visit_tex(struct ac_nir_context *ctx,
nir_tex_instr *instr)
}
/* Texture coordinates fixups */
+ if (instr->coord_components > 1 &&
+ instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
+ instr->is_array &&
+ instr->op != nir_texop_txf) {
+ args.coords[1] = apply_round_slice(&ctx->ac, args.coords[1]);
+ }
+
if (instr->coord_components > 2 &&
(instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: teach get_ac_sampler_dim() about subpass attachments
Module: Mesa
Branch: master
Commit: e37e6435895b27024e857f3b12269578613bd920
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e37e6435895b27024e857f3b12269578613bd920
Author: Samuel Pitoiset
Date: Mon Apr 23 16:55:39 2018 +0200
ac: teach get_ac_sampler_dim() about subpass attachments
Suggested by Nicolai.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 34efb2b9fe..900c1c4afe 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -87,7 +87,6 @@ get_ac_sampler_dim(const struct ac_llvm_context *ctx, enum
glsl_sampler_dim dim,
return is_array ? ac_image_1darray : ac_image_1d;
case GLSL_SAMPLER_DIM_2D:
case GLSL_SAMPLER_DIM_RECT:
- case GLSL_SAMPLER_DIM_SUBPASS:
case GLSL_SAMPLER_DIM_EXTERNAL:
return is_array ? ac_image_2darray : ac_image_2d;
case GLSL_SAMPLER_DIM_3D:
@@ -95,8 +94,11 @@ get_ac_sampler_dim(const struct ac_llvm_context *ctx, enum
glsl_sampler_dim dim,
case GLSL_SAMPLER_DIM_CUBE:
return ac_image_cube;
case GLSL_SAMPLER_DIM_MS:
- case GLSL_SAMPLER_DIM_SUBPASS_MS:
return is_array ? ac_image_2darraymsaa : ac_image_2dmsaa;
+ case GLSL_SAMPLER_DIM_SUBPASS:
+ return ac_image_2darray;
+ case GLSL_SAMPLER_DIM_SUBPASS_MS:
+ return ac_image_2darraymsaa;
default:
unreachable("bad sampler dim");
}
@@ -2090,18 +2092,6 @@ static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
return sample_index;
}
-static bool
-glsl_is_array_image(const struct glsl_type *type)
-{
- const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
-
- if (glsl_sampler_type_is_array(type))
- return true;
-
- return dim == GLSL_SAMPLER_DIM_SUBPASS ||
- dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
-}
-
static void get_image_coords(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr,
struct ac_image_args *args)
@@ -2247,7 +2237,7 @@ static LLVMValueRef visit_image_load(struct
ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_is_array_image(type));
+ glsl_sampler_type_is_array(type));
args.dmask = 15;
args.attributes = AC_FUNC_ATTR_READONLY;
if (var->data.image._volatile || var->data.image.coherent)
@@ -2290,7 +2280,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_is_array_image(type));
+ glsl_sampler_type_is_array(type));
args.dmask = 15;
if (force_glc || var->data.image._volatile ||
var->data.image.coherent)
args.cache_policy |= ac_glc;
@@ -2381,7 +2371,7 @@ static LLVMValueRef visit_image_atomic(struct
ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_is_array_image(type));
+ glsl_sampler_type_is_array(type));
return ac_build_image_opcode(&ctx->ac, &args);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: advertise 8 bits of subpixel precision for viewports
Module: Mesa
Branch: master
Commit: 8328c64eb1a9b4c6d4ad33574491d92c86a5a500
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8328c64eb1a9b4c6d4ad33574491d92c86a5a500
Author: Józef Kucia
Date: Wed Apr 11 00:11:57 2018 +0200
radv: advertise 8 bits of subpixel precision for viewports
This is what radeonsi does.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index d88d5f0642..25c0d47da8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -865,7 +865,7 @@ void radv_GetPhysicalDeviceProperties(
.maxViewports = MAX_VIEWPORTS,
.maxViewportDimensions= { (1 << 14), (1 <<
14) },
.viewportBoundsRange = { INT16_MIN,
INT16_MAX },
- .viewportSubPixelBits = 13, /* We take a
float? */
+ .viewportSubPixelBits = 8,
.minMemoryMapAlignment= 4096, /* A page */
.minTexelBufferOffsetAlignment= 1,
.minUniformBufferOffsetAlignment = 4,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac/nir: fix image dimension for subpass attachments
Module: Mesa
Branch: master
Commit: 8f13975713a7a7b8d625e3561a7fc9ce202ac64b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f13975713a7a7b8d625e3561a7fc9ce202ac64b
Author: Samuel Pitoiset
Date: Fri Apr 20 18:06:43 2018 +0200
ac/nir: fix image dimension for subpass attachments
For subpass attachments we need one more coordinate with
the layer, so make them array types.
This fixes a bunch of CTS fails with RADV.
Fixes: 24fb3e6aa1 ("ac/nir: use ac_build_image_opcode for image intrinsics")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ba7f353a9a..72c773522f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2090,6 +2090,18 @@ static LLVMValueRef
adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
return sample_index;
}
+static bool
+glsl_is_array_image(const struct glsl_type *type)
+{
+ const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
+
+ if (glsl_sampler_type_is_array(type))
+ return true;
+
+ return dim == GLSL_SAMPLER_DIM_SUBPASS ||
+ dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
+}
+
static void get_image_coords(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr,
struct ac_image_args *args)
@@ -2235,7 +2247,7 @@ static LLVMValueRef visit_image_load(struct
ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_sampler_type_is_array(type));
+ glsl_is_array_image(type));
args.dmask = 15;
args.attributes = AC_FUNC_ATTR_READONLY;
if (var->data.image._volatile || var->data.image.coherent)
@@ -2278,7 +2290,7 @@ static void visit_image_store(struct ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_sampler_type_is_array(type));
+ glsl_is_array_image(type));
args.dmask = 15;
if (force_glc || var->data.image._volatile ||
var->data.image.coherent)
args.cache_policy |= ac_glc;
@@ -2369,7 +2381,7 @@ static LLVMValueRef visit_image_atomic(struct
ac_nir_context *ctx,
args.resource = get_sampler_desc(ctx, instr->variables[0],
AC_DESC_IMAGE, NULL, true,
false);
args.dim = get_ac_image_dim(&ctx->ac,
glsl_get_sampler_dim(type),
- glsl_sampler_type_is_array(type));
+ glsl_is_array_image(type));
return ac_build_image_opcode(&ctx->ac, &args);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv/winsys: allow to submit up to 4 IBs for chips without chaining
Module: Mesa
Branch: master
Commit: fedd0a4215bcd387525000d76b77993ca38916ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fedd0a4215bcd387525000d76b77993ca38916ae
Author: Samuel Pitoiset
Date: Fri Apr 20 13:42:36 2018 +0200
radv/winsys: allow to submit up to 4 IBs for chips without chaining
The SI family doesn't support chaining which means the maximum
size in dwords per CS is limited. When that limit was reached
we failed to submit the CS and the application crashed.
This patch allows to submit up to 4 IBs which is currently the
limit, but recent amdgpu supports more than that.
Please note that we can reach the limit of 4 IBs per submit
but currently we can't improve that. The only solution is to
upgrade libdrm. That will be improved later but for now this
should fix crashes on SI or when using RADV_DEBUG=noibs.
Fixes: 36cb5508e89 ("radv/winsys: Fail early on overgrown cs.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105775
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 218 --
1 file changed, 168 insertions(+), 50 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index c4b2232ce9..0cd870b7c8 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -68,6 +68,10 @@ struct radv_amdgpu_cs {
struct radeon_winsys_bo **virtual_buffers;
uint8_t *virtual_buffer_priorities;
int *virtual_buffer_hash_table;
+
+ /* For chips that don't support chaining. */
+ struct radeon_winsys_cs *old_cs_buffers;
+ unsignednum_old_cs_buffers;
};
static inline struct radv_amdgpu_cs *
@@ -201,6 +205,12 @@ static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs
*rcs)
for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
+ for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
+ struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i];
+ free(rcs->buf);
+ }
+
+ free(cs->old_cs_buffers);
free(cs->old_ib_buffers);
free(cs->virtual_buffers);
free(cs->virtual_buffer_priorities);
@@ -286,9 +296,46 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs
*_cs, size_t min_size)
/* The total ib size cannot exceed limit_dws dwords. */
if (ib_dws > limit_dws)
{
- cs->failed = true;
+ /* The maximum size in dwords has been reached,
+* try to allocate a new one.
+*/
+ if (cs->num_old_cs_buffers + 1 >=
AMDGPU_CS_MAX_IBS_PER_SUBMIT) {
+ /* TODO: Allow to submit more than 4 IBs. */
+ fprintf(stderr, "amdgpu: Maximum number of IBs "
+ "per submit reached.\n");
+ cs->failed = true;
+ cs->base.cdw = 0;
+ return;
+ }
+
+ cs->old_cs_buffers =
+ realloc(cs->old_cs_buffers,
+ (cs->num_old_cs_buffers + 1) *
sizeof(*cs->old_cs_buffers));
+ if (!cs->old_cs_buffers) {
+ cs->failed = true;
+ cs->base.cdw = 0;
+ return;
+ }
+
+ /* Store the current one for submitting it later. */
+ cs->old_cs_buffers[cs->num_old_cs_buffers].cdw =
cs->base.cdw;
+ cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw =
cs->base.max_dw;
+ cs->old_cs_buffers[cs->num_old_cs_buffers].buf =
cs->base.buf;
+ cs->num_old_cs_buffers++;
+
+ /* Reset the cs, it will be re-allocated below. */
cs->base.cdw = 0;
- return;
+ cs->base.buf = NULL;
+
+ /* Re-compute the number of dwords to allocate. */
+ ib_dws = MAX2(cs->base.cdw + min_size,
+ MIN2(cs->base.max_dw * 2, limit_dws));
+ if (ib_dws > limit_dws) {
+ fprintf(stderr, "amdgpu: Too high number of "
+ "dwords to allocate\n");
+ cs->fail
Mesa (master): ac/nir: handle nir_intrinsic_load_first_vertex like base_vertex
Module: Mesa
Branch: master
Commit: dd069e9b41cb667cc6290417a7ce83e1f9ab1349
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd069e9b41cb667cc6290417a7ce83e1f9ab1349
Author: Samuel Pitoiset
Date: Fri Apr 20 16:58:24 2018 +0200
ac/nir: handle nir_intrinsic_load_first_vertex like base_vertex
This fixes a ton of CTS crashes.
Fixes: c366f422f0 ("nir: Offset vertex_id by first_vertex instead of
base_vertex")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f00091e825..ba7f353a9a 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2815,10 +2815,10 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ac_build_gather_values(&ctx->ac, values, 3);
break;
}
- case nir_intrinsic_load_base_vertex: {
+ case nir_intrinsic_load_base_vertex:
+ case nir_intrinsic_load_first_vertex:
result = ctx->abi->load_base_vertex(ctx->abi);
break;
- }
case nir_intrinsic_load_local_group_size:
result = ctx->abi->load_local_group_size(ctx->abi);
break;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv/winsys: allow local BOs on APUs
Module: Mesa
Branch: master
Commit: b21a4efb55359cc1ddcb6cfd99982e3bddfc8332
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b21a4efb55359cc1ddcb6cfd99982e3bddfc8332
Author: Samuel Pitoiset
Date: Fri Apr 20 15:11:24 2018 +0200
radv/winsys: allow local BOs on APUs
Ported from RadeonSI.
Local BOs ignore BO priorities, and we don't need those on APUs.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 32f263addd..e2060651e4 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -347,7 +347,8 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
if (!(flags & RADEON_FLAG_IMPLICIT_SYNC) && ws->info.drm_minor >= 22)
request.flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
- if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && ws->info.drm_minor
>= 20 && ws->use_local_bos) {
+ if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
+ ws->info.has_local_buffers && ws->use_local_bos) {
bo->base.is_local = true;
request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Revert "radv: Don't store buffer references in the descriptor set."
Module: Mesa
Branch: master
Commit: 7bd5367546971f65c8210c0b44b8f21c0b8811c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bd5367546971f65c8210c0b44b8f21c0b8811c4
Author: Samuel Pitoiset
Date: Thu Apr 19 13:39:17 2018 +0200
Revert "radv: Don't store buffer references in the descriptor set."
In order to reduce a performance regression introduced by
4b13fe55a4 ("radv: Keep a global BO list for VkMemory."),
we are going to maintain two different paths.
One when VK_EXT_descriptor_indexing is enabled by the
application because we need to have a global BO list, and
one (the old one) when it's not enabled.
With Talos on Polaris, the global BO list reduces performance
by 10% which is too much for me.
This reverts commit ab6cadd3ecc7fbdd9079808b407674e0b19c52f0.
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 4 ++
src/amd/vulkan/radv_debug.c | 3 ++
src/amd/vulkan/radv_descriptor_set.c | 82 ++--
src/amd/vulkan/radv_descriptor_set.h | 4 ++
src/amd/vulkan/radv_private.h| 2 +
5 files changed, 82 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1afdeda486..b06429abd7 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2206,6 +2206,10 @@ radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
assert(!(set->layout->flags &
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
+ for (unsigned j = 0; j < set->layout->buffer_count; ++j)
+ if (set->descriptors[j])
+ radv_cs_add_buffer(ws, cmd_buffer->cs,
set->descriptors[j], 7);
+
if(set->bo)
radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
}
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 2e9e016523..368bc4b5d0 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -250,6 +250,7 @@ radv_dump_descriptor_set(enum chip_class chip_class,
fprintf(f, "\tshader_stages: %x\n", layout->shader_stages);
fprintf(f, "\tdynamic_shader_stages: %x\n",
layout->dynamic_shader_stages);
+ fprintf(f, "\tbuffer_count: %d\n", layout->buffer_count);
fprintf(f, "\tdynamic_offset_count: %d\n",
layout->dynamic_offset_count);
fprintf(f, "\n");
@@ -265,6 +266,8 @@ radv_dump_descriptor_set(enum chip_class chip_class,
layout->binding[i].array_size);
fprintf(f, "\t\toffset: %d\n",
layout->binding[i].offset);
+ fprintf(f, "\t\tbuffer_offset: %d\n",
+ layout->binding[i].buffer_offset);
fprintf(f, "\t\tdynamic_offset_offset: %d\n",
layout->binding[i].dynamic_offset_offset);
fprintf(f, "\t\tdynamic_offset_count: %d\n",
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index 55b4aaa388..4b08a1f0f8 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -117,12 +117,14 @@ VkResult radv_CreateDescriptorSetLayout(
memset(set_layout->binding, 0, size - sizeof(struct
radv_descriptor_set_layout));
+ uint32_t buffer_count = 0;
uint32_t dynamic_offset_count = 0;
for (uint32_t j = 0; j < pCreateInfo->bindingCount; j++) {
const VkDescriptorSetLayoutBinding *binding = bindings + j;
uint32_t b = binding->binding;
uint32_t alignment;
+ unsigned binding_buffer_count = 0;
switch (binding->descriptorType) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
@@ -131,6 +133,7 @@ VkResult radv_CreateDescriptorSetLayout(
set_layout->binding[b].dynamic_offset_count = 1;
set_layout->dynamic_shader_stages |=
binding->stageFlags;
set_layout->binding[b].size = 0;
+ binding_buffer_count = 1;
alignment = 1;
break;
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
@@ -138,6 +141,7 @@ VkResult radv_CreateDescriptorSetLayout(
case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
set_layout->binding[b].size = 16;
+ binding_buffer_count = 1;
alignment = 16;
break;
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
@@ -145,11 +149,13 @@ VkResult radv_CreateDescriptorSetLayout(
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
Mesa (master): radv: use a global BO list only for VK_EXT_descriptor_indexing
Module: Mesa
Branch: master
Commit: 5c1233ed620754c1691ffc6fc68d3f58f29a8d03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c1233ed620754c1691ffc6fc68d3f58f29a8d03
Author: Samuel Pitoiset
Date: Thu Apr 19 13:48:33 2018 +0200
radv: use a global BO list only for VK_EXT_descriptor_indexing
Maintaining two different paths is annoying but this gets
rid of the performance regression introduced by the global
BO list.
We might find a better solution in the future, but for now
just keeps two paths.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 8 +---
src/amd/vulkan/radv_device.c | 32 ++--
src/amd/vulkan/radv_private.h| 3 +++
3 files changed, 34 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b06429abd7..baab8db617 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2206,9 +2206,11 @@ radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
assert(!(set->layout->flags &
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
- for (unsigned j = 0; j < set->layout->buffer_count; ++j)
- if (set->descriptors[j])
- radv_cs_add_buffer(ws, cmd_buffer->cs,
set->descriptors[j], 7);
+ if (!cmd_buffer->device->use_global_bo_list) {
+ for (unsigned j = 0; j < set->layout->buffer_count; ++j)
+ if (set->descriptors[j])
+ radv_cs_add_buffer(ws, cmd_buffer->cs,
set->descriptors[j], 7);
+ }
if(set->bo)
radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9950ed40f1..edf099e4f0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1302,8 +1302,14 @@ radv_bo_list_finish(struct radv_bo_list *bo_list)
pthread_mutex_destroy(&bo_list->mutex);
}
-static VkResult radv_bo_list_add(struct radv_bo_list *bo_list, struct
radeon_winsys_bo *bo)
+static VkResult radv_bo_list_add(struct radv_device *device,
+struct radeon_winsys_bo *bo)
{
+ struct radv_bo_list *bo_list = &device->bo_list;
+
+ if (unlikely(!device->use_global_bo_list))
+ return VK_SUCCESS;
+
pthread_mutex_lock(&bo_list->mutex);
if (bo_list->list.count == bo_list->capacity) {
unsigned capacity = MAX2(4, bo_list->capacity * 2);
@@ -1323,8 +1329,14 @@ static VkResult radv_bo_list_add(struct radv_bo_list
*bo_list, struct radeon_win
return VK_SUCCESS;
}
-static void radv_bo_list_remove(struct radv_bo_list *bo_list, struct
radeon_winsys_bo *bo)
+static void radv_bo_list_remove(struct radv_device *device,
+ struct radeon_winsys_bo *bo)
{
+ struct radv_bo_list *bo_list = &device->bo_list;
+
+ if (unlikely(!device->use_global_bo_list))
+ return;
+
pthread_mutex_lock(&bo_list->mutex);
for(unsigned i = 0; i < bo_list->list.count; ++i) {
if (bo_list->list.bos[i] == bo) {
@@ -1434,6 +1446,12 @@ VkResult radv_CreateDevice(
keep_shader_info = device->enabled_extensions.AMD_shader_info;
+ /* With update after bind we can't attach bo's to the command buffer
+* from the descriptor set anymore, so we have to use a global BO list.
+*/
+ device->use_global_bo_list =
+ device->enabled_extensions.EXT_descriptor_indexing;
+
mtx_init(&device->shader_slab_mutex, mtx_plain);
list_inithead(&device->shader_slabs);
@@ -2506,14 +2524,16 @@ VkResult radv_QueueSubmit(
sem_info.cs_emit_wait = j == 0;
sem_info.cs_emit_signal = j + advance ==
pSubmits[i].commandBufferCount;
- pthread_mutex_lock(&queue->device->bo_list.mutex);
+ if (unlikely(queue->device->use_global_bo_list))
+
pthread_mutex_lock(&queue->device->bo_list.mutex);
ret = queue->device->ws->cs_submit(ctx,
queue->queue_idx, cs_array + j,
advance,
initial_preamble, continue_preamble_cs,
&sem_info,
&queue->device->bo_list.list,
can_patch, base_fence);
- pthread_mutex_unlock(&queue->device->bo_list.mutex);
+ if (unlikely(queue->device->use_global_bo_list))
+
pthread_mutex_unl
Mesa (master): radv: enable DCC for MSAA 2x textures on VI under an option
Module: Mesa
Branch: master
Commit: 2f63b3dd09cb516b83537504adf36a0227e3f874
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f63b3dd09cb516b83537504adf36a0227e3f874
Author: Samuel Pitoiset
Date: Tue Apr 17 16:05:18 2018 +0200
radv: enable DCC for MSAA 2x textures on VI under an option
This can be enabled with RADV_PERFTEST=dccmsaa.
DCC for MSAA textures is actually not as easy to implement. It
looks like there is some corner cases. I will improve support
incrementally.
Vega support, as well as Polaris improvements, will be added later.
No CTS changes on Polaris using RADV_DEBUG=zerovram and
RADV_PERFTEST=dccmsaa.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 4
src/amd/vulkan/radv_image.c | 6 +-
src/amd/vulkan/radv_private.h | 3 +++
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index f35991fa4e..79c624aec1 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -51,6 +51,7 @@ enum {
RADV_PERFTEST_LOCAL_BOS = 0x4,
RADV_PERFTEST_BINNING = 0x8,
RADV_PERFTEST_OUT_OF_ORDER = 0x10,
+ RADV_PERFTEST_DCC_MSAA = 0x20,
};
bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fd11cedcbf..14ecbd0200 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -314,6 +314,9 @@ radv_physical_device_init(struct radv_physical_device
*device,
device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
(device->instance->perftest_flags &
RADV_PERFTEST_OUT_OF_ORDER);
+ device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
+ (device->instance->perftest_flags &
RADV_PERFTEST_DCC_MSAA);
+
radv_physical_device_init_mem_types(device);
radv_fill_device_extension_table(device, &device->supported_extensions);
@@ -399,6 +402,7 @@ static const struct debug_control radv_perftest_options[] =
{
{"localbos", RADV_PERFTEST_LOCAL_BOS},
{"binning", RADV_PERFTEST_BINNING},
{"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
+ {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{NULL, 0}
};
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index ba8f14d91b..348f4c7b34 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -133,8 +133,12 @@ radv_use_dcc_for_image(struct radv_device *device,
if (create_info->scanout)
return false;
+ /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet. */
+ if (pCreateInfo->samples > 2)
+ return false;
+
/* TODO: Enable DCC for MSAA textures. */
- if (pCreateInfo->samples >= 2)
+ if (!device->physical_device->dcc_msaa_allowed)
return false;
/* Determine if the formats are DCC compatible. */
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index af95f4b649..4a860c595f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -295,6 +295,9 @@ struct radv_physical_device {
bool has_out_of_order_rast;
bool out_of_order_rast_allowed;
+ /* Whether DCC should be enabled for MSAA textures. */
+ bool dcc_msaa_allowed;
+
/* This is the drivers on-disk cache used as a fallback as opposed to
* the pipeline cache defined by apps.
*/
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add a workaround for fast clears with DCC and MSAA textures
Module: Mesa
Branch: master
Commit: 1aefb62f1e85de379d6045f234f32bf6cb924a09
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1aefb62f1e85de379d6045f234f32bf6cb924a09
Author: Samuel Pitoiset
Date: Tue Apr 17 16:05:16 2018 +0200
radv: add a workaround for fast clears with DCC and MSAA textures
This should be fixed at some point in order to improve
performance.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_clear.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 86e0bc17ed..858e3368b6 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1062,6 +1062,15 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (iview->image->info.samples > 1) {
/* DCC fast clear with MSAA should clear CMASK. */
+ /* FIXME: This doesn't work for now. There is a
+* hardware bug with fast clears and DCC for MSAA
+* textures. AMDVLK has a workaround but it doesn't
+* seem to work here. Note that we might emit useless
+* CB flushes but that shouldn't matter.
+*/
+ if (!can_avoid_fast_clear_elim)
+ goto fail;
+
assert(radv_image_has_cmask(iview->image));
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: implement fast color clear for DCC with MSAA
Module: Mesa
Branch: master
Commit: 255506c4e04bfa5490d98a748aa248189a213ad6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=255506c4e04bfa5490d98a748aa248189a213ad6
Author: Samuel Pitoiset
Date: Tue Apr 17 16:05:14 2018 +0200
radv: implement fast color clear for DCC with MSAA
When DCC is enabled with MSAA textures, CMASK should be
cleared to 0x.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_clear.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 016c1ee296..86e0bc17ed 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1054,14 +1054,29 @@ emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer,
if (radv_image_has_dcc(iview->image)) {
uint32_t reset_value;
bool can_avoid_fast_clear_elim;
+ bool need_decompress_pass = false;
+
vi_get_fast_clear_parameters(iview->image->vk_format,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
+ if (iview->image->info.samples > 1) {
+ /* DCC fast clear with MSAA should clear CMASK. */
+ assert(radv_image_has_cmask(iview->image));
+
+ flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
+ cmask_clear_value);
+
+ need_decompress_pass = true;
+ }
+
+ if (!can_avoid_fast_clear_elim)
+ need_decompress_pass = true;
+
flush_bits = radv_clear_dcc(cmd_buffer, iview->image,
reset_value);
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
- !can_avoid_fast_clear_elim);
+ need_decompress_pass);
} else {
flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
cmask_clear_value);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: decompress DCC for multisampled source images before resolving
Module: Mesa
Branch: master
Commit: dc3d39771ff561fe3e71aa0d08623e190ff496f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc3d39771ff561fe3e71aa0d08623e190ff496f9
Author: Samuel Pitoiset
Date: Tue Apr 17 16:05:17 2018 +0200
radv: decompress DCC for multisampled source images before resolving
Multisampled source images (ie. color attachments) can be now
DCC compressed, so the driver needs to perform a DCC decompression
pass before resolving
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta.h| 1 +
src/amd/vulkan/radv_meta_resolve.c| 17 +++--
src/amd/vulkan/radv_meta_resolve_cs.c | 2 +-
src/amd/vulkan/radv_meta_resolve_fs.c | 2 +-
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 47eec5cd6a..4a9abae30a 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -195,6 +195,7 @@ void radv_decompress_resolve_subpass_src(struct
radv_cmd_buffer *cmd_buffer);
void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image,
+VkImageLayout src_image_layout,
uint32_t region_count,
const VkImageResolve *regions);
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index d66f1c9f93..f3e088b10c 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -697,7 +697,8 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer
*cmd_buffer)
region.srcSubresource.mipLevel = 0;
region.srcSubresource.layerCount = 1;
- radv_decompress_resolve_src(cmd_buffer, src_image, 1, ®ion);
+ radv_decompress_resolve_src(cmd_buffer, src_image,
+ src_att.layout, 1, ®ion);
}
}
@@ -707,6 +708,7 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer
*cmd_buffer)
void
radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image,
+ VkImageLayout src_image_layout,
uint32_t region_count,
const VkImageResolve *regions)
{
@@ -722,6 +724,17 @@ radv_decompress_resolve_src(struct radv_cmd_buffer
*cmd_buffer,
range.baseArrayLayer = src_base_layer;
range.layerCount = region->srcSubresource.layerCount;
- radv_fast_clear_flush_image_inplace(cmd_buffer, src_image,
&range);
+ uint32_t queue_mask =
+ radv_image_queue_family_mask(src_image,
+
cmd_buffer->queue_family_index,
+
cmd_buffer->queue_family_index);
+
+ if (radv_layout_dcc_compressed(src_image, src_image_layout,
+ queue_mask)) {
+ radv_decompress_dcc(cmd_buffer, src_image, &range);
+ } else {
+ radv_fast_clear_flush_image_inplace(cmd_buffer,
+ src_image, &range);
+ }
}
}
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index ede55f6d00..274e64999a 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -388,7 +388,7 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer
*cmd_buffer,
{
struct radv_meta_saved_state saved_state;
- radv_decompress_resolve_src(cmd_buffer, src_image,
+ radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
region_count, regions);
radv_meta_save(&saved_state, cmd_buffer,
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 499b3ae27a..ef8c1d8b1d 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -458,7 +458,7 @@ void radv_meta_resolve_fragment_image(struct
radv_cmd_buffer *cmd_buffer,
unsigned dst_layout =
radv_meta_dst_layout_from_layout(dest_image_layout);
VkRenderPass rp;
- radv_decompress_resolve_src(cmd_buffer, src_image,
+ radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
region_count, regions);
rp =
device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: make sure to sync after resolving using the compute path
Module: Mesa
Branch: master
Commit: 796b6f4aab46924f9954c9b2a9821b4706618cab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=796b6f4aab46924f9954c9b2a9821b4706618cab
Author: Samuel Pitoiset
Date: Tue Apr 17 15:08:11 2018 +0200
radv: make sure to sync after resolving using the compute path
This fixes some random CTS failures:
dEQP-VK.renderpass.multisample.*.
Performing a fast-clear eliminate is still useless, but it
seems that we need to sync.
Found while running CTS with RADV_DEBUG=zerovram.
Fixes: 56a171a499c ("radv: don't fast-clear eliminate after resolving a subpass
with compute")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_resolve_cs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 628208d635..ede55f6d00 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -516,5 +516,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer)
&(VkExtent2D) { fb->width, fb->height });
}
+ cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
+ RADV_CMD_FLAG_INV_VMEM_L1;
+
radv_meta_restore(&saved_state, cmd_buffer);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allocate CMASK for DCC fast clear with MSAA
Module: Mesa
Branch: master
Commit: 373fa0b599ca3b2904433e413fd6e24fc37292b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=373fa0b599ca3b2904433e413fd6e24fc37292b7
Author: Samuel Pitoiset
Date: Tue Apr 17 16:05:15 2018 +0200
radv: allocate CMASK for DCC fast clear with MSAA
CMASK is required because it should be cleared to
0x for MSAA textures.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index a14e7c18b2..ba8f14d91b 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -997,6 +997,13 @@ radv_image_create(VkDevice _device,
/* Try to enable DCC first. */
if (radv_image_can_enable_dcc(image)) {
radv_image_alloc_dcc(image);
+ if (image->info.samples > 1) {
+ /* CMASK should be enabled because DCC fast
+* clear with MSAA needs it.
+*/
+ assert(radv_image_can_enable_cmask(image));
+ radv_image_alloc_cmask(device, image);
+ }
} else {
/* When DCC cannot be enabled, try CMASK. */
image->surface.dcc_size = 0;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: dump the SHA1 of SPIRV in the hang report
Module: Mesa
Branch: master
Commit: 4a698660aef46475e9bb49a03eb1019792f478c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a698660aef46475e9bb49a03eb1019792f478c2
Author: Samuel Pitoiset
Date: Wed Apr 18 18:53:44 2018 +0200
radv: dump the SHA1 of SPIRV in the hang report
Might be useful for debugging purposes, especially when we
want to replace a shader on the fly.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_debug.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 17782ab744..2e9e016523 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -29,6 +29,7 @@
#include
#include
+#include "util/mesa-sha1.h"
#include "sid.h"
#include "gfx9d.h"
#include "ac_debug.h"
@@ -496,7 +497,13 @@ radv_dump_shader(struct radv_pipeline *pipeline,
fprintf(f, "%s:\n\n", radv_get_shader_name(shader, stage));
if (shader->spirv) {
- fprintf(f, "SPIRV:\n");
+ unsigned char sha1[21];
+ char sha1buf[41];
+
+ _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
+ _mesa_sha1_format(sha1buf, sha1);
+
+ fprintf(f, "SPIRV (sha1: %s):\n", sha1buf);
radv_print_spirv(shader->spirv, shader->spirv_size, f);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix scissor computation when using half-pixel viewport offset
Module: Mesa
Branch: master
Commit: 893e19efb74edd6133a607e09338bf5d449632f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=893e19efb74edd6133a607e09338bf5d449632f1
Author: Samuel Pitoiset
Date: Tue Apr 17 22:07:26 2018 +0200
radv: fix scissor computation when using half-pixel viewport offset
'scale[i]' can be non-integer.
Original patch by Philip Rebohle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074
Fixes: 0f3de89a56a ("radv: Use the guard band.")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/si_cmd_buffer.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index aed291be35..15edaa4b2b 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -663,10 +663,10 @@ static VkRect2D si_scissor_from_viewport(const VkViewport
*viewport)
get_viewport_xform(viewport, scale, translate);
- rect.offset.x = translate[0] - abs(scale[0]);
- rect.offset.y = translate[1] - abs(scale[1]);
- rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
- rect.extent.height = ceilf(translate[1] + abs(scale[1])) -
rect.offset.y;
+ rect.offset.x = translate[0] - fabs(scale[0]);
+ rect.offset.y = translate[1] - fabs(scale[1]);
+ rect.extent.width = ceilf(translate[0] + fabs(scale[0])) -
rect.offset.x;
+ rect.extent.height = ceilf(translate[1] + fabs(scale[1])) -
rect.offset.y;
return rect;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: merge radv_handle_{dcc,cmask}_image_transition() functions
Module: Mesa
Branch: master
Commit: 584d1f2711e07f0c0bf159ddde9c7bf127591437
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=584d1f2711e07f0c0bf159ddde9c7bf127591437
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:49 2018 +0200
radv: merge radv_handle_{dcc,cmask}_image_transition() functions
Into radv_handle_color_image_transition().
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 58
1 file changed, 17 insertions(+), 41 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 48877bde4a..afe953d90c 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3766,20 +3766,6 @@ static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
-static void radv_handle_cmask_image_transition(struct radv_cmd_buffer
*cmd_buffer,
- struct radv_image *image,
- VkImageLayout src_layout,
- VkImageLayout dst_layout,
- unsigned src_queue_mask,
- unsigned dst_queue_mask,
- const VkImageSubresourceRange
*range)
-{
- if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
- !radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
- radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
- }
-}
-
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
{
@@ -3794,25 +3780,6 @@ void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer,
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
-static void radv_handle_dcc_image_transition(struct radv_cmd_buffer
*cmd_buffer,
-struct radv_image *image,
-VkImageLayout src_layout,
-VkImageLayout dst_layout,
-unsigned src_queue_mask,
-unsigned dst_queue_mask,
-const VkImageSubresourceRange
*range)
-{
- if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
- radv_initialize_dcc(cmd_buffer, image, 0xu);
- } else if (radv_layout_dcc_compressed(image, src_layout,
src_queue_mask) &&
- !radv_layout_dcc_compressed(image, dst_layout,
dst_queue_mask)) {
- radv_decompress_dcc(cmd_buffer, image, range);
- } else if (radv_layout_can_fast_clear(image, src_layout,
src_queue_mask) &&
- !radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
- radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
- }
-}
-
/**
* Initialize DCC/FMASK/CMASK metadata for a color image.
*/
@@ -3864,15 +3831,24 @@ static void radv_handle_color_image_transition(struct
radv_cmd_buffer *cmd_buffe
return;
}
- if (radv_image_has_dcc(image))
- radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
-dst_layout, src_queue_mask,
-dst_queue_mask, range);
+ if (radv_image_has_dcc(image)) {
+ if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
+ radv_initialize_dcc(cmd_buffer, image, 0xu);
+ } else if (radv_layout_dcc_compressed(image, src_layout,
src_queue_mask) &&
+ !radv_layout_dcc_compressed(image, dst_layout,
dst_queue_mask)) {
+ radv_decompress_dcc(cmd_buffer, image, range);
+ } else if (radv_layout_can_fast_clear(image, src_layout,
src_queue_mask) &&
+ !radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
+ radv_fast_clear_flush_image_inplace(cmd_buffer, image,
range);
+ }
+ }
- if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
- radv_handle_cmask_image_transition(cmd_buffer, image,
src_layout,
- dst_layout, src_queue_mask,
- dst_queue_mask, range);
+ if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
+ if (radv_layout_can_fast_clear(image, src_layout,
src_queue_mask) &&
+ !radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
+
Mesa (master): radv: disable prediction only if it has been enabled
Module: Mesa
Branch: master
Commit: 79c87a45b69e6f94ebe42ffcd59267ec3d9c99ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79c87a45b69e6f94ebe42ffcd59267ec3d9c99ca
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:43 2018 +0200
radv: disable prediction only if it has been enabled
When decompressing DCC we don't enable it, so it's useless
to disable it. This reduces the number of prediction packets
sent to the GPU when performing color decompression passes.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 327c1ae440..d5af7a1b0c 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -667,7 +667,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer
*cmd_buffer,
&cmd_buffer->pool->alloc);
}
- if (radv_image_has_dcc(image)) {
+ if (!decompress_dcc && radv_image_has_dcc(image)) {
cmd_buffer->state.predicating = false;
radv_emit_set_predication_state_from_image(cmd_buffer, image,
false);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: clean up radv_handle_image_transition() a bit
Module: Mesa
Branch: master
Commit: 790f6e47182d4f1b1b85b449f29b6fdd4954074f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=790f6e47182d4f1b1b85b449f29b6fdd4954074f
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:46 2018 +0200
radv: clean up radv_handle_image_transition() a bit
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 270dcd5a9e..a74bad1981 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3718,6 +3718,9 @@ static void radv_handle_depth_image_transition(struct
radv_cmd_buffer *cmd_buffe
const VkImageSubresourceRange
*range,
VkImageAspectFlags
pending_clears)
{
+ if (!radv_image_has_htile(image))
+ return;
+
if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
(pending_clears & vk_format_aspects(image->vk_format)) ==
vk_format_aspects(image->vk_format) &&
cmd_buffer->state.render_area.offset.x == 0 &&
cmd_buffer->state.render_area.offset.y == 0 &&
@@ -3867,18 +3870,24 @@ static void radv_handle_image_transition(struct
radv_cmd_buffer *cmd_buffer,
return;
}
- unsigned src_queue_mask = radv_image_queue_family_mask(image,
src_family, cmd_buffer->queue_family_index);
- unsigned dst_queue_mask = radv_image_queue_family_mask(image,
dst_family, cmd_buffer->queue_family_index);
+ unsigned src_queue_mask =
+ radv_image_queue_family_mask(image, src_family,
+cmd_buffer->queue_family_index);
+ unsigned dst_queue_mask =
+ radv_image_queue_family_mask(image, dst_family,
+cmd_buffer->queue_family_index);
- if (radv_image_has_htile(image))
- radv_handle_depth_image_transition(cmd_buffer, image,
src_layout,
- dst_layout, src_queue_mask,
- dst_queue_mask, range,
- pending_clears);
-
- radv_handle_color_image_transition(cmd_buffer, image, src_layout,
- dst_layout, src_queue_mask,
- dst_queue_mask, range);
+ if (vk_format_is_depth(image->vk_format)) {
+ radv_handle_depth_image_transition(cmd_buffer, image,
+ src_layout, dst_layout,
+ src_queue_mask,
dst_queue_mask,
+ range, pending_clears);
+ } else {
+ radv_handle_color_image_transition(cmd_buffer, image,
+ src_layout, dst_layout,
+ src_queue_mask,
dst_queue_mask,
+ range);
+ }
}
void radv_CmdPipelineBarrier(
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: make radv_initialise_cmask() static
Module: Mesa
Branch: master
Commit: fde7b90ecf6fe74e977e5676acc9454de5d5d9e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fde7b90ecf6fe74e977e5676acc9454de5d5d9e4
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:47 2018 +0200
radv: make radv_initialise_cmask() static
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
src/amd/vulkan/radv_private.h| 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a74bad1981..8fe96b2e50 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3753,8 +3753,8 @@ static void radv_handle_depth_image_transition(struct
radv_cmd_buffer *cmd_buffe
}
}
-void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value)
{
struct radv_cmd_state *state = &cmd_buffer->state;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index df8fe891dc..1869604e9e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1728,8 +1728,6 @@ void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
uint32_t descriptorWriteCount,
const VkWriteDescriptorSet
*pDescriptorWrites);
-void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value);
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_init_color_image_metadata() helper
Module: Mesa
Branch: master
Commit: d5812b900b68ec639a0b305e62712c182b9fa5d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5812b900b68ec639a0b305e62712c182b9fa5d6
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:48 2018 +0200
radv: add radv_init_color_image_metadata() helper
In order to separate initialization from decompression. In the
future, that will allow us to init DCC/FMASK/CMASK in one shot.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 51
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8fe96b2e50..48877bde4a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3774,12 +3774,7 @@ static void radv_handle_cmask_image_transition(struct
radv_cmd_buffer *cmd_buffe
unsigned dst_queue_mask,
const VkImageSubresourceRange
*range)
{
- if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
- if (radv_image_has_fmask(image))
- radv_initialise_cmask(cmd_buffer, image, 0xu);
- else
- radv_initialise_cmask(cmd_buffer, image, 0xu);
- } else if (radv_layout_can_fast_clear(image, src_layout,
src_queue_mask) &&
+ if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
}
@@ -3809,10 +3804,6 @@ static void radv_handle_dcc_image_transition(struct
radv_cmd_buffer *cmd_buffer,
{
if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
radv_initialize_dcc(cmd_buffer, image, 0xu);
- } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
- radv_initialize_dcc(cmd_buffer, image,
- radv_layout_dcc_compressed(image,
dst_layout, dst_queue_mask) ?
-0x20202020u : 0xu);
} else if (radv_layout_dcc_compressed(image, src_layout,
src_queue_mask) &&
!radv_layout_dcc_compressed(image, dst_layout,
dst_queue_mask)) {
radv_decompress_dcc(cmd_buffer, image, range);
@@ -3823,6 +3814,39 @@ static void radv_handle_dcc_image_transition(struct
radv_cmd_buffer *cmd_buffer,
}
/**
+ * Initialize DCC/FMASK/CMASK metadata for a color image.
+ */
+static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image,
+ VkImageLayout src_layout,
+ VkImageLayout dst_layout,
+ unsigned src_queue_mask,
+ unsigned dst_queue_mask)
+{
+ if (radv_image_has_cmask(image)) {
+ uint32_t value = 0xu; /* Fully expanded mode. */
+
+ /* TODO: clarify this. */
+ if (radv_image_has_fmask(image)) {
+ value = 0xu;
+ }
+
+ radv_initialise_cmask(cmd_buffer, image, value);
+ }
+
+ if (radv_image_has_dcc(image)) {
+ uint32_t value = 0xu; /* Fully expanded mode. */
+
+ if (radv_layout_dcc_compressed(image, dst_layout,
+ dst_queue_mask)) {
+ value = 0x20202020u;
+ }
+
+ radv_initialize_dcc(cmd_buffer, image, value);
+ }
+}
+
+/**
* Handle color image transitions for DCC/FMASK/CMASK.
*/
static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer,
@@ -3833,6 +3857,13 @@ static void radv_handle_color_image_transition(struct
radv_cmd_buffer *cmd_buffe
unsigned dst_queue_mask,
const VkImageSubresourceRange
*range)
{
+ if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+ radv_init_color_image_metadata(cmd_buffer, image,
+ src_layout, dst_layout,
+ src_queue_mask, dst_queue_mask);
+ return;
+ }
+
if (radv_image_has_dcc(image))
radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
dst_layout, src_queue_mask,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: handle DCC image transitions before CMASK/FMASK transitions
Module: Mesa Branch: master Commit: c6b1f1c97a2f2b7079a7f9c870903f20ea6de8f0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6b1f1c97a2f2b7079a7f9c870903f20ea6de8f0 Author: Samuel Pitoiset Date: Fri Apr 13 19:14:44 2018 +0200 radv: handle DCC image transitions before CMASK/FMASK transitions Mostly because DCC implies a fast-clear eliminate and we should be able to skip some DCC decompressions by setting a predicate like for CMASK and FMASK. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Niuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f73526b5fc..92c00f5394 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3854,15 +3854,15 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, dst_queue_mask, range, pending_clears); - if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) - radv_handle_cmask_image_transition(cmd_buffer, image, src_layout, - dst_layout, src_queue_mask, - dst_queue_mask, range); - if (radv_image_has_dcc(image)) radv_handle_dcc_image_transition(cmd_buffer, image, src_layout, dst_layout, src_queue_mask, dst_queue_mask, range); + + if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) + radv_handle_cmask_image_transition(cmd_buffer, image, src_layout, + dst_layout, src_queue_mask, + dst_queue_mask, range); } void radv_CmdPipelineBarrier( ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: handle CMASK/FMASK transitions only if DCC is disabled
Module: Mesa
Branch: master
Commit: 7e84d698611fce27c625a270408fa0137e4b803b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e84d698611fce27c625a270408fa0137e4b803b
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:50 2018 +0200
radv: handle CMASK/FMASK transitions only if DCC is disabled
DCC implies a fast-clear eliminate, so I think this sounds
reasonable.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index afe953d90c..72fb6d6357 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3841,9 +3841,7 @@ static void radv_handle_color_image_transition(struct
radv_cmd_buffer *cmd_buffe
!radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image,
range);
}
- }
-
- if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
+ } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
if (radv_layout_can_fast_clear(image, src_layout,
src_queue_mask) &&
!radv_layout_can_fast_clear(image, dst_layout,
dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image,
range);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: clean up radv_decompress_resolve_subpass_src()
Module: Mesa
Branch: master
Commit: 62510846b6ed7083b384d7f5b9765aebf34b2e3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62510846b6ed7083b384d7f5b9765aebf34b2e3a
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:52 2018 +0200
radv: clean up radv_decompress_resolve_subpass_src()
To handle the source color image transitions in the same place.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_meta_resolve.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index 1828eb37f4..d66f1c9f93 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -689,18 +689,15 @@ radv_decompress_resolve_subpass_src(struct
radv_cmd_buffer *cmd_buffer)
dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
- struct radv_image_view *src_iview =
- fb->attachments[src_att.attachment].attachment;
+ struct radv_image *src_image =
+ fb->attachments[src_att.attachment].attachment->image;
- VkImageSubresourceRange range;
- range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
- range.baseMipLevel = 0;
- range.levelCount = 1;
- range.baseArrayLayer = 0;
- range.layerCount = 1;
+ VkImageResolve region = {};
+ region.srcSubresource.baseArrayLayer = 0;
+ region.srcSubresource.mipLevel = 0;
+ region.srcSubresource.layerCount = 1;
- radv_fast_clear_flush_image_inplace(cmd_buffer,
- src_iview->image, &range);
+ radv_decompress_resolve_src(cmd_buffer, src_image, 1, ®ion);
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: don't fast-clear eliminate after resolving a subpass with compute
Module: Mesa
Branch: master
Commit: 56a171a499c861c261c2b0821951e05fde845af6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56a171a499c861c261c2b0821951e05fde845af6
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:51 2018 +0200
radv: don't fast-clear eliminate after resolving a subpass with compute
That looks useless, and I think radv_handle_image_transition()
will do a fast-clear eliminate because it's called after the
resolve.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_meta_resolve_cs.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 6d605aba01..628208d635 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -517,18 +517,4 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer)
}
radv_meta_restore(&saved_state, cmd_buffer);
-
- for (uint32_t i = 0; i < subpass->color_count; ++i) {
- VkAttachmentReference dest_att =
subpass->resolve_attachments[i];
- struct radv_image *dst_img =
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
- if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
- continue;
- VkImageSubresourceRange range;
- range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
- range.baseMipLevel = 0;
- range.levelCount = 1;
- range.baseArrayLayer = 0;
- range.layerCount = 1;
- radv_fast_clear_flush_image_inplace(cmd_buffer, dst_img,
&range);
- }
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_handle_color_image_transition() helper
Module: Mesa
Branch: master
Commit: 6967d32bebf84b715d4fd6dd4a750d1fc75f8991
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6967d32bebf84b715d4fd6dd4a750d1fc75f8991
Author: Samuel Pitoiset
Date: Fri Apr 13 19:14:45 2018 +0200
radv: add radv_handle_color_image_transition() helper
To handle CMASK, FMASK and DCC transitions in the same place.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Niuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 92c00f5394..270dcd5a9e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3819,6 +3819,28 @@ static void radv_handle_dcc_image_transition(struct
radv_cmd_buffer *cmd_buffer,
}
}
+/**
+ * Handle color image transitions for DCC/FMASK/CMASK.
+ */
+static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer,
+ struct radv_image *image,
+ VkImageLayout src_layout,
+ VkImageLayout dst_layout,
+ unsigned src_queue_mask,
+ unsigned dst_queue_mask,
+ const VkImageSubresourceRange
*range)
+{
+ if (radv_image_has_dcc(image))
+ radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
+dst_layout, src_queue_mask,
+dst_queue_mask, range);
+
+ if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
+ radv_handle_cmask_image_transition(cmd_buffer, image,
src_layout,
+ dst_layout, src_queue_mask,
+ dst_queue_mask, range);
+}
+
static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkImageLayout src_layout,
@@ -3854,15 +3876,9 @@ static void radv_handle_image_transition(struct
radv_cmd_buffer *cmd_buffer,
dst_queue_mask, range,
pending_clears);
- if (radv_image_has_dcc(image))
- radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
-dst_layout, src_queue_mask,
-dst_queue_mask, range);
-
- if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
- radv_handle_cmask_image_transition(cmd_buffer, image,
src_layout,
- dst_layout, src_queue_mask,
- dst_queue_mask, range);
+ radv_handle_color_image_transition(cmd_buffer, image, src_layout,
+ dst_layout, src_queue_mask,
+ dst_queue_mask, range);
}
void radv_CmdPipelineBarrier(
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix radv_layout_dcc_compressed() when image doesn't have DCC
Module: Mesa
Branch: master
Commit: 9eac49246cdc501530418e8bd2a3e6d47173332b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9eac49246cdc501530418e8bd2a3e6d47173332b
Author: Samuel Pitoiset
Date: Wed Apr 11 21:34:43 2018 +0200
radv: fix radv_layout_dcc_compressed() when image doesn't have DCC
num_dcc_levels means that DCC is supported, but this doesn't
mean that it's enabled by the driver. Instead, we should rely
on radv_image_has_dcc().
This fixes some multisample regressions since 0babc8e5d66
("radv: fix picking the method for resolve subpass") on Vega.
This is because the resolve method changed from HW to FS, but
those fails are totally unexpected, so there might some
differences between Polaris and Vega here.
Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer
dest.")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index acb569203d..a14e7c18b2 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -1241,7 +1241,7 @@ bool radv_layout_dcc_compressed(const struct radv_image
*image,
(queue_mask & (1u << RADV_QUEUE_COMPUTE)))
return false;
- return image->surface.num_dcc_levels > 0 && layout !=
VK_IMAGE_LAYOUT_GENERAL;
+ return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_decompress_resolve_{subpass}_src() helpers
Module: Mesa
Branch: master
Commit: ab0e625a671d19bb6a736d663bbc6fa5fd9ecd06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab0e625a671d19bb6a736d663bbc6fa5fd9ecd06
Author: Samuel Pitoiset
Date: Wed Apr 11 14:09:16 2018 +0200
radv: add radv_decompress_resolve_{subpass}_src() helpers
This helper shares common code before resolving using either
a fragment or a compute shader.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta.h| 7 +
src/amd/vulkan/radv_meta_resolve.c| 58 +++
src/amd/vulkan/radv_meta_resolve_cs.c | 34 ++--
src/amd/vulkan/radv_meta_resolve_fs.c | 28 +++--
4 files changed, 73 insertions(+), 54 deletions(-)
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 57b76c1326..47eec5cd6a 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -191,6 +191,13 @@ void radv_meta_resolve_fragment_image(struct
radv_cmd_buffer *cmd_buffer,
uint32_t region_count,
const VkImageResolve *regions);
+void radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer);
+
+void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
+struct radv_image *src_image,
+uint32_t region_count,
+const VkImageResolve *regions);
+
void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
struct radv_image *linear_image);
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index e932976df2..1828eb37f4 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -670,3 +670,61 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer)
cmd_buffer->state.subpass = subpass;
radv_meta_restore(&saved_state, cmd_buffer);
}
+
+/**
+ * Decompress CMask/FMask before resolving a multisampled source image inside a
+ * subpass.
+ */
+void
+radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
+{
+ const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+ struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
+
+ for (uint32_t i = 0; i < subpass->color_count; ++i) {
+ VkAttachmentReference src_att = subpass->color_attachments[i];
+ VkAttachmentReference dest_att =
subpass->resolve_attachments[i];
+
+ if (src_att.attachment == VK_ATTACHMENT_UNUSED ||
+ dest_att.attachment == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ struct radv_image_view *src_iview =
+ fb->attachments[src_att.attachment].attachment;
+
+ VkImageSubresourceRange range;
+ range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+ range.baseMipLevel = 0;
+ range.levelCount = 1;
+ range.baseArrayLayer = 0;
+ range.layerCount = 1;
+
+ radv_fast_clear_flush_image_inplace(cmd_buffer,
+ src_iview->image, &range);
+ }
+}
+
+/**
+ * Decompress CMask/FMask before resolving a multisampled source image.
+ */
+void
+radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *src_image,
+ uint32_t region_count,
+ const VkImageResolve *regions)
+{
+ for (uint32_t r = 0; r < region_count; ++r) {
+ const VkImageResolve *region = ®ions[r];
+ const uint32_t src_base_layer =
+ radv_meta_get_iview_layer(src_image,
®ion->srcSubresource,
+ ®ion->srcOffset);
+ VkImageSubresourceRange range;
+ range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+ range.baseMipLevel = region->srcSubresource.mipLevel;
+ range.levelCount = 1;
+ range.baseArrayLayer = src_base_layer;
+ range.layerCount = region->srcSubresource.layerCount;
+
+ radv_fast_clear_flush_image_inplace(cmd_buffer, src_image,
&range);
+ }
+}
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c
b/src/amd/vulkan/radv_meta_resolve_cs.c
index ca8f826f53..6d605aba01 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -388,19 +388,8 @@ void radv_meta_resolve_compute_image(struct
radv_cmd_buffer *cmd_buffer,
{
struct radv_meta_saved_state saved_state;
- for (uint32_t r = 0; r < region_count; ++r) {
- const VkImageResolve *region
Mesa (master): radv: add radv_init_dcc_control_reg() helper
Module: Mesa
Branch: master
Commit: ed93d90a67d31fc396e64d566e2ac58e2994a4e3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed93d90a67d31fc396e64d566e2ac58e2994a4e3
Author: Samuel Pitoiset
Date: Wed Apr 11 14:09:15 2018 +0200
radv: add radv_init_dcc_control_reg() helper
And add some comments.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 84 +++-
1 file changed, 52 insertions(+), 32 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 22e8f1e7a7..d912fac8ec 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3450,6 +3450,57 @@ static uint32_t radv_surface_max_layer_count(struct
radv_image_view *iview)
return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth :
(iview->base_layer + iview->layer_count);
}
+static uint32_t
+radv_init_dcc_control_reg(struct radv_device *device,
+ struct radv_image_view *iview)
+{
+ unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
+ unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
+ unsigned max_compressed_block_size;
+ unsigned independent_64b_blocks;
+
+ if (device->physical_device->rad_info.chip_class < VI)
+ return 0;
+
+ if (iview->image->info.samples > 1) {
+ if (iview->image->surface.bpe == 1)
+ max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_64B;
+ else if (iview->image->surface.bpe == 2)
+ max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_128B;
+ }
+
+ if (!device->physical_device->rad_info.has_dedicated_vram) {
+ /* amdvlk: [min-compressed-block-size] should be set to 32 for
+* dGPU and 64 for APU because all of our APUs to date use
+* DIMMs which have a request granularity size of 64B while all
+* other chips have a 32B request size.
+*/
+ min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
+ }
+
+ if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
+ /* If this DCC image is potentially going to be used in texture
+* fetches, we need some special settings.
+*/
+ independent_64b_blocks = 1;
+ max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
+ } else {
+ /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
+* MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
+* big as possible for better compression state.
+*/
+ independent_64b_blocks = 0;
+ max_compressed_block_size = max_uncompressed_block_size;
+ }
+
+ return
S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
+ S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
+ S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
+ S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
+}
+
static void
radv_initialise_color_surface(struct radv_device *device,
struct radv_color_buffer_info *cb,
@@ -3604,38 +3655,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (radv_dcc_enabled(iview->image, iview->base_mip))
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
- if (device->physical_device->rad_info.chip_class >= VI) {
- unsigned max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_256B;
- unsigned min_compressed_block_size =
V_028C78_MIN_BLOCK_SIZE_32B;
- unsigned independent_64b_blocks = 0;
- unsigned max_compressed_block_size;
-
- /* amdvlk: [min-compressed-block-size] should be set to 32 for
dGPU and
- 64 for APU because all of our APUs to date use DIMMs which
have
- a request granularity size of 64B while all other chips have
a
- 32B request size */
- if (!device->physical_device->rad_info.has_dedicated_vram)
- min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
-
- if (iview->image->info.samples > 1) {
- if (iview->image->surface.bpe == 1)
- max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_64B;
- else if (iview->image->surface.bpe == 2)
- max_uncompressed_block_size =
V_028C78_MAX_BLOCK_SIZE_128B;
- }
Mesa (master): radv: add shader BOs to the list at pipeline bind time
Module: Mesa
Branch: master
Commit: 9f6a28eb27ca059cbadfa5e277bfe4509a426615
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f6a28eb27ca059cbadfa5e277bfe4509a426615
Author: Samuel Pitoiset
Date: Tue Apr 10 14:09:04 2018 +0200
radv: add shader BOs to the list at pipeline bind time
Otherwise, the shader BOs are not added to the list on SI because
prefetching isn't supported. Calling radv_cs_add_buffer() in the
prefetch codepath was a bad idea.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105952
Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2")
Signed-off-by: Samuel Pitoiset
Tested-by: Turo Lamminen
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4e89969016..3b1d6aedc8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -625,8 +625,6 @@ static void
radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *shader)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint64_t va;
if (!shader)
@@ -634,7 +632,6 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer,
va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
- radv_cs_add_buffer(ws, cs, shader->bo, 8);
si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
}
@@ -702,6 +699,18 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer)
radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
+ for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
+ if (!pipeline->shaders[i])
+ continue;
+
+ radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+ pipeline->shaders[i]->bo, 8);
+ }
+
+ if (radv_pipeline_has_gs(pipeline))
+ radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+ pipeline->gs_copy_shader->bo, 8);
+
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
@@ -2280,6 +2289,9 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer)
MAX2(cmd_buffer->compute_scratch_size_needed,
pipeline->max_waves *
pipeline->scratch_bytes_per_wave);
+ radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+ pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
+
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix picking the method for resolve subpass
Module: Mesa
Branch: master
Commit: 0babc8e5d665e54783c926b89183ab9a596aa04c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0babc8e5d665e54783c926b89183ab9a596aa04c
Author: Samuel Pitoiset
Date: Tue Apr 10 16:00:56 2018 +0200
radv: fix picking the method for resolve subpass
The source and destination image parameters were swapped.
No CTS changes on Polaris10, but I suspect this might
fix something.
Fixes: 2a04f5481df ("radv/meta: select resolve paths")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_resolve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index bee398378c..e932976df2 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -621,7 +621,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer)
struct radv_image *dst_img =
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
struct radv_image *src_img =
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment->image;
- radv_pick_resolve_method_images(dst_img, src_img,
dest_att.layout, cmd_buffer, &resolve_method);
+ radv_pick_resolve_method_images(src_img, dst_img,
dest_att.layout, cmd_buffer, &resolve_method);
if (resolve_method == RESOLVE_FRAGMENT) {
break;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: fix prefetching of vertex shader and VBOs on SI
Module: Mesa
Branch: master
Commit: 04e609f1f8cf633f33b20de7f8c603e301379b74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04e609f1f8cf633f33b20de7f8c603e301379b74
Author: Samuel Pitoiset
Date: Mon Apr 9 14:38:16 2018 +0200
radv: fix prefetching of vertex shader and VBOs on SI
Forgot one check... Too many mistakes for a simple change.
Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders on CIK and older
chips")
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e8a6d9be15..6cd798dbfc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3083,7 +3083,7 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
*/
si_emit_cache_flush(cmd_buffer);
- if (cmd_buffer->state.prefetch_L2_mask) {
+ if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
/* Only prefetch the vertex shader and VBO descriptors
* in order to start the draw as soon as possible.
*/
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add RADV_NUM_PHYSICAL_VGPRS constant
Module: Mesa
Branch: master
Commit: 466aba9fa2fd18ffbd9ca2377a51f18a0b9ed11f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=466aba9fa2fd18ffbd9ca2377a51f18a0b9ed11f
Author: Samuel Pitoiset
Date: Fri Apr 6 14:10:34 2018 +0200
radv: add RADV_NUM_PHYSICAL_VGPRS constant
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 6 --
src/amd/vulkan/radv_shader.h | 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 59ad2f3819..eaf24dcdee 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -633,7 +633,9 @@ generate_shader_stats(struct radv_device *device,
radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
if (conf->num_vgprs)
- max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
+ max_simd_waves =
+ MIN2(max_simd_waves,
+RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
/* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
* that PS can use.
@@ -712,7 +714,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
VkShaderStatisticsInfoAMD statistics = {};
statistics.shaderStageMask = shaderStage;
- statistics.numPhysicalVgprs = 256;
+ statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
statistics.numPhysicalSgprs =
radv_get_num_physical_sgprs(device->physical_device);
statistics.numAvailableSgprs =
statistics.numPhysicalSgprs;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index f5c0645b5f..cbb7394eea 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -46,6 +46,8 @@
// Match MAX_SETS from radv_descriptor_set.h
#define RADV_UD_MAX_SETS MAX_SETS
+#define RADV_NUM_PHYSICAL_VGPRS 256
+
struct radv_shader_module {
struct nir_shader *nir;
unsigned char sha1[20];
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_get_num_physical_sgprs() helper
Module: Mesa
Branch: master
Commit: 2f7bb93146743497a6b9fa703b0135c22af6fe31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f7bb93146743497a6b9fa703b0135c22af6fe31
Author: Samuel Pitoiset
Date: Fri Apr 6 14:06:24 2018 +0200
radv: add radv_get_num_physical_sgprs() helper
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.c | 15 ---
src/amd/vulkan/radv_shader.h | 6 ++
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f46beab8c1..59ad2f3819 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -597,15 +597,6 @@ radv_get_shader_name(struct radv_shader_variant *var,
gl_shader_stage stage)
};
}
-static uint32_t
-get_total_sgprs(struct radv_device *device)
-{
- if (device->physical_device->rad_info.chip_class >= VI)
- return 800;
- else
- return 512;
-}
-
static void
generate_shader_stats(struct radv_device *device,
struct radv_shader_variant *variant,
@@ -637,7 +628,9 @@ generate_shader_stats(struct radv_device *device,
}
if (conf->num_sgprs)
- max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) /
conf->num_sgprs);
+ max_simd_waves =
+ MIN2(max_simd_waves,
+
radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
if (conf->num_vgprs)
max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
@@ -720,7 +713,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
VkShaderStatisticsInfoAMD statistics = {};
statistics.shaderStageMask = shaderStage;
statistics.numPhysicalVgprs = 256;
- statistics.numPhysicalSgprs = get_total_sgprs(device);
+ statistics.numPhysicalSgprs =
radv_get_num_physical_sgprs(device->physical_device);
statistics.numAvailableSgprs =
statistics.numPhysicalSgprs;
if (stage == MESA_SHADER_COMPUTE) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index ae30d6125b..f5c0645b5f 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -362,4 +362,10 @@ static inline unsigned
shader_io_get_unique_index(gl_varying_slot slot)
unreachable("illegal slot in get unique index\n");
}
+static inline uint32_t
+radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
+{
+ return physical_device->rad_info.chip_class >= VI ? 800 : 512;
+}
+
#endif
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vulkan: Update the XML and headers to 1.1.72
Module: Mesa Branch: master Commit: b30dec738a66d5427916b56f4428bb3d45dd4756 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b30dec738a66d5427916b56f4428bb3d45dd4756 Author: Samuel Pitoiset Date: Fri Apr 6 12:39:41 2018 +0200 vulkan: Update the XML and headers to 1.1.72 Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- include/vulkan/vulkan_android.h | 66 ++ include/vulkan/vulkan_core.h| 144 +++- src/vulkan/registry/vk.xml | 286 +--- 3 files changed, 445 insertions(+), 51 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=b30dec738a66d5427916b56f4428bb3d45dd4756 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: implement VK_AMD_shader_core_properties
Module: Mesa
Branch: master
Commit: 56a4d03b0cbc4477e8074652919994b3eaac0b94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56a4d03b0cbc4477e8074652919994b3eaac0b94
Author: Samuel Pitoiset
Date: Fri Apr 6 12:40:33 2018 +0200
radv: implement VK_AMD_shader_core_properties
Simple extension that only returns information for AMD hw.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 40 +++
src/amd/vulkan/radv_extensions.py | 1 +
2 files changed, 41 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index de184603eb..4fc7392e65 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -961,6 +961,46 @@ void radv_GetPhysicalDeviceProperties2(
properties->filterMinmaxSingleComponentFormats = true;
break;
}
+ case
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
+ VkPhysicalDeviceShaderCorePropertiesAMD *properties =
+ (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
+
+ /* Shader engines. */
+ properties->shaderEngineCount =
+ pdevice->rad_info.max_se;
+ properties->shaderArraysPerEngineCount =
+ pdevice->rad_info.max_sh_per_se;
+ properties->computeUnitsPerShaderArray =
+ pdevice->rad_info.num_good_compute_units /
+ (pdevice->rad_info.max_se *
+pdevice->rad_info.max_sh_per_se);
+ properties->simdPerComputeUnit = 4;
+ properties->wavefrontsPerSimd =
+ pdevice->rad_info.family == CHIP_TONGA ||
+ pdevice->rad_info.family == CHIP_ICELAND ||
+ pdevice->rad_info.family == CHIP_POLARIS10 ||
+ pdevice->rad_info.family == CHIP_POLARIS11 ||
+ pdevice->rad_info.family == CHIP_POLARIS12 ? 8
: 10;
+ properties->wavefrontSize = 64;
+
+ /* SGPR. */
+ properties->sgprsPerSimd =
+ radv_get_num_physical_sgprs(pdevice);
+ properties->minSgprAllocation =
+ pdevice->rad_info.chip_class >= VI ? 16 : 8;
+ properties->maxSgprAllocation =
+ pdevice->rad_info.family == CHIP_TONGA ||
+ pdevice->rad_info.family == CHIP_ICELAND ? 96 :
104;
+ properties->sgprAllocationGranularity =
+ pdevice->rad_info.chip_class >= VI ? 16 : 8;
+
+ /* VGPR. */
+ properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
+ properties->minVgprAllocation = 4;
+ properties->maxVgprAllocation = 256;
+ properties->vgprAllocationGranularity = 4;
+ break;
+ }
default:
break;
}
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index bc63a34896..a25db637e2 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -96,6 +96,7 @@ EXTENSIONS = [
Extension('VK_AMD_draw_indirect_count', 1, True),
Extension('VK_AMD_gcn_shader',1, True),
Extension('VK_AMD_rasterization_order', 1,
'device->has_out_of_order_rast'),
+Extension('VK_AMD_shader_core_properties',1, True),
Extension('VK_AMD_shader_info', 1, True),
Extension('VK_AMD_shader_trinary_minmax', 1, True),
]
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_use_dcc_for_image() helper
Module: Mesa
Branch: master
Commit: 95d5ad80e9d9670a7dd8c6fd7891b97fd006b44d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=95d5ad80e9d9670a7dd8c6fd7891b97fd006b44d
Author: Samuel Pitoiset
Date: Fri Mar 30 16:46:14 2018 +0200
radv: add radv_use_dcc_for_image() helper
And add some TODOs.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 98 +++--
1 file changed, 68 insertions(+), 30 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index dc4781231d..86d97ff83b 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -103,6 +103,71 @@ radv_use_tc_compat_htile_for_image(struct radv_device
*device,
return true;
}
+static bool
+radv_use_dcc_for_image(struct radv_device *device,
+ const struct radv_image_create_info *create_info,
+ const VkImageCreateInfo *pCreateInfo)
+{
+ bool dcc_compatible_formats;
+ bool blendable;
+
+ /* DCC (Delta Color Compression) is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < VI)
+ return false;
+
+ if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
+ return false;
+
+ /* TODO: Enable DCC for storage images. */
+ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
+ (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
+ return false;
+
+ if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
+ return false;
+
+ /* TODO: Enable DCC for mipmaps and array layers. */
+ if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
+ return false;
+
+ if (create_info->scanout)
+ return false;
+
+ /* TODO: Enable DCC for MSAA textures. */
+ if (pCreateInfo->samples >= 2)
+ return false;
+
+ /* Determine if the formats are DCC compatible. */
+ dcc_compatible_formats =
+ radv_is_colorbuffer_format_supported(pCreateInfo->format,
+&blendable);
+
+ if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
+ const struct VkImageFormatListCreateInfoKHR *format_list =
+ (const struct VkImageFormatListCreateInfoKHR *)
+ vk_find_struct_const(pCreateInfo->pNext,
+
IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ /* We have to ignore the existence of the list if
viewFormatCount = 0 */
+ if (format_list && format_list->viewFormatCount) {
+ /* compatibility is transitive, so we only need to check
+* one format with everything else. */
+ for (unsigned i = 0; i < format_list->viewFormatCount;
++i) {
+ if
(!radv_dcc_formats_compatible(pCreateInfo->format,
+
format_list->pViewFormats[i]))
+ dcc_compatible_formats = false;
+ }
+ } else {
+ dcc_compatible_formats = false;
+ }
+ }
+
+ if (!dcc_compatible_formats)
+ return false;
+
+ return true;
+}
+
static int
radv_init_surface(struct radv_device *device,
struct radeon_surf *surface,
@@ -112,7 +177,7 @@ radv_init_surface(struct radv_device *device,
unsigned array_mode = radv_choose_tiling(device, create_info);
const struct vk_format_description *desc =
vk_format_description(pCreateInfo->format);
- bool is_depth, is_stencil, blendable;
+ bool is_depth, is_stencil;
is_depth = vk_format_has_depth(desc);
is_stencil = vk_format_has_stencil(desc);
@@ -158,36 +223,9 @@ radv_init_surface(struct radv_device *device,
surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- bool dcc_compatible_formats =
radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
- if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
- const struct VkImageFormatListCreateInfoKHR *format_list =
- (const struct VkImageFormatListCreateInfoKHR *)
- vk_find_struct_const(pCreateInfo->pNext,
-
IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
-
- /* We have to ignore the existence of the list if
viewFormatCount = 0 */
- if (format_list && format_list->viewFormatCount) {
- /* compatibility is transitive, so
Mesa (master): radv: simplify a check in radv_initialise_color_surface()
Module: Mesa
Branch: master
Commit: 2692736cee84931ca9b50faaa02529f4b78fe312
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2692736cee84931ca9b50faaa02529f4b78fe312
Author: Samuel Pitoiset
Date: Fri Apr 6 16:02:16 2018 +0200
radv: simplify a check in radv_initialise_color_surface()
If the image has FMASK metadata, the number of samples is > 1
because radv_image_can_enable_fmask() handles that already.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 846639eab0..39e320e377 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3548,7 +3548,7 @@ radv_initialise_color_surface(struct radv_device *device,
format != V_028C70_COLOR_24_8) |
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
- if ((iview->image->info.samples > 1) &&
radv_image_has_fmask(iview->image)) {
+ if (radv_image_has_fmask(iview->image)) {
cb->cb_color_info |= S_028C70_COMPRESSION(1);
if (device->physical_device->rad_info.chip_class == SI) {
unsigned fmask_bankh =
util_logbase2(iview->image->fmask.bank_height);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: rename radv_image_is_tc_compat_htile()
Module: Mesa
Branch: master
Commit: fab5fe4284ee8087c2a38df0cb7af76ac591b5ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fab5fe4284ee8087c2a38df0cb7af76ac591b5ee
Author: Samuel Pitoiset
Date: Fri Apr 6 16:07:22 2018 +0200
radv: rename radv_image_is_tc_compat_htile()
... to radv_use_tc_compat_htile_for_image(). This function
name makes more sense to me because we want to know if and
only if TC-compat HTILE should be used.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 1a8352fea2..dc4781231d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -65,8 +65,8 @@ radv_choose_tiling(struct radv_device *device,
}
static bool
-radv_image_is_tc_compat_htile(struct radv_device *device,
- const VkImageCreateInfo *pCreateInfo)
+radv_use_tc_compat_htile_for_image(struct radv_device *device,
+ const VkImageCreateInfo *pCreateInfo)
{
/* TC-compat HTILE is only available for GFX8+. */
if (device->physical_device->rad_info.chip_class < VI)
@@ -149,7 +149,7 @@ radv_init_surface(struct radv_device *device,
if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
- if (radv_image_is_tc_compat_htile(device, pCreateInfo))
+ if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: clean up radv_vi_dcc_enabled()
Module: Mesa
Branch: master
Commit: ed41e776d03d27d2874f9b02e00bbd1f2226528f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed41e776d03d27d2874f9b02e00bbd1f2226528f
Author: Samuel Pitoiset
Date: Fri Apr 6 16:00:08 2018 +0200
radv: clean up radv_vi_dcc_enabled()
And rename to radv_dcc_enabled() to be consistent.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 2 +-
src/amd/vulkan/radv_image.c | 2 +-
src/amd/vulkan/radv_private.h | 16 ++--
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index caf6f00e63..846639eab0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3560,7 +3560,7 @@ radv_initialise_color_surface(struct radv_device *device,
!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
- if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
+ if (radv_dcc_enabled(iview->image, iview->base_mip))
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
if (device->physical_device->rad_info.chip_class >= VI) {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 56b9ba1cda..1a8352fea2 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -294,7 +294,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
- if (!is_storage_image && radv_vi_dcc_enabled(image,
first_level)) {
+ if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index f954d67874..97f4cf657d 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1384,12 +1384,6 @@ bool radv_layout_dcc_compressed(const struct radv_image
*image,
VkImageLayout layout,
unsigned queue_mask);
-static inline bool
-radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
-{
- return image->surface.dcc_size && level < image->surface.num_dcc_levels;
-}
-
/**
* Return whether the image has CMASK metadata for color surfaces.
*/
@@ -1418,6 +1412,16 @@ radv_image_has_dcc(const struct radv_image *image)
}
/**
+ * Return whether DCC metadata is enabled for a level.
+ */
+static inline bool
+radv_dcc_enabled(const struct radv_image *image, unsigned level)
+{
+ return radv_image_has_dcc(image) &&
+ level < image->surface.num_dcc_levels;
+}
+
+/**
* Return whether the image has HTILE metadata for depth surfaces.
*/
static inline bool
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_clear_{cmask,dcc} helpers
Module: Mesa
Branch: master
Commit: f882c62218fdb184c57e65b9d84b6214d8eef156
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f882c62218fdb184c57e65b9d84b6214d8eef156
Author: Samuel Pitoiset
Date: Fri Apr 6 12:22:02 2018 +0200
radv: add radv_clear_{cmask,dcc} helpers
They will help for DCC MSAA textures and if we support mipmaps
in the future.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 8 ++--
src/amd/vulkan/radv_meta.h| 5 +
src/amd/vulkan/radv_meta_clear.c | 27 +--
src/amd/vulkan/radv_meta_fast_clear.c | 4 +---
4 files changed, 29 insertions(+), 15 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d9f12a351e..7003818b5b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3617,9 +3617,7 @@ void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
- image->offset +
image->cmask.offset,
- image->cmask.size, value);
+ state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
@@ -3651,9 +3649,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->dcc_offset,
- image->surface.dcc_size, value);
+ state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 9f3198e879..57b76c1326 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -195,6 +195,11 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer
*cmd_buffer,
struct radv_image *image,
struct radv_image *linear_image);
+uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value);
+uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value);
+
/* common nir builder helpers */
#include "nir/nir_builder.h"
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 98fb8fa6a7..678de4275f 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -859,6 +859,24 @@ fail:
return res;
}
+uint32_t
+radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
+struct radv_image *image, uint32_t value)
+{
+ return radv_fill_buffer(cmd_buffer, image->bo,
+ image->offset + image->cmask.offset,
+ image->cmask.size, value);
+}
+
+uint32_t
+radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value)
+{
+ return radv_fill_buffer(cmd_buffer, image->bo,
+ image->offset + image->dcc_offset,
+ image->surface.dcc_size, value);
+}
+
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
@@ -1020,15 +1038,12 @@ emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
- flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
- iview->image->offset +
iview->image->dcc_offset,
- iview->image->surface.dcc_size,
reset_value);
+ flush_bits = radv_clear_dcc(cmd_buffer, iview->image,
reset_value);
+
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
!can_avoid_fast_clear_elim);
} else {
- flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
- iview->image->offset +
iview->image->cmask.offse
Mesa (master): radv: clean up radv_htile_enabled()
Module: Mesa
Branch: master
Commit: e213f199079365ff03a7012b2b57f1d47843d507
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e213f199079365ff03a7012b2b57f1d47843d507
Author: Samuel Pitoiset
Date: Fri Apr 6 15:57:48 2018 +0200
radv: clean up radv_htile_enabled()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_private.h | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b4952b56e1..f954d67874 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1390,12 +1390,6 @@ radv_vi_dcc_enabled(const struct radv_image *image,
unsigned level)
return image->surface.dcc_size && level < image->surface.num_dcc_levels;
}
-static inline bool
-radv_htile_enabled(const struct radv_image *image, unsigned level)
-{
- return image->surface.htile_size && level == 0;
-}
-
/**
* Return whether the image has CMASK metadata for color surfaces.
*/
@@ -1432,6 +1426,15 @@ radv_image_has_htile(const struct radv_image *image)
return image->surface.htile_size;
}
+/**
+ * Return whether HTILE metadata is enabled for a level.
+ */
+static inline bool
+radv_htile_enabled(const struct radv_image *image, unsigned level)
+{
+ return radv_image_has_htile(image) && level == 0;
+}
+
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t
family, uint32_t queue_family);
static inline uint32_t
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_get_cmask_fast_clear_value() helper
Module: Mesa
Branch: master
Commit: 32f5174ce825d13ed3b1cb6e8c5f8091ddc5045f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32f5174ce825d13ed3b1cb6e8c5f8091ddc5045f
Author: Samuel Pitoiset
Date: Fri Apr 6 15:32:25 2018 +0200
radv: add radv_get_cmask_fast_clear_value() helper
DCC for MSAA textures are currently unsupported but that will
be used later on.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_clear.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 678de4275f..7de2f2d013 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -859,6 +859,22 @@ fail:
return res;
}
+static uint32_t
+radv_get_cmask_fast_clear_value(const struct radv_image *image)
+{
+ uint32_t value = 0; /* Default value when no DCC. */
+
+ /* The fast-clear value is different for images that have both DCC and
+* CMASK metadata.
+*/
+ if (image->surface.dcc_size) {
+ /* DCC fast clear with MSAA should clear CMASK to 0xC. */
+ return image->info.samples > 1 ? 0x : 0x;
+ }
+
+ return value;
+}
+
uint32_t
radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
@@ -970,6 +986,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image_view *iview =
fb->attachments[pass_att].attachment;
VkClearColorValue clear_value = clear_att->clearValue.color;
uint32_t clear_color[2], flush_bits;
+ uint32_t cmask_clear_value;
bool ret;
if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
@@ -1030,6 +1047,9 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
} else
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
+
+ cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
+
/* clear cmask buffer */
if (iview->image->surface.dcc_size) {
uint32_t reset_value;
@@ -1043,7 +1063,8 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
!can_avoid_fast_clear_elim);
} else {
- flush_bits = radv_clear_cmask(cmd_buffer, iview->image, 0);
+ flush_bits = radv_clear_cmask(cmd_buffer, iview->image,
+ cmask_clear_value);
}
if (post_flush) {
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpers
Module: Mesa
Branch: master
Commit: 0fc9113ac593e396d3b103bebb2713aac9d072ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fc9113ac593e396d3b103bebb2713aac9d072ff
Author: Samuel Pitoiset
Date: Fri Apr 6 15:37:28 2018 +0200
radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpers
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 18 +-
src/amd/vulkan/radv_device.c | 10 +-
src/amd/vulkan/radv_image.c | 14 +++---
src/amd/vulkan/radv_meta_clear.c | 12 ++--
src/amd/vulkan/radv_meta_copy.c | 4 ++--
src/amd/vulkan/radv_meta_decompress.c | 2 +-
src/amd/vulkan/radv_meta_fast_clear.c | 8
src/amd/vulkan/radv_meta_resolve.c| 4 ++--
src/amd/vulkan/radv_private.h | 36 +++
9 files changed, 72 insertions(+), 36 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7003818b5b..e8a6d9be15 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -947,7 +947,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
va += image->offset + image->clear_value_offset;
unsigned reg_offset = 0, reg_count = 0;
- assert(image->surface.htile_size);
+ assert(radv_image_has_htile(image));
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
++reg_count;
@@ -985,7 +985,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
va += image->offset + image->clear_value_offset;
unsigned reg_offset = 0, reg_count = 0;
- if (!image->surface.htile_size)
+ if (!radv_image_has_htile(image))
return;
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
@@ -1024,7 +1024,7 @@ radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer,
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->dcc_pred_offset;
- assert(image->surface.dcc_size);
+ assert(radv_image_has_dcc(image));
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
@@ -1045,7 +1045,7 @@ radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
- assert(image->cmask.size || image->surface.dcc_size);
+ assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
@@ -1069,7 +1069,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
- if (!image->cmask.size && !image->surface.dcc_size)
+ if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
return;
uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
@@ -3631,7 +3631,7 @@ static void radv_handle_cmask_image_transition(struct
radv_cmd_buffer *cmd_buffe
const VkImageSubresourceRange
*range)
{
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
- if (image->fmask.size)
+ if (radv_image_has_fmask(image))
radv_initialise_cmask(cmd_buffer, image, 0xu);
else
radv_initialise_cmask(cmd_buffer, image, 0xu);
@@ -3707,18 +3707,18 @@ static void radv_handle_image_transition(struct
radv_cmd_buffer *cmd_buffer,
unsigned src_queue_mask = radv_image_queue_family_mask(image,
src_family, cmd_buffer->queue_family_index);
unsigned dst_queue_mask = radv_image_queue_family_mask(image,
dst_family, cmd_buffer->queue_family_index);
- if (image->surface.htile_size)
+ if (radv_image_has_htile(image))
radv_handle_depth_image_transition(cmd_buffer, image,
src_layout,
dst_layout, src_queue_mask,
dst_queue_mask, range,
pending_clears);
- if (image->cmask.size || image->fmask.size)
+ if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
radv_handle_cmask_image_transition(cmd_buffer, image,
src_layout,
dst_layout, src_queue_mask,
dst_queue_mask, range);
- if (image->surface.dcc_size)
+ if (radv_image_has_dcc(image))
radv_handle_dcc_image_
