Re: [Mesa-dev] [PATCH 5/5] llvmpipe: consolidate the sampler and sampler view setting code
On 08/05/2012 01:27 AM, Jose Fonseca wrote:
- Original Message -
Less code. And as with softpipe, if/when we consolidate the
pipe_context
functions for binding sampler state, this will make the llvmpipe
changes
trivial.
---
src/gallium/drivers/llvmpipe/lp_state_sampler.c | 118
++-
1 files changed, 50 insertions(+), 68 deletions(-)
diff --git a/src/gallium/drivers/llvmpipe/lp_state_sampler.c
b/src/gallium/drivers/llvmpipe/lp_state_sampler.c
index 1451538..cb4846a 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_sampler.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_sampler.c
@@ -66,7 +66,8 @@ llvmpipe_create_sampler_state(struct pipe_context
*pipe,
static void
llvmpipe_bind_sampler_states(struct pipe_context *pipe,
- unsigned num, void **sampler)
+ unsigned shader,
+ unsigned num, void **samplers)
{
struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
unsigned i;
@@ -74,66 +75,57 @@ llvmpipe_bind_sampler_states(struct pipe_context
*pipe,
assert(num= PIPE_MAX_SAMPLERS);
/* Check for no-op */
- if (num == llvmpipe-num_samplers[PIPE_SHADER_FRAGMENT]
- !memcmp(llvmpipe-samplers[PIPE_SHADER_FRAGMENT], sampler,
num * sizeof(void *)))
+ if (num == llvmpipe-num_samplers[shader]
+ !memcmp(llvmpipe-samplers[shader], samplers, num *
sizeof(void *)))
return;
draw_flush(llvmpipe-draw);
for (i = 0; i num; ++i)
- llvmpipe-samplers[PIPE_SHADER_FRAGMENT][i] = sampler[i];
+ llvmpipe-samplers[shader][i] = samplers[i];
for (i = num; i PIPE_MAX_SAMPLERS; ++i)
- llvmpipe-samplers[PIPE_SHADER_FRAGMENT][i] = NULL;
+ llvmpipe-samplers[shader][i] = NULL;
- llvmpipe-num_samplers[PIPE_SHADER_FRAGMENT] = num;
+ llvmpipe-num_samplers[shader] = num;
+
+ if (shader == PIPE_SHADER_VERTEX) {
+ draw_set_samplers(llvmpipe-draw,
+llvmpipe-samplers[PIPE_SHADER_VERTEX],
+llvmpipe-num_samplers[PIPE_SHADER_VERTEX]);
+ }
llvmpipe-dirty |= LP_NEW_SAMPLER;
}
static void
-llvmpipe_bind_vertex_sampler_states(struct pipe_context *pipe,
-unsigned num_samplers,
-void **samplers)
+llvmpipe_bind_fragment_sampler_states(struct pipe_context *pipe,
+ unsigned num, void **samplers)
{
- struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
- unsigned i;
-
- assert(num_samplers= PIPE_MAX_VERTEX_SAMPLERS);
-
- /* Check for no-op */
- if (num_samplers == llvmpipe-num_samplers[PIPE_SHADER_VERTEX]
- !memcmp(llvmpipe-samplers[PIPE_SHADER_VERTEX], samplers,
num_samplers * sizeof(void *)))
- return;
-
- draw_flush(llvmpipe-draw);
-
- for (i = 0; i num_samplers; ++i)
- llvmpipe-samplers[PIPE_SHADER_VERTEX][i] = samplers[i];
- for (i = num_samplers; i PIPE_MAX_VERTEX_SAMPLERS; ++i)
- llvmpipe-samplers[PIPE_SHADER_VERTEX][i] = NULL;
-
- llvmpipe-num_samplers[PIPE_SHADER_VERTEX] = num_samplers;
+ llvmpipe_bind_sampler_states(pipe, PIPE_SHADER_FRAGMENT, num,
samplers);
+}
- draw_set_samplers(llvmpipe-draw,
- llvmpipe-samplers[PIPE_SHADER_VERTEX],
- llvmpipe-num_samplers[PIPE_SHADER_VERTEX]);
- llvmpipe-dirty |= LP_NEW_SAMPLER;
+static void
+llvmpipe_bind_vertex_sampler_states(struct pipe_context *pipe,
+unsigned num, void **samplers)
+{
+ llvmpipe_bind_sampler_states(pipe, PIPE_SHADER_VERTEX, num,
samplers);
}
static void
llvmpipe_bind_geometry_sampler_states(struct pipe_context *pipe,
- unsigned num, void **sampler)
+ unsigned num, void **samplers)
{
- /* XXX: implementation missing */
+ llvmpipe_bind_sampler_states(pipe, PIPE_SHADER_GEOMETRY, num,
samplers);
}
static void
-llvmpipe_set_fragment_sampler_views(struct pipe_context *pipe,
-unsigned num,
-struct pipe_sampler_view
**views)
+llvmpipe_set_sampler_views(struct pipe_context *pipe,
+ unsigned shader,
+ unsigned num,
+ struct pipe_sampler_view **views)
{
struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
uint i;
@@ -141,8 +133,8 @@ llvmpipe_set_fragment_sampler_views(struct
pipe_context *pipe,
assert(num= PIPE_MAX_SAMPLERS);
/* Check for no-op */
- if (num == llvmpipe-num_sampler_views[PIPE_SHADER_FRAGMENT]
- !memcmp(llvmpipe-sampler_views[PIPE_SHADER_FRAGMENT], views,
num * sizeof(struct pipe_sampler_view *)))
+ if (num == llvmpipe-num_sampler_views[shader]
+ !memcmp(llvmpipe-sampler_views[shader], views, num *
sizeof(struct pipe_sampler_view *)))
return;
draw_flush(llvmpipe-draw);
@@
[Mesa-dev] [PATCH 1/2] radeon/winsys: fix winsys VM handling
Move releasing the VM area after closing the bo handle.
Signed-off-by: Christian König deathsim...@vodafone.de
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 2626586..464842c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -319,13 +319,14 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
if (bo-ptr)
os_munmap(bo-ptr, bo-base.size);
+/* Close object. */
+args.handle = bo-handle;
+drmIoctl(bo-rws-fd, DRM_IOCTL_GEM_CLOSE, args);
+
if (mgr-va) {
radeon_bomgr_free_va(mgr, bo-va, bo-va_size);
}
-/* Close object. */
-args.handle = bo-handle;
-drmIoctl(bo-rws-fd, DRM_IOCTL_GEM_CLOSE, args);
pipe_mutex_destroy(bo-map_mutex);
FREE(bo);
}
--
1.7.9.5
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[Mesa-dev] [PATCH 2/2] radeonsi: fix memory leak and/or segfaults
Fix a stupid typo that could lead to memory
leaks and/or segfaults.
Signed-off-by: Christian König deathsim...@vodafone.de
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pm4.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
index 0aad78f..12facaf 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
@@ -119,7 +119,7 @@ void si_pm4_free_state(struct r600_context *rctx,
}
for (int i = 0; i state-nbo; ++i) {
- si_resource_reference(state-bo[idx], NULL);
+ si_resource_reference(state-bo[i], NULL);
}
FREE(state);
}
--
1.7.9.5
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Re: [Mesa-dev] [PATCH 1/2] radeon/winsys: fix winsys VM handling
On Mon, Aug 6, 2012 at 12:14 PM, Christian König
deathsim...@vodafone.de wrote:
Move releasing the VM area after closing the bo handle.
Maybe reference the bugzilla in the commit message?
Signed-off-by: Christian König deathsim...@vodafone.de
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 2626586..464842c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -319,13 +319,14 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
if (bo-ptr)
os_munmap(bo-ptr, bo-base.size);
+/* Close object. */
+args.handle = bo-handle;
+drmIoctl(bo-rws-fd, DRM_IOCTL_GEM_CLOSE, args);
+
if (mgr-va) {
radeon_bomgr_free_va(mgr, bo-va, bo-va_size);
}
-/* Close object. */
-args.handle = bo-handle;
-drmIoctl(bo-rws-fd, DRM_IOCTL_GEM_CLOSE, args);
pipe_mutex_destroy(bo-map_mutex);
FREE(bo);
}
--
1.7.9.5
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[Mesa-dev] [PATCH] Docs: Add OpenGL 4.3 requirements
Add OpenGL 4.3 requirements. Signed-off-by: Jason Wood sand...@hotmail.com --- a/docs/GL3.txt 2012-08-06 10:49:10.185597917 -0600 +++ b/docs/GL3.txt 2012-08-06 10:48:45.809477043 -0600 @@ -130,5 +130,35 @@ GL_ARB_map_buffer_alignment not started +GL 4.3: + +GLSL 4.3 +ARB_arrays_of_arrays not started +ARB_ES3_compatibilitynot started +ARB_clear_buffer_object not started +ARB_compute_shader not started +ARB_copy_image not started +ARB_debug_group not started +ARB_debug_label not started +ARB_debug_output2not started +ARB_debug_output not started +ARB_explicit_uniform_locationnot started +ARB_fragment_layer_viewport not started +ARB_framebuffer_no_attachments not started +ARB_internalformat_query2not started +ARB_invalidate_subdata not started +ARB_multi_draw_indirect not started +ARB_program_interface_query not started +ARB_robust_buffer_access_behaviornot started +ARB_shader_image_sizenot started +ARB_shader_storage_buffer_object not started +ARB_stencil_texturingnot started +ARB_texture_buffer_range not started +ARB_texture_query_levels not started +ARB_texture_storage_multisample not started +ARB_texture_view not started +ARB_vertex_attrib_bindingnot started + + More info about these features and the work involved can be found at http://dri.freedesktop.org/wiki/MissingFunctionality ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Allocate dummy slots for point sprites before computing VUE map.
Kenneth Graunke kenn...@whitecape.org writes: Commit f0cecd43d6b6d moved the VUE map computation to be only once, at VS compile time. However, it did so in slightly the wrong place: it made the one call to brw_vue_compute_map happen right before the allocation of dummy slots for replaced point sprite coordinates, causing a different VUE map to be generated (at least on Ironlake). Fixes a regression in Piglit's point-sprite test on Ironlake. This had been on my list to look at, thanks for getting to it first. Reviewed-by: Eric Anholt e...@anholt.net pgpKf7oSC4HGi.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] i965/vs: Don't clobber sampler message MRFs with subexpressions.
Kenneth Graunke kenn...@whitecape.org writes:
See the preceding commit for a description of the problem.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 60
++
1 file changed, 43 insertions(+), 17 deletions(-)
No observed benefit to this patch, at least in Piglit, but it certainly
is worth doing.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c77dc91..03089d0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+ src_reg lod, dPdy;
+ switch (ir-op) {
+ case ir_txf:
+ case ir_txl:
+ case ir_txs:
+ ir-lod_info.lod-accept(this);
+ lod = this-result;
+ break;
+ case ir_txd:
+ ir-lod_info.grad.dPdx-accept(this);
+ lod = this-result;
+
+ ir-lod_info.grad.dPdy-accept(this);
+ dPdy = this-result;
+ break;
+ case ir_tex:
+ case ir_txb:
+ break;
+ }
-
- ir-lod_info.grad.dPdx-accept(this);
- src_reg dPdx = this-result;
- ir-lod_info.grad.dPdy-accept(this);
- src_reg dPdy = this-result;
+ src_reg dPdx = lod;
Could dPdx get declared and set up above next to dPdy?
Other than that and the commit message note on 2/4,
Reviewed-by: Eric Anholt e...@anholt.net
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Re: [Mesa-dev] [PATCH 2/4] i965/fs: Factor out texcoord setup into a helper function.
Kenneth Graunke kenn...@whitecape.org writes:
With the textureRect support and GL_CLAMP workarounds, it's grown
sufficiently that it deserves its own function. Separating it out
makes the original function much more readable.
This looks good.
While we're refactoring it, tidy up a conditional. Instead of:
if (gen 6 rect)
...
else if (rect)
...
We can do the more readable:
if (rect) {
if (gen 6)
...
else
...
}
I don't see this having actually happened in this commit. Which I'm
fine with, just as long as the commit message and code are consistent :)
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Re: [Mesa-dev] [PATCH] Docs: Add OpenGL 4.3 requirements
On Mon, Aug 6, 2012 at 1:12 PM, Jason Wood sand...@hotmail.com wrote: Add OpenGL 4.3 requirements. Signed-off-by: Jason Wood sand...@hotmail.com --- a/docs/GL3.txt 2012-08-06 10:49:10.185597917 -0600 +++ b/docs/GL3.txt 2012-08-06 10:48:45.809477043 -0600 @@ -130,5 +130,35 @@ GL_ARB_map_buffer_alignment not started +GL 4.3: + +GLSL 4.3 +ARB_arrays_of_arrays not started +ARB_ES3_compatibilitynot started +ARB_clear_buffer_object not started +ARB_compute_shader not started The compute shader extension can take advantage of the compute work that Francisco and Tom have been working on for gallium and OpenCL so that one at least could be considered started, at least for gallium drivers. Alex +ARB_copy_image not started +ARB_debug_group not started +ARB_debug_label not started +ARB_debug_output2not started +ARB_debug_output not started +ARB_explicit_uniform_locationnot started +ARB_fragment_layer_viewport not started +ARB_framebuffer_no_attachments not started +ARB_internalformat_query2not started +ARB_invalidate_subdata not started +ARB_multi_draw_indirect not started +ARB_program_interface_query not started +ARB_robust_buffer_access_behaviornot started +ARB_shader_image_sizenot started +ARB_shader_storage_buffer_object not started +ARB_stencil_texturingnot started +ARB_texture_buffer_range not started +ARB_texture_query_levels not started +ARB_texture_storage_multisample not started +ARB_texture_view not started +ARB_vertex_attrib_bindingnot started + + More info about these features and the work involved can be found at http://dri.freedesktop.org/wiki/MissingFunctionality ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 53179] New: libOSMesa / libdricore not linked well
https://bugs.freedesktop.org/show_bug.cgi?id=53179 Bug #: 53179 Summary: libOSMesa / libdricore not linked well Classification: Unclassified Product: Mesa Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Mesa core AssignedTo: mesa-dev@lists.freedesktop.org ReportedBy: ar...@maven.pl There is bunch of unresolved symbols in libOSMesa.so (git master as of today). Looks like at least -lm -ldl is missing. Unresolved symbols found in: /home/users/arekm/tmp/Mesa-8.1.0-root-arekm/usr/lib64/libOSMesa.so.8.1.0 sincos sqrt floor sinf __fpclassifyf truncf _glapi_get_proc_address dlsym _glapi_get_dispatch_table_size powf sqrtf expf log ceilf sincosf exp2f _glapi_get_context logf floorf _glapi_add_dispatch cosf exp _glapi_check_multithread _glapi_tls_Context _glapi_set_context pow cos log2f dlopen dlclose _glapi_set_dispatch _glapi_tls_Dispatch Same for libdricore.so Unresolved symbols found in: /home/users/arekm/tmp/Mesa-8.1.0-root-arekm/usr/lib64/libdricore8.1.0.so.1.0.0 dlsym _glapi_get_dispatch_table_size _glapi_get_context _glapi_add_dispatch _glapi_tls_Context _glapi_set_context dlopen dlclose _glapi_set_dispatch _glapi_tls_Dispatch -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/16] intel: Add singlesample fields to intel_mipmap_tree
Chad Versace chad.vers...@linux.intel.com writes: Add the following fields: singlesamle_width0 singlesample_height0 singlesample_mt needs_downsample These will all be used by later commits that implement MSAA for window system buffers. I really don't like splitting the commits for creation of fields from their usage. I was pretty convinced that singlesample_width0/height0 wasn't needed (since it should just be in singlesample_mt, right?) until I searched later in the commit series to find the singlesample_tmp flag, which is introduced in the appropriate commit. pgpBkdFIIlDgm.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/16] i965: Add functions up/downsampling on miptrees (v2)
Chad Versace chad.vers...@linux.intel.com writes: These functions do an up or downsample between mt and mt-singlesample_mt. Conceptually, these functions belong in intel_mipmap_tree.c. However, they needs to interact with blorp, which is C++. So I created a new file, brw_blorp_orphans.cpp, for these and other functions that fall into the same category. v2: - Add an upsample function. - Also up/downsample the stencil miptree. - Assert that the miptree is flat. Couldn't we just make a brw_blorp_blit(brw, src_mt, dst_mt, ...) function in the brw_blorp_blit file.cpp, which do_blorp_blit could use, and then we wouldn't need to put this code in a weird file? pgpplVH9qvm1l.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Don't set the saturate bit on gen4 math send instructions.
On 07/28/2012 05:55 PM, Eric Anholt wrote: The saturate bit gets communicated as part of the message descriptor, and setting it in the instruction somehow trashes the results. Fixes piglit general/fog-modes and ext_fog_coord-modes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628 NOTE: This is a candidate for the 8.0 branch. --- src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index dc5f3e1..9658d91 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -237,6 +237,8 @@ fs_visitor::generate_math_gen4(fs_inst *inst, assert(inst-mlen = 1); + brw_set_saturate(p, false); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_math(p, dst, op, Reviewed-by: Kenneth Graunke kenn...@whitecape.org The VS backend is probably broken too. It looks like it's not even setting the message dsecriptor bits. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 07/16] intel: Add function for marking needed downsample
Chad Versace chad.vers...@linux.intel.com writes: Add function intel_renderbuffer_set_needs_downsample. It is a no-op except on multisample winsys buffers shared with DRI2. Squash into next commit and this gets Reviewed-by: Eric Anholt e...@anholt.net pgpCcBp2Gd83A.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 11/16] intel: Support mapping multisample miptrees
Chad Versace chad.vers...@linux.intel.com writes:
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
void
@@ -1513,5 +1606,8 @@ intel_miptree_unmap(struct intel_context *intel,
unsigned int level,
unsigned int slice)
{
- intel_miptree_unmap_singlesample(intel, mt, level, slice);
+ if (mt-num_samples == 0)
Isn't mt-num_samples sometimes 1 for a singlesample mt now?
+ intel_miptree_unmap_singlesample(intel, mt, level, slice);
+ else
+ intel_miptree_unmap_multisample(intel, mt, level, slice);
}
Other than that, downsamples get done in some cases where needs
needs_downsample was false, which is suboptimal. But I think the code
is correct, and this is a fallback path so I don't care too much.
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Re: [Mesa-dev] [PATCH 05/16] i965: Add functions up/downsampling on miptrees (v2)
Chad Versace chad.vers...@linux.intel.com writes:
These functions do an up or downsample between mt and mt-singlesample_mt.
+static void
+intel_miptree_updownsample(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ enum intel_updownsample direction)
+{
+ struct intel_mipmap_tree *src;
+ struct intel_mipmap_tree *dst;
+
+ /* Only flat, renderbuffer-like miptrees are supported. */
+ assert(mt-target == GL_TEXTURE_2D);
+ assert(mt-first_level == 0);
+ assert(mt-last_level == 0);
+
+ switch (direction) {
+ case INTEL_DOWNSAMPLE: {
+ if (!mt-need_downsample)
+ return;
+ src = mt;
+ dst = mt-singlesample_mt;
+ break;
+ }
+ case INTEL_UPSAMPLE: {
+ assert(!mt-need_downsample);
+ src = mt-singlesample_mt;
+ dst = mt;
+ break;
+ }
Also, I think the direction-dependent code should be moved into the two
callers.
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Re: [Mesa-dev] [PATCH 12/16] intel: Downsample on DRI2 flush
Chad Versace chad.vers...@linux.intel.com writes: CC: Eric Anholt e...@anholt.net Reviewed-by: Paul Berry stereotype...@gmail.com Signed-off-by: Chad Versace chad.vers...@linux.intel.com Reviewed-by: Eric Anholt e...@anholt.net pgp9FB4QzN2S0.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 14/16] dri: Simplify use of driConcatConfigs
Chad Versace chad.vers...@linux.intel.com writes: If either argument to driConcatConfigs(a, b) is null or the empty list, then simply return the other argument as the resultant list. All callers were accomplishing that same behavior anyway. And each caller accopmplished it with the same pattern. So this patch moves that external pattern into the function. An obvious cleanup. Reviewed-by: Eric Anholt e...@anholt.net pgproNAHGupnr.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [REVIEW-8.0] Cherry-pick bin/shortlog_mesa.sh script
To make Ian's life easier, please cherry-pick these two commits: mesa: added Ian's shortlog_mesa.sh script in bin/ 51c9c67a2ff2ec5963680fe5733691a6a991eab5 mesa: fix html in shortlog_mesa.sh script c1dcf9665c770d25ba8cbe827f4e3e69349d2665 Andreas. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] docs/helpwanted: add r600g and i915g todo lists
--- docs/helpwanted.html |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/docs/helpwanted.html b/docs/helpwanted.html index 6d6058e..8aa1b92 100644 --- a/docs/helpwanted.html +++ b/docs/helpwanted.html @@ -56,8 +56,12 @@ You can find some further To-do lists here: target=_parentbLLVMpipe - todo/b/a/li lia href=http://dri.freedesktop.org/wiki/MissingFunctionality; target=_parentbMissingFunctionality/b/a/li + lia href=http://dri.freedesktop.org/wiki/R600ToDo; +target=_parentbR600ToDo/b/a/li lia href=http://dri.freedesktop.org/wiki/R300ToDo; target=_parentbR300ToDo/b/a/li + lia href=http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/i915/TODO; +target=_parentbi915g TODO/b/a/li /ul p -- 1.7.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] docs: update piglit url
--- docs/helpwanted.html |2 +- docs/shading.html|2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/helpwanted.html b/docs/helpwanted.html index 8aa1b92..e452689 100644 --- a/docs/helpwanted.html +++ b/docs/helpwanted.html @@ -37,7 +37,7 @@ deprecated starting in Mesa 8.0.br They have to be ported to DRI2 to be accepted in mesa master again. li bContribute more tests to -a href=http://people.freedesktop.org/~nh/piglit/; target=_parentPiglit/a./b +a href=http://piglit.freedesktop.org/; target=_parentPiglit/a./b li bAutomatic testing. /b diff --git a/docs/shading.html b/docs/shading.html index a9b7cfc..17cf35c 100644 --- a/docs/shading.html +++ b/docs/shading.html @@ -243,7 +243,7 @@ regressions. /p p -The a href=http://people.freedesktop.org/~nh/piglit/; target=_parentPiglit/a project +The a href=http://piglit.freedesktop.org/; target=_parentPiglit/a project has many GLSL tests and the a href=http://glean.sf.net; target=_parentGlean/a glsl1 test tests GLSL features. -- 1.7.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/22] glsl: Add a lowering pass to turn complicated UBO references to vector loads.
On 07/31/2012 03:01 PM, Eric Anholt wrote:
---
src/glsl/Makefile.sources|1 +
src/glsl/ir_optimization.h |1 +
src/glsl/lower_ubo_reference.cpp | 325
++
3 files changed, 327 insertions(+)
create mode 100644 src/glsl/lower_ubo_reference.cpp
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index f2743f7..765f06a 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -66,6 +66,7 @@ LIBGLSL_CXX_FILES = \
$(GLSL_SRCDIR)/lower_vec_index_to_swizzle.cpp \
$(GLSL_SRCDIR)/lower_vector.cpp \
$(GLSL_SRCDIR)/lower_output_reads.cpp \
+ $(GLSL_SRCDIR)/lower_ubo_reference.cpp \
$(GLSL_SRCDIR)/opt_algebraic.cpp \
$(GLSL_SRCDIR)/opt_array_splitting.cpp \
$(GLSL_SRCDIR)/opt_constant_folding.cpp \
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index c435d77..2220d51 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -74,6 +74,7 @@ bool lower_variable_index_to_cond_assign(exec_list
*instructions,
bool lower_quadop_vector(exec_list *instructions, bool dont_lower_swz);
bool lower_clip_distance(exec_list *instructions);
void lower_output_reads(exec_list *instructions);
+void lower_ubo_reference(struct gl_shader *shader, exec_list *instructions);
bool optimize_redundant_jumps(exec_list *instructions);
bool optimize_split_arrays(exec_list *instructions, bool linked);
diff --git a/src/glsl/lower_ubo_reference.cpp
b/src/glsl/lower_ubo_reference.cpp
new file mode 100644
index 000..6a8d75d
--- /dev/null
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -0,0 +1,325 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file lower_ubo_reference.cpp
+ * IR lower pass to remove noise opcodes.
+ */
+
+#include ir.h
+#include ir_builder.h
+#include ir_rvalue_visitor.h
+#include main/macros.h
+
+using namespace ir_builder;
+
+namespace {
+class lower_ubo_reference_visitor : public ir_rvalue_enter_visitor {
+public:
+ lower_ubo_reference_visitor(struct gl_shader *shader)
+ : shader(shader)
+ {
+ }
+
+ void handle_rvalue(ir_rvalue **rvalue);
+ void emit_ubo_loads(ir_dereference *deref, ir_variable *offset);
+ ir_expression *ubo_load(const struct glsl_type *type,
+ir_rvalue *offset);
+
+ void *mem_ctx;
+ struct gl_shader *shader;
+ struct gl_uniform_buffer_variable *ubo_var;
+ unsigned uniform_block;
+ bool progress;
+};
+
+static inline unsigned int
+align(unsigned int a, unsigned int align)
+{
+ return (a + align - 1) / align * align;
+}
+
+void
+lower_ubo_reference_visitor::handle_rvalue(ir_rvalue **rvalue)
+{
+ if (!*rvalue)
+ return;
+
+ ir_dereference *deref = (*rvalue)-as_dereference();
+ if (!deref)
+ return;
+
+ ir_variable *var = deref-variable_referenced();
+ if (!var || var-uniform_block == -1)
+ return;
+
+ mem_ctx = ralloc_parent(*rvalue);
+ uniform_block = var-uniform_block;
+ struct gl_uniform_block *block = shader-UniformBlocks[uniform_block];
+ this-ubo_var = block-Uniforms[var-location];
+ ir_rvalue *offset = new(mem_ctx) ir_constant(0u);
+ unsigned const_offset = 0;
+ bool row_major = ubo_var-RowMajor;
Could you put a comment here describing what this large block of code is
intending to do? Something like:
/* Calculate the offset to the start of the dereference. */
+ while (deref) {
+ switch (deref-ir_type) {
+ case ir_type_dereference_variable: {
+ const_offset += ubo_var-Offset;
+ deref = NULL;
+ break;
+ }
+
+ case ir_type_dereference_array: {
+ ir_dereference_array *deref_array = (ir_dereference_array *)deref;
+ unsigned array_stride;
+ if
[Mesa-dev] [PATCH v2] docs: Add OpenGL 4.3 requirements
Add OpenGL 4.3 requirements. v2: Note that GLSL 4.3 has not been started, and that ARB_compute_shader has been started in Gallium drivers. Feel free to commit this as I do not have access. Signed-off-by: Jason Wood sand...@hotmail.com --- a/docs/GL3.txt 2012-08-06 10:49:10.185597917 -0600 +++ b/docs/GL3.txt 2012-08-06 10:48:45.809477043 -0600 @@ -130,5 +130,35 @@ GL_ARB_map_buffer_alignment not started +GL 4.3: + +GLSL 4.3 not started +ARB_arrays_of_arrays not started +ARB_ES3_compatibilitynot started +ARB_clear_buffer_object not started +ARB_compute_shader started (gallium) +ARB_copy_image not started +ARB_debug_group not started +ARB_debug_label not started +ARB_debug_output2not started +ARB_debug_output not started +ARB_explicit_uniform_locationnot started +ARB_fragment_layer_viewport not started +ARB_framebuffer_no_attachments not started +ARB_internalformat_query2not started +ARB_invalidate_subdata not started +ARB_multi_draw_indirect not started +ARB_program_interface_query not started +ARB_robust_buffer_access_behaviornot started +ARB_shader_image_sizenot started +ARB_shader_storage_buffer_object not started +ARB_stencil_texturingnot started +ARB_texture_buffer_range not started +ARB_texture_query_levels not started +ARB_texture_storage_multisample not started +ARB_texture_view not started +ARB_vertex_attrib_bindingnot started + + More info about these features and the work involved can be found at http://dri.freedesktop.org/wiki/MissingFunctionality ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 09/22] glsl: Fix calculation of std140 offset alignment for mat2s.
On 07/31/2012 03:01 PM, Eric Anholt wrote:
We were getting the base offset of a vec2, not of a vec2[2] like the quoted
spec text says we should.
---
src/glsl/glsl_types.cpp | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 3d78660..8e7ae42 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -694,14 +694,19 @@ glsl_type::std140_base_alignment(bool row_major) const
* row vectors with C components each, according to rule (4).
*/
if (this-is_matrix()) {
- const struct glsl_type *vec_type;
+ const struct glsl_type *vec_type, *array_type;
+ int c = this-matrix_columns;
+ int r = this-vector_elements;
+
if (row_major) {
- vec_type = get_instance(GLSL_TYPE_FLOAT, this-vector_elements, 1);
+ vec_type = get_instance(GLSL_TYPE_FLOAT, r, 1);
+ array_type = glsl_type::get_array_instance(vec_type, c);
} else {
- vec_type = get_instance(GLSL_TYPE_FLOAT, this-matrix_columns, 1);
+ vec_type = get_instance(GLSL_TYPE_FLOAT, c, 1);
+ array_type = glsl_type::get_array_instance(vec_type, r);
}
Your row major and column major cases are backwards. It turns out to be
the same since std140_base_alignment of any array type is the same.
Please reverse the then/else cases. Then it's:
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
- return vec_type-std140_base_alignment(false);
+ return array_type-std140_base_alignment(false);
}
/* (9) If the member is a structure, the base alignment of the
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[Mesa-dev] [PATCH] mesa: In conditional rendering fallback, check the query status.
Otherwise, conditional rendering always takes the fallthrough render it anyway case unless the application had itself done a check or wait on the query. Fixes intel oglconform's conditional_render advanced.nofbo.readpixels. --- src/mesa/main/condrender.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/main/condrender.c b/src/mesa/main/condrender.c index 57f3715..bfd2b08 100644 --- a/src/mesa/main/condrender.c +++ b/src/mesa/main/condrender.c @@ -139,6 +139,8 @@ _mesa_check_conditional_render(struct gl_context *ctx) case GL_QUERY_BY_REGION_NO_WAIT: /* fall-through */ case GL_QUERY_NO_WAIT: + if (!q-Ready) + ctx-Driver.CheckQuery(ctx, q); return q-Ready ? (q-Result 0) : GL_TRUE; default: _mesa_problem(ctx, Bad cond render mode %s in -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: In conditional rendering fallback, check the query status.
On 08/06/2012 01:52 PM, Eric Anholt wrote: Otherwise, conditional rendering always takes the fallthrough render it anyway case unless the application had itself done a check or wait on the query. Fixes intel oglconform's conditional_render advanced.nofbo.readpixels. --- src/mesa/main/condrender.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/main/condrender.c b/src/mesa/main/condrender.c index 57f3715..bfd2b08 100644 --- a/src/mesa/main/condrender.c +++ b/src/mesa/main/condrender.c @@ -139,6 +139,8 @@ _mesa_check_conditional_render(struct gl_context *ctx) case GL_QUERY_BY_REGION_NO_WAIT: /* fall-through */ case GL_QUERY_NO_WAIT: + if (!q-Ready) + ctx-Driver.CheckQuery(ctx, q); return q-Ready ? (q-Result 0) : GL_TRUE; default: _mesa_problem(ctx, Bad cond render mode %s in Reviewed-by: Brian Paul bri...@vmware.com Candidate for the 8.0 branch? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] down to 1 test page failing in WebGL 1.0.1 test on Radeon driver
On Mon, Aug 6, 2012 at 12:43 AM, Benoit Jacob bja...@mozilla.com wrote: Hi, Just so you know: the WebGL 1.0.1 tests are now passing on 2 drivers on Linux: the Intel Mesa driver, and the NVIDIA driver. Technically that's enough for us to claim conformance (we need to pass with 2 drivers on each OS we support). But I'd really like to include the Radeon driver in the list of driver we can claim to fully pass conformance tests on. As of Ubuntu 12.04 64bit / Gallium 0.4 on AMD RV710 / Mesa 8.0.2, I have this single test page failing: https://www.khronos.org/registry/webgl/conformance-suites/1.0.1/conformance/textures/texture-mips.html Does it still fail with mesa from git (soon to be 8.1)? I think the tiling rework may have fixed this, but is too invasive to backport to the 8.x branch. Alex ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] down to 1 test page failing in WebGL 1.0.1 test on Radeon driver
On Mon, Aug 6, 2012 at 5:14 PM, Alex Deucher alexdeuc...@gmail.com wrote: On Mon, Aug 6, 2012 at 12:43 AM, Benoit Jacob bja...@mozilla.com wrote: Hi, Just so you know: the WebGL 1.0.1 tests are now passing on 2 drivers on Linux: the Intel Mesa driver, and the NVIDIA driver. Technically that's enough for us to claim conformance (we need to pass with 2 drivers on each OS we support). But I'd really like to include the Radeon driver in the list of driver we can claim to fully pass conformance tests on. As of Ubuntu 12.04 64bit / Gallium 0.4 on AMD RV710 / Mesa 8.0.2, I have this single test page failing: https://www.khronos.org/registry/webgl/conformance-suites/1.0.1/conformance/textures/texture-mips.html Does it still fail with mesa from git (soon to be 8.1)? I think the tiling rework may have fixed this, but is too invasive to backport to the 8.x branch. 8.0 branch that is. Alex ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 19/22] i965/vs: Communicate the pull constant block read parameters through src_regs.
On 07/31/2012 03:01 PM, Eric Anholt wrote:
Similar to the previous commit for the fragment shader.
---
src/mesa/drivers/dri/i965/brw_vec4.h |3 ++-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 19 ---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |5 +++--
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 920d703..deac55d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -476,7 +476,8 @@ public:
struct brw_reg index);
void generate_pull_constant_load(vec4_instruction *inst,
struct brw_reg dst,
- struct brw_reg index);
+ struct brw_reg index,
+ struct brw_reg offset);
Commit message says through src_regs. These are brw_regs.
Other than that, this looks fine.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
One tiny comment below.
};
} /* namespace brw */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 9df7b11..7658bb8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -645,15 +645,20 @@ vec4_visitor::generate_scratch_write(vec4_instruction
*inst,
void
vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
struct brw_reg dst,
- struct brw_reg index)
+ struct brw_reg index,
+ struct brw_reg offset)
{
+ assert(index.file == BRW_IMMEDIATE_VALUE
+ index.type == BRW_REGISTER_TYPE_UD);
+ uint32_t surf_index = index.dw1.ud;
+
if (intel-gen == 7) {
- gen6_resolve_implied_move(p, index, inst-base_mrf);
+ gen6_resolve_implied_move(p, offset, inst-base_mrf);
brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, dst);
- brw_set_src0(p, insn, index);
+ brw_set_src0(p, insn, offset);
brw_set_sampler_message(p, insn,
- SURF_INDEX_VERT_CONST_BUFFER,
+ surf_index,
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1, /* rlen */
@@ -669,7 +674,7 @@
vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
gen6_resolve_implied_move(p, header, inst-base_mrf);
brw_MOV(p, retype(brw_message_reg(inst-base_mrf + 1),
BRW_REGISTER_TYPE_D),
-index);
+offset);
uint32_t msg_type;
@@ -689,7 +694,7 @@
vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
if (intel-gen 6)
send-header.destreg__conditionalmod = inst-base_mrf;
brw_set_dp_read_message(p, send,
-SURF_INDEX_VERT_CONST_BUFFER,
+surf_index,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
msg_type,
BRW_DATAPORT_READ_TARGET_DATA_CACHE,
@@ -753,7 +758,7 @@ vec4_visitor::generate_vs_instruction(vec4_instruction
*instruction,
break;
case VS_OPCODE_PULL_CONSTANT_LOAD:
- generate_pull_constant_load(inst, dst, src[0]);
+ generate_pull_constant_load(inst, dst, src[0], src[1]);
break;
default:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index d6a786f..33078a0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2484,11 +2484,12 @@
vec4_visitor::emit_pull_constant_load(vec4_instruction *inst,
int base_offset)
{
int reg_offset = base_offset + orig_src.reg_offset;
- src_reg index = get_pull_constant_offset(inst, orig_src.reladdr,
reg_offset);
+ src_reg index = src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER);
If you want, in C++ you can constructor-style casts:
src_reg index = src_reg(unsigned(SURF_INDEX_VERT_CONST_BUFFER));
Makes the parenthesis a little nicer, IMHO. But it's purely preference.
+ src_reg offset = get_pull_constant_offset(inst, orig_src.reladdr,
reg_offset);
vec4_instruction *load;
load = new(mem_ctx) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD,
- temp, index);
+ temp, index, offset);
load-base_mrf = 14;
load-mlen = 1;
emit_before(inst, load);
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Re: [Mesa-dev] Last UBO patchbomb!
On 07/31/2012 03:01 PM, Eric Anholt wrote: I've tested it with my piglit series and with Intel's oglconform. My piglit series complains about negative-bindbuffer-buffer's expectations being violated by patch 6, but I think that testcase wants to be replced by one that is aware of gl =3.1 versus =3.0. Intel's oglconform complains only about one testcase that's transform feedbacking into a UBO and failing, so probably a little driver bug I hope. Other than that, I've got a few testing TODOs, but I think this is ready to land and unblock GL 3.1. Except for patch 5, this series gets a: Reviewed-by: Kenneth Graunke kenn...@whitecape.org I would like to review v2 of patch 5. Nice work! I do like the UBO load lowering pass. It encapsulates all the ugly offset computation in one place and makes the backend code so much simpler. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/16] i965: Add functions up/downsampling on miptrees (v2)
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/06/2012 11:10 AM, Eric Anholt wrote: Chad Versace chad.vers...@linux.intel.com writes: These functions do an up or downsample between mt and mt-singlesample_mt. Conceptually, these functions belong in intel_mipmap_tree.c. However, they needs to interact with blorp, which is C++. So I created a new file, brw_blorp_orphans.cpp, for these and other functions that fall into the same category. v2: - Add an upsample function. - Also up/downsample the stencil miptree. - Assert that the miptree is flat. Couldn't we just make a brw_blorp_blit(brw, src_mt, dst_mt, ...) function in the brw_blorp_blit file.cpp, which do_blorp_blit could use, and then we wouldn't need to put this code in a weird file? Sure, that's sensible. Then intel_miptree_downsample can call brw_blop_blit, and we can move the its definition to intel_mipmap_tree.c. I see two places where it is appropriate to declare brw_blorp_bit(): 1. In a new header, brw_blorp_blit.h. 2. In brw_blorp.h. This is currently a C++ header. So, to make it cross C/C++ header usable by intel_mipmap_tree.c, the C++ parts will need to guarded by an #ifdef. Do you have a preference? -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.19 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJQIDqXAAoJEAIvNt057x8i8a4P/0RJ5VuMuWO+aLiC9bfnbMHP a3PxRYz0junUOrB4d+MjDVFwYKB08Oh37MHwNbOFmNrj1KR5LhBDLlJN5M4r71Dv hG3LbWmiqiJQMg3FES3Bm5Uwzv/MRwp2lA6hOIagsrfkX33AmNqHfkqPGikkzR7A 7vbZy7WFOCd6VDmn90bEXiKyuLOf/LhQOARhKw+VxffrZYBXQrXhwjycFTvH0i7o dm7TaB1sSym8WoZeux7EnHZqAJp094zBa8TDpGcKbei9ZhmYq/KdcuMvnuPndFgQ XPPRxEge2uxcTo6fpav/u0ttVaOV/EoVG0Lbotn5nto5MN1Hcq/lYdUVWnVHdG7H anWanGyg3ZayovxW39fP5fIsQD9+O66pnBjxjtZ/cjqA5VP24mY1q/brUa4sgnOQ fwHgIXP4Wf/Z0mQQ5KQqImYgEV31ygwtrdC+KcqeNfBJNN6cg90lpQjNnTZct0Of QTkKsTROVyV2jMYA8RXvHm8nhDlGTboHyrYmK71vL4TNUDKSNkGVFYmRY9C3Ueg6 52v132SxnA1BT22cHV7hEtb7mlaiqD4rZHRPZnZh1RubTtVsSgwsD0bxHzzUjH4c pd1fveW6hH1NyVAa/f09MSHUCN22+MnH7wAIX95Ojndm8oCGZgYRhC22ZJqQq5AJ GpxaUhlGhb29ltfN+eqF =h2TJ -END PGP SIGNATURE- ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH mesa] i965: add more Haswell PCI IDs
From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- include/pci_ids/i965_pci_ids.h | 33 ++- src/mesa/drivers/dri/intel/intel_chipset.h | 67 -- src/mesa/drivers/dri/intel/intel_context.c | 35 +++- 3 files changed, 130 insertions(+), 5 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index e38f8d2..09dca5b 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -28,6 +28,37 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) +CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) -CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2) +CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) +CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) +CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) +CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) +CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) +CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) +CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) +CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) +CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) +CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) +CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) +CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) +CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) +CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) +CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) +CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) +CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) +CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) +CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) +CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index c1d904e..9c00ba8 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -89,9 +89,40 @@ #define PCI_CHIP_HASWELL_GT10x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT20x0412 +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */ +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_SDV_GT10x0C02 /* Desktop */ +#define PCI_CHIP_HASWELL_SDV_GT20x0C12 +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_ULT_GT10x0A02 /* Desktop */ +#define PCI_CHIP_HASWELL_ULT_GT20x0A12 +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_CRW_GT10x0D12 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT20x0D22 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -163,10 +194,40 @@ IS_HASWELL(devid)) #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ -devid == PCI_CHIP_HASWELL_M_GT1) +devid == PCI_CHIP_HASWELL_M_GT1 || \ +devid == PCI_CHIP_HASWELL_S_GT1 ||
[Mesa-dev] R600 VDPAU 422 regression since r600g: make sure copying of all texture formats is accelerated
Kernel is dcn card is rv790 - vdpau csc/scale regressed. This only shows with 422 colour so most things work. commit 7c371f46958910dd2ca9487c89af1b72bbfdada9 Author: Marek Olšák mar...@gmail.com Date: Sat Jul 28 00:38:42 2012 +0200 r600g: make sure copying of all texture formats is accelerated [drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream ! radeon :01:00.0: texture bo too small ((704 576) (1 1) 0 26 0 - 1622016 have 884736) radeon :01:00.0: alignments 384 1 1 1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Don't set the saturate bit on gen4 math send instructions.
Kenneth Graunke kenn...@whitecape.org writes: On 07/28/2012 05:55 PM, Eric Anholt wrote: The saturate bit gets communicated as part of the message descriptor, and setting it in the instruction somehow trashes the results. Fixes piglit general/fog-modes and ext_fog_coord-modes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628 NOTE: This is a candidate for the 8.0 branch. --- src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index dc5f3e1..9658d91 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -237,6 +237,8 @@ fs_visitor::generate_math_gen4(fs_inst *inst, assert(inst-mlen = 1); + brw_set_saturate(p, false); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_math(p, dst, op, Reviewed-by: Kenneth Graunke kenn...@whitecape.org The VS backend is probably broken too. It looks like it's not even setting the message dsecriptor bits. You're right. You're so right I'm replacing this patch with one that's +6, -44 by removing the saturate arg to brw_maths, but now I need to do another piglit run on gen4 :( pgploSal0n2AM.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glx/dri: Initialize reset to __DRI_CTX_RESET_NO_NOTIFICATION.
If the application has requested reset notification, then dri2_convert_glx_attribs will initialize this to the correct value. Otherwise, it's supposed to initialize this to NO_NOTIFICATION, but doesn't when num_attribs == 0. Fixes a regression since a8724d85f8cb2f0fb73b9c6c1f268f9084c6d473 where trying to apitrace Unigine Heaven would result in: dri_util.c:221: dri2CreateContextAttribs: Assertion `!Should not get here.' failed. Cc: Ian Romanick i...@freedesktop.org Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/glx/dri2_glx.c | 2 +- src/glx/drisw_glx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c index 79237c3..4e8b351 100644 --- a/src/glx/dri2_glx.c +++ b/src/glx/dri2_glx.c @@ -241,7 +241,7 @@ dri2_create_context_attribs(struct glx_screen *base, uint32_t major_ver = 2; uint32_t flags = 0; unsigned api; - int reset; + int reset = __DRI_CTX_RESET_NO_NOTIFICATION; uint32_t ctx_attribs[2 * 5]; unsigned num_ctx_attribs = 0; diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c index 519786e..462be7d 100644 --- a/src/glx/drisw_glx.c +++ b/src/glx/drisw_glx.c @@ -433,7 +433,7 @@ drisw_create_context_attribs(struct glx_screen *base, uint32_t major_ver = 0; uint32_t flags = 0; unsigned api; - int reset; + int reset = __DRI_CTX_RESET_NO_NOTIFICATION; uint32_t ctx_attribs[2 * 4]; unsigned num_ctx_attribs = 0; -- 1.7.11.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Intel-gfx] [PATCH mesa] i965: add more Haswell PCI IDs
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com On Mon, Aug 6, 2012 at 6:50 PM, Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- include/pci_ids/i965_pci_ids.h | 33 ++- src/mesa/drivers/dri/intel/intel_chipset.h | 67 -- src/mesa/drivers/dri/intel/intel_context.c | 35 +++- 3 files changed, 130 insertions(+), 5 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index e38f8d2..09dca5b 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -28,6 +28,37 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) +CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) -CHIPSET(0x0A16, HASWELL_M_ULT_GT2, hsw_gt2) +CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) +CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) +CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) +CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) +CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) +CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) +CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) +CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) +CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) +CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) +CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) +CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) +CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) +CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) +CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) +CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) +CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) +CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) +CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) +CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index c1d904e..9c00ba8 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -89,9 +89,40 @@ #define PCI_CHIP_HASWELL_GT10x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT20x0412 +#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ #define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */ +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_SDV_GT10x0C02 /* Desktop */ +#define PCI_CHIP_HASWELL_SDV_GT20x0C12 +#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_ULT_GT10x0A02 /* Desktop */ +#define PCI_CHIP_HASWELL_ULT_GT20x0A12 +#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_CRW_GT10x0D12 /* Desktop */ +#define PCI_CHIP_HASWELL_CRW_GT20x0D22 +#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -163,10 +194,40 @@ IS_HASWELL(devid)) #define IS_HSW_GT1(devid) (devid ==
Re: [Mesa-dev] [PATCH 1/2] docs/helpwanted: add r600g and i915g todo lists
On 08/06/2012 01:38 PM, Andreas Boll wrote: --- docs/helpwanted.html |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/docs/helpwanted.html b/docs/helpwanted.html index 6d6058e..8aa1b92 100644 --- a/docs/helpwanted.html +++ b/docs/helpwanted.html @@ -56,8 +56,12 @@ You can find some further To-do lists here: target=_parentbLLVMpipe - todo/b/a/li lia href=http://dri.freedesktop.org/wiki/MissingFunctionality; target=_parentbMissingFunctionality/b/a/li +lia href=http://dri.freedesktop.org/wiki/R600ToDo; +target=_parentbR600ToDo/b/a/li lia href=http://dri.freedesktop.org/wiki/R300ToDo; target=_parentbR300ToDo/b/a/li +lia href=http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/i915/TODO; +target=_parentbi915g TODO/b/a/li /ul p Thanks. I'm pushing these two doc patches. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] docs: Add OpenGL 4.3 requirements
On 08/06/2012 01:47 PM, Jason Wood wrote: Add OpenGL 4.3 requirements. v2: Note that GLSL 4.3 has not been started, and that ARB_compute_shader has been started in Gallium drivers. Feel free to commit this as I do not have access. Signed-off-by: Jason Woodsand...@hotmail.com --- a/docs/GL3.txt 2012-08-06 10:49:10.185597917 -0600 +++ b/docs/GL3.txt 2012-08-06 10:48:45.809477043 -0600 @@ -130,5 +130,35 @@ GL_ARB_map_buffer_alignment not started +GL 4.3: + +GLSL 4.3 not started +ARB_arrays_of_arrays not started +ARB_ES3_compatibilitynot started +ARB_clear_buffer_object not started +ARB_compute_shader started (gallium) +ARB_copy_image not started +ARB_debug_group not started +ARB_debug_label not started +ARB_debug_output2not started +ARB_debug_output not started +ARB_explicit_uniform_locationnot started +ARB_fragment_layer_viewport not started +ARB_framebuffer_no_attachments not started +ARB_internalformat_query2not started +ARB_invalidate_subdata not started +ARB_multi_draw_indirect not started +ARB_program_interface_query not started +ARB_robust_buffer_access_behaviornot started +ARB_shader_image_sizenot started +ARB_shader_storage_buffer_object not started +ARB_stencil_texturingnot started +ARB_texture_buffer_range not started +ARB_texture_query_levels not started +ARB_texture_storage_multisample not started +ARB_texture_view not started +ARB_vertex_attrib_bindingnot started + + More info about these features and the work involved can be found at http://dri.freedesktop.org/wiki/MissingFunctionality Thanks. I'll push this soon. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] docs: Add OpenGL 4.3 requirements
On 08/06/2012 12:47 PM, Jason Wood wrote: Add OpenGL 4.3 requirements. v2: Note that GLSL 4.3 has not been started, and that ARB_compute_shader has been started in Gallium drivers. Feel free to commit this as I do not have access. Signed-off-by: Jason Wood sand...@hotmail.com --- a/docs/GL3.txt 2012-08-06 10:49:10.185597917 -0600 +++ b/docs/GL3.txt 2012-08-06 10:48:45.809477043 -0600 @@ -130,5 +130,35 @@ GL_ARB_map_buffer_alignment not started +GL 4.3: + +GLSL 4.3 not started +ARB_arrays_of_arrays not started +ARB_ES3_compatibilitynot started +ARB_clear_buffer_object not started +ARB_compute_shader started (gallium) +ARB_copy_image not started +ARB_debug_group not started +ARB_debug_label not started +ARB_debug_output2not started +ARB_debug_output not started This extension is already supported. +ARB_explicit_uniform_locationnot started +ARB_fragment_layer_viewport not started +ARB_framebuffer_no_attachments not started +ARB_internalformat_query2not started +ARB_invalidate_subdata not started +ARB_multi_draw_indirect not started +ARB_program_interface_query not started +ARB_robust_buffer_access_behaviornot started +ARB_shader_image_sizenot started +ARB_shader_storage_buffer_object not started +ARB_stencil_texturingnot started +ARB_texture_buffer_range not started +ARB_texture_query_levels not started +ARB_texture_storage_multisample not started +ARB_texture_view not started +ARB_vertex_attrib_bindingnot started + + More info about these features and the work involved can be found at http://dri.freedesktop.org/wiki/MissingFunctionality ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glx/dri: Initialize reset to __DRI_CTX_RESET_NO_NOTIFICATION.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com On Mon, Aug 6, 2012 at 3:12 PM, Kenneth Graunke kenn...@whitecape.org wrote: If the application has requested reset notification, then dri2_convert_glx_attribs will initialize this to the correct value. Otherwise, it's supposed to initialize this to NO_NOTIFICATION, but doesn't when num_attribs == 0. Fixes a regression since a8724d85f8cb2f0fb73b9c6c1f268f9084c6d473 where trying to apitrace Unigine Heaven would result in: dri_util.c:221: dri2CreateContextAttribs: Assertion `!Should not get here.' failed. Cc: Ian Romanick i...@freedesktop.org Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/glx/dri2_glx.c | 2 +- src/glx/drisw_glx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c index 79237c3..4e8b351 100644 --- a/src/glx/dri2_glx.c +++ b/src/glx/dri2_glx.c @@ -241,7 +241,7 @@ dri2_create_context_attribs(struct glx_screen *base, uint32_t major_ver = 2; uint32_t flags = 0; unsigned api; - int reset; + int reset = __DRI_CTX_RESET_NO_NOTIFICATION; uint32_t ctx_attribs[2 * 5]; unsigned num_ctx_attribs = 0; diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c index 519786e..462be7d 100644 --- a/src/glx/drisw_glx.c +++ b/src/glx/drisw_glx.c @@ -433,7 +433,7 @@ drisw_create_context_attribs(struct glx_screen *base, uint32_t major_ver = 0; uint32_t flags = 0; unsigned api; - int reset; + int reset = __DRI_CTX_RESET_NO_NOTIFICATION; uint32_t ctx_attribs[2 * 4]; unsigned num_ctx_attribs = 0; -- 1.7.11.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH mesa] i965: add more Haswell PCI IDs
On 08/06/2012 02:50 PM, Paulo Zanoni wrote: From: Paulo Zanoni paulo.r.zan...@intel.com Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com Reviewed-by: Kenneth Graunke kenn...@whitecape.org Do you have push access? If not, I can commit this for you. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glx/dri: Initialize reset to __DRI_CTX_RESET_NO_NOTIFICATION.
I noticed that we have a bit of inconsistency in how we handle context
defaults. In some cases, we initialize variables with default values in
dri{2,sw}_create_context_attribs. In other cases, we rely on
dri2_convert_glx_attribs to do that for us.
For example, in dri2_convert_glx_attribs:
uint32_t minor_ver = 1;
uint32_t major_ver = 2;
uint32_t flags = 0;
unsigned api;
int reset;
we default the version to 2.1. Whereas in dri_convert_glx_attribs we have:
if (num_attribs == 0) {
*api = __DRI_API_OPENGL;
return true;
}
...
*major_ver = 1;
*minor_ver = 0;
*reset = __DRI_CTX_RESET_NO_NOTIFICATION;
So if they try to create a context with _no_ attributes, we pick 2.1.
If they specify _some_ attributes, but not version attributes, we hit
this code and pick 1.0. drisw_create_context_attribs also defaults to 1.0.
My feeling is that we should either make dri2_convert_glx_attribs not
short-circuit on num_attribs == 0, so it fully initializes all the
defaults, or we should make both the callers fully specify defaults and
remove the block that makes it set them. Either would work, but it'd be
nice to pick one.
Preferences?
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[Mesa-dev] [PATCH 01/15] intel: Refactor quantize_num_samples (v1)
Rename quantize_num_samples to intel_quantize_num_samples and change the
first param from struct intel_context* to struct intel_screen*. The
function will later be used by intelCreateBuffer, which is not bound to
any context but is bound to a screen.
v2: Keep the function in intel_fbo.c, per Anholt.
CC: Eric Anholt e...@anholt.net
Reviewed-by: Paul Berry stereotype...@gmail.com (v1)
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 7 ---
src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 613287f..80af192 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -182,8 +182,8 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
/**
* Round up the requested multisample count to the next supported sample size.
*/
-static unsigned
-quantize_num_samples(struct intel_context *intel, unsigned num_samples)
+unsigned
+intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples)
{
switch (intel-gen) {
case 6:
@@ -226,8 +226,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
GLuint width, GLuint height)
{
struct intel_context *intel = intel_context(ctx);
+ struct intel_screen *screen = intel-intelScreen;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- rb-NumSamples = quantize_num_samples(intel, rb-NumSamples);
+ rb-NumSamples = intel_quantize_num_samples(screen, rb-NumSamples);
switch (internalFormat) {
default:
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index 02bda1e..b922dca 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -200,6 +200,9 @@ bool
intel_renderbuffer_resolve_depth(struct intel_context *intel,
struct intel_renderbuffer *irb);
+unsigned
+intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);
+
#ifdef __cplusplus
}
#endif
--
1.7.11.4
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[Mesa-dev] [PATCH 03/15] intel: Refactor creation of hiz and mcs miptrees
Move the logic for creating the ancillary hiz and mcs miptress for winsys
and non-texture renderbuffers from intel_alloc_renderbuffer_storage to
intel_miptree_create_for_renderbuffer. Let's try to isolate complex
miptree logic to intel_mipmap_tree.c.
Without this refactor, code duplication would be required along the
intel_process_dri2_buffer codepath in order to create the mcs miptree.
Reviewed-by: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c | 16
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 19 +++
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index cea57e6..e6e6408 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -274,22 +274,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
if (!irb-mt)
return false;
- if (intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
- bool ok = intel_miptree_alloc_hiz(intel, irb-mt, rb-NumSamples);
- if (!ok) {
-intel_miptree_release(irb-mt);
-return false;
- }
- }
-
- if (irb-mt-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
- bool ok = intel_miptree_alloc_mcs(intel, irb-mt, rb-NumSamples);
- if (!ok) {
- intel_miptree_release(irb-mt);
- return false;
- }
- }
-
return true;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 9f349d0..b6ecbca 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -334,6 +334,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context
*intel,
struct intel_mipmap_tree *mt;
uint32_t depth = 1;
enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE;
+ bool ok;
if (num_samples 1) {
/* Adjust width/height/depth for MSAA */
@@ -397,8 +398,26 @@ intel_miptree_create_for_renderbuffer(struct intel_context
*intel,
mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0,
width, height, depth, true, num_samples,
msaa_layout);
+ if (!mt)
+ goto fail;
+
+ if (intel-vtbl.is_hiz_depth_format(intel, format)) {
+ ok = intel_miptree_alloc_hiz(intel, mt, num_samples);
+ if (!ok)
+ goto fail;
+ }
+
+ if (mt-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ ok = intel_miptree_alloc_mcs(intel, mt, num_samples);
+ if (!ok)
+ goto fail;
+ }
return mt;
+
+fail:
+ intel_miptree_release(mt);
+ return NULL;
}
void
--
1.7.11.4
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[Mesa-dev] [PATCH 05/15] i965: Add function brw_blorp_blit_miptrees
Define a function, brw_blorp_blit_miptrees, that simply wraps
brw_blorp_blit_params + brw_blorp_exec with C calling conventions. This
enables intel_miptree.c, in a following commit, to perform blits with
blorp for the purpose of downsampling multisample miptrees.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_blorp.h| 17 +
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 24
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 9af492d..8d05543 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -30,6 +30,21 @@
struct brw_context;
+#ifdef __cplusplus
+extern C {
+#endif
+
+void
+brw_blorp_blit_miptrees(struct intel_context *intel,
+struct intel_mipmap_tree *src_mt,
+struct intel_mipmap_tree *dst_mt,
+int src_x0, int src_y0,
+int dst_x0, int dst_y0,
+int dst_x1, int dst_y1,
+bool mirror_x, bool mirror_y);
+
+#ifdef __cplusplus
+} /* end extern C */
/**
* Binding table indices used by BLORP.
@@ -340,3 +355,5 @@ void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
const brw_blorp_params *params);
/** \} */
+
+#endif /* __cplusplus */
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1206237..700b0cf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -121,6 +121,23 @@ find_miptree(GLbitfield buffer_bit, struct gl_renderbuffer
*rb)
return mt;
}
+void
+brw_blorp_blit_miptrees(struct intel_context *intel,
+struct intel_mipmap_tree *src_mt,
+struct intel_mipmap_tree *dst_mt,
+int src_x0, int src_y0,
+int dst_x0, int dst_y0,
+int dst_x1, int dst_y1,
+bool mirror_x, bool mirror_y)
+{
+ brw_blorp_blit_params params(brw_context(intel-ctx),
+src_mt, dst_mt,
+src_x0, src_y0,
+dst_x0, dst_y0,
+dst_x1, dst_y1,
+mirror_x, mirror_y);
+ brw_blorp_exec(intel, params);
+}
static void
do_blorp_blit(struct intel_context *intel, GLbitfield buffer_bit,
@@ -142,10 +159,9 @@ do_blorp_blit(struct intel_context *intel, GLbitfield
buffer_bit,
intel_renderbuffer_resolve_depth(intel, intel_renderbuffer(dst_rb));
/* Do the blit */
- brw_blorp_blit_params params(brw_context(ctx), src_mt, dst_mt,
-srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
-mirror_x, mirror_y);
- brw_blorp_exec(intel, params);
+ brw_blorp_blit_miptrees(intel, src_mt, dst_mt,
+ srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
+ mirror_x, mirror_y);
/* Mark the dst buffer as needing a HiZ resolve if necessary. */
intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb));
--
1.7.11.4
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[Mesa-dev] [PATCH 04/15] intel: Allocate miptree for multisample DRI2 buffers (v3)
Immediately after obtaining, with DRI2GetBuffersWithFormat, the DRM buffer
handle for a DRI2 buffer, we wrap that DRM buffer handle with a region and
a miptree. This patch additionally allocates an accompanying multisample
miptree if the DRI2 buffer is multisampled.
Since we do not yet advertise multisample GL configs, the code for
allocating the multisample miptree is currently inactive.
This patch adds the following fields to intel_mipmap_tree:
singlesample_mt
needs_downsample
and the following function stubs:
intel_miptree_downsample
intel_miptree_upsample
v2:
- Fix typo 'miptre'.
- Upsample when rendering to the front buffer, per Paul.
v3:
- Fold introduction of new fields into this patch, per Anholt.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_context.c | 27 ++---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 84 ++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 59 ++
3 files changed, 162 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 378859c..b32daa3 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -893,14 +893,24 @@ intel_process_dri2_buffer(struct intel_context *intel,
if (!rb)
return;
+ unsigned num_samples = rb-Base.Base.NumSamples;
+
/* We try to avoid closing and reopening the same BO name, because the first
* use of a mapping of the buffer involves a bunch of page faulting which is
* moderately expensive.
*/
- if (rb-mt
- rb-mt-region
- rb-mt-region-name == buffer-name)
- return;
+ if (num_samples == 0) {
+ if (rb-mt
+ rb-mt-region
+ rb-mt-region-name == buffer-name)
+ return;
+ } else {
+ if (rb-mt
+ rb-mt-singlesample_mt
+ rb-mt-singlesample_mt-region
+ rb-mt-singlesample_mt-region-name == buffer-name)
+ return;
+ }
if (unlikely(INTEL_DEBUG DEBUG_DRI)) {
fprintf(stderr,
@@ -920,9 +930,10 @@ intel_process_dri2_buffer(struct intel_context *intel,
if (!region)
return;
- rb-mt = intel_miptree_create_for_region(intel,
-GL_TEXTURE_2D,
-intel_rb_format(rb),
-region);
+ rb-mt = intel_miptree_create_for_dri2_buffer(intel,
+ buffer-attachment,
+ intel_rb_format(rb),
+ num_samples,
+ region);
intel_region_release(region);
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index b6ecbca..5da24f2 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -25,6 +25,9 @@
*
**/
+#include GL/gl.h
+#include GL/internal/dri_interface.h
+
#include intel_batchbuffer.h
#include intel_context.h
#include intel_mipmap_tree.h
@@ -324,6 +327,62 @@ compute_msaa_layout(struct intel_context *intel, gl_format
format)
}
}
+/**
+ * For a singlesample DRI2 buffer, this simply wraps the given region with a
miptree.
+ *
+ * For a multisample DRI2 buffer, this wraps the given region with
+ * a singlesample miptree, then creates a multisample miptree into which the
+ * singlesample miptree is embedded as a child.
+ */
+struct intel_mipmap_tree*
+intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
+ unsigned dri_attachment,
+ gl_format format,
+ uint32_t num_samples,
+ struct intel_region *region)
+{
+ struct intel_mipmap_tree *singlesample_mt = NULL;
+ struct intel_mipmap_tree *multisample_mt = NULL;
+ GLenum base_format = _mesa_get_format_base_format(format);
+
+ /* Only the front and back buffers, which are color buffers, are shared
+* through DRI2.
+*/
+ assert(dri_attachment == __DRI_BUFFER_BACK_LEFT ||
+ dri_attachment == __DRI_BUFFER_FRONT_LEFT ||
+ dri_attachment == __DRI_BUFFER_FAKE_FRONT_LEFT);
+ assert(base_format == GL_RGB || base_format == GL_RGBA);
+
+ singlesample_mt = intel_miptree_create_for_region(intel, GL_TEXTURE_2D,
+ format, region);
+ if (!singlesample_mt)
+ return NULL;
+
+ if (num_samples == 0)
+ return singlesample_mt;
+
+ multisample_mt = intel_miptree_create_for_renderbuffer(intel,
+
[Mesa-dev] [PATCH 06/15] intel: Define functions for up/downsampling on miptrees (v3)
Flesh out the stub functions intel_miptree_{up,down}sample.
v2:
- Add an upsample function.
- Also up/downsample the stencil miptree.
- Assert that the miptree is flat.
v3:
- Move direction-dependent code out of shared function, per Anholt.
- Move functions from brw_blorp_orphans.cpp into intel_mipmap_tree.c,
per Anholt.
- Delete brw_blorp_orphans.cpp, per Anholt.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 74 +-
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 5da24f2..b424e4d 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -38,6 +38,10 @@
#include intel_tex.h
#include intel_blit.h
+#ifndef I915
+#include brw_blorp.h
+#endif
+
#include main/enums.h
#include main/formats.h
#include main/glformats.h
@@ -959,6 +963,48 @@ intel_miptree_all_slices_resolve_depth(struct
intel_context *intel,
GEN6_HIZ_OP_DEPTH_RESOLVE);
}
+static void
+intel_miptree_updownsample(struct intel_context *intel,
+ struct intel_mipmap_tree *src,
+ struct intel_mipmap_tree *dst,
+ unsigned width,
+ unsigned height)
+{
+#ifndef I915
+ int src_x0 = 0;
+ int src_y0 = 0;
+ int dst_x0 = 0;
+ int dst_y0 = 0;
+
+ intel_miptree_slice_resolve_depth(intel, src, 0, 0);
+ intel_miptree_slice_resolve_depth(intel, dst, 0, 0);
+
+ brw_blorp_blit_miptrees(intel,
+ src, dst,
+ src_x0, src_y0,
+ dst_x0, dst_y0,
+ width, height,
+ false, false /*mirror x, y*/);
+
+ if (src-stencil_mt) {
+ brw_blorp_blit_miptrees(intel,
+ src-stencil_mt, dst-stencil_mt,
+ src_x0, src_y0,
+ dst_x0, dst_y0,
+ width, height,
+ false, false /*mirror x, y*/);
+ }
+#endif /* I915 */
+}
+
+static void
+assert_is_flat(struct intel_mipmap_tree *mt)
+{
+ assert(mt-target == GL_TEXTURE_2D);
+ assert(mt-first_level == 0);
+ assert(mt-last_level == 0);
+}
+
/**
* \brief Downsample from mt to mt-singlesample_mt.
*
@@ -968,7 +1014,23 @@ void
intel_miptree_downsample(struct intel_context *intel,
struct intel_mipmap_tree *mt)
{
- /* TODO: stub */
+ /* Only flat, renderbuffer-like miptrees are supported. */
+ assert_is_flat(mt);
+
+ if (!mt-need_downsample)
+ return;
+ intel_miptree_updownsample(intel,
+ mt, mt-singlesample_mt,
+ mt-singlesample_mt-width0,
+ mt-singlesample_mt-height0);
+ mt-need_downsample = false;
+
+ /* Strictly speaking, after a downsample on a depth miptree, a hiz
+* resolve is needed on the singlesample miptree. However, since the
+* singlesample miptree is never rendered to, the hiz resolve will never
+* occur. Therefore we do not mark the needed hiz resolve after
+* downsampling.
+*/
}
/**
@@ -980,7 +1042,15 @@ void
intel_miptree_upsample(struct intel_context *intel,
struct intel_mipmap_tree *mt)
{
- /* TODO: stub */
+ /* Only flat, renderbuffer-like miptrees are supported. */
+ assert_is_flat(mt);
+ assert(!mt-need_downsample);
+
+ intel_miptree_updownsample(intel,
+ mt-singlesample_mt, mt,
+ mt-singlesample_mt-width0,
+ mt-singlesample_mt-height0);
+ intel_miptree_slice_set_needs_hiz_resolve(mt, 0, 0);
}
static void
--
1.7.11.4
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[Mesa-dev] [PATCH 07/15] i965: Mark needed downsamples for msaa winsys buffers
Add function intel_renderbuffer_set_needs_downsample. It is a no-op
except on multisample winsys buffers shared with DRI2.
Mark the needed downsamples with the new function at two locations:
- Immediately after drawing is complete.
- After blitting.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c | 20 +++-
src/mesa/drivers/dri/intel/intel_fbo.c | 10 ++
src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 700b0cf..53b72f6 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -163,8 +163,8 @@ do_blorp_blit(struct intel_context *intel, GLbitfield
buffer_bit,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
mirror_x, mirror_y);
- /* Mark the dst buffer as needing a HiZ resolve if necessary. */
intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb));
+ intel_renderbuffer_set_needs_downsample(intel_renderbuffer(dst_rb));
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 1069a63..ccfc306 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -326,18 +326,28 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
* If the depth buffer was written to and if it has an accompanying HiZ
* buffer, then mark that it needs a depth resolve.
*
- * (In the future, this will also mark needed MSAA resolves).
+ * If the color buffer is a multisample window system buffer, then
+ * mark that it needs a downsample.
*/
static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
{
+ struct intel_context *intel = brw-intel;
struct gl_context *ctx = brw-intel.ctx;
struct gl_framebuffer *fb = ctx-DrawBuffer;
- struct intel_renderbuffer *depth_irb =
-intel_get_renderbuffer(fb, BUFFER_DEPTH);
- if (depth_irb ctx-Depth.Mask) {
+ struct intel_renderbuffer *front_irb = NULL;
+ struct intel_renderbuffer *back_irb = intel_get_renderbuffer(fb,
BUFFER_BACK_LEFT);
+ struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb,
BUFFER_DEPTH);
+
+ if (intel-is_front_buffer_rendering)
+ front_irb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
+
+ if (front_irb)
+ intel_renderbuffer_set_needs_downsample(front_irb);
+ if (back_irb)
+ intel_renderbuffer_set_needs_downsample(back_irb);
+ if (depth_irb ctx-Depth.Mask)
intel_renderbuffer_set_needs_depth_resolve(depth_irb);
- }
}
static int
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index e6e6408..3a610c2 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -881,6 +881,16 @@ intel_blit_framebuffer(struct gl_context *ctx,
mask, filter);
}
+/**
+ * This is a no-op except on multisample buffers shared with DRI2.
+ */
+void
+intel_renderbuffer_set_needs_downsample(struct intel_renderbuffer *irb)
+{
+ if (irb-mt irb-mt-singlesample_mt)
+ irb-mt-need_downsample = true;
+}
+
void
intel_renderbuffer_set_needs_hiz_resolve(struct intel_renderbuffer *irb)
{
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index 72ed04d..6574f0f 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -170,6 +170,9 @@ struct intel_region*
intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex);
void
+intel_renderbuffer_set_needs_downsample(struct intel_renderbuffer *irb);
+
+void
intel_renderbuffer_set_needs_hiz_resolve(struct intel_renderbuffer *irb);
void
--
1.7.11.4
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[Mesa-dev] [PATCH 08/15] intel: Refactor intel_miptree_map/unmap
Move the body of intel_miptree_map into a new function,
intel_miptree_map_singlesample. Now intel_miptree_map dispatches to the
new function. A future commit adds a multisample variant.
Ditto for intel_miptree_unmap.
CC: Paul Berry stereotype...@gmail.com
CC: Eric Anholt e...@anholt.net
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 67 +++---
1 file changed, 50 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index b424e4d..2a00c78 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -1448,21 +1448,23 @@ intel_miptree_unmap_depthstencil(struct intel_context
*intel,
free(map-buffer);
}
-void
-intel_miptree_map(struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int slice,
- unsigned int x,
- unsigned int y,
- unsigned int w,
- unsigned int h,
- GLbitfield mode,
- void **out_ptr,
- int *out_stride)
+static void
+intel_miptree_map_singlesample(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice,
+ unsigned int x,
+ unsigned int y,
+ unsigned int w,
+ unsigned int h,
+ GLbitfield mode,
+ void **out_ptr,
+ int *out_stride)
{
struct intel_miptree_map *map;
+ assert(mt-num_samples == 0);
+
map = calloc(1, sizeof(struct intel_miptree_map));
if (!map){
*out_ptr = NULL;
@@ -1507,14 +1509,16 @@ intel_miptree_map(struct intel_context *intel,
}
}
-void
-intel_miptree_unmap(struct intel_context *intel,
- struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int slice)
+static void
+intel_miptree_unmap_singlesample(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice)
{
struct intel_miptree_map *map = mt-level[level].slice[slice].map;
+ assert(mt-num_samples == 0);
+
if (!map)
return;
@@ -1536,3 +1540,32 @@ intel_miptree_unmap(struct intel_context *intel,
mt-level[level].slice[slice].map = NULL;
free(map);
}
+
+void
+intel_miptree_map(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice,
+ unsigned int x,
+ unsigned int y,
+ unsigned int w,
+ unsigned int h,
+ GLbitfield mode,
+ void **out_ptr,
+ int *out_stride)
+{
+ intel_miptree_map_singlesample(intel, mt,
+ level, slice,
+ x, y, w, h,
+ mode,
+ out_ptr, out_stride);
+}
+
+void
+intel_miptree_unmap(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice)
+{
+ intel_miptree_unmap_singlesample(intel, mt, level, slice);
+}
--
1.7.11.4
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[Mesa-dev] [PATCH 10/15] intel: Support mapping multisample miptrees (v2)
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
v2:
- Move the introduction of
intel_mipmap_tree::singlesample_{width0,height0} to this patch, per
Anholt.
- Replace relations `mt-num_samples == 0` and `mt-num_samples 0`
with `= 1` and ` 0`, per Anholt.
- Don't downsample unnecessarily, found by Anholt.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 115 +++--
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 18
2 files changed, 127 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 23d84c0..6ecb48f 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -397,6 +397,8 @@ intel_miptree_create_for_renderbuffer(struct intel_context
*intel,
struct intel_mipmap_tree *mt;
uint32_t depth = 1;
enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE;
+ const uint32_t singlesample_width = width;
+ const uint32_t singlesample_height = height;
bool ok;
if (num_samples 1) {
@@ -476,6 +478,9 @@ intel_miptree_create_for_renderbuffer(struct intel_context
*intel,
goto fail;
}
+ mt-singlesample_width0 = singlesample_width;
+ mt-singlesample_height0 = singlesample_height;
+
return mt;
fail:
@@ -1576,6 +1581,94 @@ intel_miptree_unmap_singlesample(struct intel_context
*intel,
intel_miptree_release_map(mt, level, slice);
}
+static void
+intel_miptree_map_multisample(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice,
+ unsigned int x,
+ unsigned int y,
+ unsigned int w,
+ unsigned int h,
+ GLbitfield mode,
+ void **out_ptr,
+ int *out_stride)
+{
+ struct intel_miptree_map *map;
+
+ assert(mt-num_samples 1);
+
+ /* Only flat, renderbuffer-like miptrees are supported. */
+ if (mt-target != GL_TEXTURE_2D ||
+ mt-first_level != 0 ||
+ mt-last_level != 0) {
+ _mesa_problem(intel-ctx, attempt to map a multisample miptree for
+which (target, first_level, last_level !=
+(GL_TEXTURE_2D, 0, 0));
+ goto fail;
+ }
+
+ map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
+ if (!map)
+ goto fail;
+
+ if (!mt-singlesample_mt) {
+ map-singlesample_mt_is_tmp = true;
+ mt-need_downsample = true;
+ mt-singlesample_mt =
+ intel_miptree_create_for_renderbuffer(intel,
+ mt-format,
+ mt-singlesample_width0,
+ mt-singlesample_height0,
+ 0 /*num_samples*/);
+ if (!mt-singlesample_mt) {
+ mt-need_downsample = false;
+ goto fail;
+ }
+ }
+
+ if (mode GL_MAP_INVALIDATE_RANGE_BIT)
+ mt-need_downsample = false;
+
+ intel_miptree_downsample(intel, mt);
+ intel_miptree_map_singlesample(intel, mt-singlesample_mt,
+ level, slice,
+ x, y, w, h,
+ mode,
+ out_ptr, out_stride);
+ return;
+
+fail:
+ intel_miptree_release_map(mt, level, slice);
+ *out_ptr = NULL;
+ *out_stride = 0;
+}
+
+static void
+intel_miptree_unmap_multisample(struct intel_context *intel,
+struct intel_mipmap_tree *mt,
+unsigned int level,
+unsigned int slice)
+{
+ struct intel_miptree_map *map = mt-level[level].slice[slice].map;
+
+ assert(mt-num_samples 1);
+
+ if (!map)
+ return;
+
+ intel_miptree_unmap_singlesample(intel, mt-singlesample_mt, level, slice);
+
+ mt-need_downsample = false;
+ if (map-mode GL_MAP_WRITE_BIT)
+ intel_miptree_upsample(intel, mt);
+
+ if (map-singlesample_mt_is_tmp)
+ intel_miptree_release(mt-singlesample_mt);
+
+ intel_miptree_release_map(mt, level, slice);
+}
+
void
intel_miptree_map(struct intel_context *intel,
struct intel_mipmap_tree *mt,
@@ -1589,11 +1682,18 @@ intel_miptree_map(struct intel_context *intel,
void **out_ptr,
int *out_stride)
{
- intel_miptree_map_singlesample(intel, mt,
- level, slice,
[Mesa-dev] [PATCH 11/15] intel: Downsample on DRI2 flush
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 9aca463..a3c0140 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -150,6 +150,36 @@ static const __DRItexBufferExtension
intelTexBufferExtension = {
};
static void
+intel_downsample_for_dri2_flush(struct intel_context *intel,
+__DRIdrawable *drawable)
+{
+ if (intel-gen 6) {
+ /* MSAA is not supported, so don't waste time checking for
+ * a multisample buffer.
+ */
+ return;
+ }
+
+ struct gl_framebuffer *fb = drawable-driverPrivate;
+ struct intel_renderbuffer *rb;
+
+ /* Usually, only the back buffer will need to be downsampled. However,
+* the front buffer will also need it if the user has rendered into it.
+*/
+ static const gl_buffer_index buffers[2] = {
+ BUFFER_BACK_LEFT,
+ BUFFER_FRONT_LEFT,
+ };
+
+ for (int i = 0; i 2; ++i) {
+ rb = intel_get_renderbuffer(fb, buffers[i]);
+ if (rb == NULL || rb-mt == NULL)
+ continue;
+ intel_miptree_downsample(intel, rb-mt);
+ }
+}
+
+static void
intelDRI2Flush(__DRIdrawable *drawable)
{
GET_CURRENT_CONTEXT(ctx);
@@ -160,6 +190,7 @@ intelDRI2Flush(__DRIdrawable *drawable)
if (intel-gen 4)
INTEL_FIREVERTICES(intel);
+ intel_downsample_for_dri2_flush(intel, drawable);
intel-need_throttle = true;
if (intel-batch.used)
--
1.7.11.4
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[Mesa-dev] [PATCH 09/15] intel: Refactor use of intel_miptree_map
Move the opencoded construction and destruction of intel_miptree_map into
new functions, intel_miptree_attach_map and intel_miptree_release_map.
This patch prevents code duplication in a future commit that adds support
for mapping multisample miptrees.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 65 --
1 file changed, 50 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 2a00c78..23d84c0 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -1448,6 +1448,52 @@ intel_miptree_unmap_depthstencil(struct intel_context
*intel,
free(map-buffer);
}
+/**
+ * Create and attach a map to the miptree at (level, slice). Return the
+ * attached map.
+ */
+static struct intel_miptree_map*
+intel_miptree_attach_map(struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice,
+ unsigned int x,
+ unsigned int y,
+ unsigned int w,
+ unsigned int h,
+ GLbitfield mode)
+{
+ struct intel_miptree_map *map = calloc(1, sizeof(*map));
+
+ if (!map)
+ return NULL;
+
+ assert(mt-level[level].slice[slice].map == NULL);
+ mt-level[level].slice[slice].map = map;
+
+ map-mode = mode;
+ map-x = x;
+ map-y = y;
+ map-w = w;
+ map-h = h;
+
+ return map;
+}
+
+/**
+ * Release the map at (level, slice).
+ */
+static void
+intel_miptree_release_map(struct intel_mipmap_tree *mt,
+ unsigned int level,
+ unsigned int slice)
+{
+ struct intel_miptree_map **map;
+
+ map = mt-level[level].slice[slice].map;
+ free(*map);
+ *map = NULL;
+}
+
static void
intel_miptree_map_singlesample(struct intel_context *intel,
struct intel_mipmap_tree *mt,
@@ -1465,21 +1511,13 @@ intel_miptree_map_singlesample(struct intel_context
*intel,
assert(mt-num_samples == 0);
- map = calloc(1, sizeof(struct intel_miptree_map));
+ map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
if (!map){
*out_ptr = NULL;
*out_stride = 0;
return;
}
- assert(!mt-level[level].slice[slice].map);
- mt-level[level].slice[slice].map = map;
- map-mode = mode;
- map-x = x;
- map-y = y;
- map-w = w;
- map-h = h;
-
intel_miptree_slice_resolve_depth(intel, mt, level, slice);
if (map-mode GL_MAP_WRITE_BIT) {
intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice);
@@ -1503,10 +1541,8 @@ intel_miptree_map_singlesample(struct intel_context
*intel,
*out_ptr = map-ptr;
*out_stride = map-stride;
- if (map-ptr == NULL) {
- mt-level[level].slice[slice].map = NULL;
- free(map);
- }
+ if (map-ptr == NULL)
+ intel_miptree_release_map(mt, level, slice);
}
static void
@@ -1537,8 +1573,7 @@ intel_miptree_unmap_singlesample(struct intel_context
*intel,
intel_miptree_unmap_gtt(intel, mt, map, level, slice);
}
- mt-level[level].slice[slice].map = NULL;
- free(map);
+ intel_miptree_release_map(mt, level, slice);
}
void
--
1.7.11.4
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[Mesa-dev] [PATCH 12/15] intel: Refactor creation of DRI2 configs
DRI2 configs were constructed in intelInitScreen2. That function already
does too much, so move verbatim the code for creating configs to a new
function, intel_screen_make_configs.
CC: Eric Anholt e...@anholt.net
Reviewed-by: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 189 --
1 file changed, 98 insertions(+), 91 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index a3c0140..491f12a 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -821,6 +821,103 @@ intel_detect_swizzling(struct intel_screen *screen)
return true;
}
+static __DRIconfig**
+intel_screen_make_configs(__DRIscreen *dri_screen)
+{
+ static const GLenum back_buffer_modes[] = {
+ GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
+ };
+
+ GLenum fb_format[3];
+ GLenum fb_type[3];
+ uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
+ int color;
+ __DRIconfig **configs = NULL;
+
+ msaa_samples_array[0] = 0;
+
+ fb_format[0] = GL_RGB;
+ fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
+
+ fb_format[1] = GL_BGR;
+ fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
+
+ fb_format[2] = GL_BGRA;
+ fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
+
+ depth_bits[0] = 0;
+ stencil_bits[0] = 0;
+
+ /* Generate a rich set of useful configs that do not include an
+* accumulation buffer.
+*/
+ for (color = 0; color ARRAY_SIZE(fb_format); color++) {
+ __DRIconfig **new_configs;
+ int depth_factor;
+
+ /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
+ * buffer that has a different number of bits per pixel than the color
+ * buffer. This isn't yet supported here.
+ */
+ if (fb_type[color] == GL_UNSIGNED_SHORT_5_6_5) {
+ depth_bits[1] = 16;
+ stencil_bits[1] = 0;
+ } else {
+ depth_bits[1] = 24;
+ stencil_bits[1] = 8;
+ }
+
+ depth_factor = 2;
+
+ new_configs = driCreateConfigs(fb_format[color], fb_type[color],
+ depth_bits,
+ stencil_bits,
+ depth_factor,
+ back_buffer_modes,
+ ARRAY_SIZE(back_buffer_modes),
+ msaa_samples_array,
+ ARRAY_SIZE(msaa_samples_array),
+ false);
+ if (configs == NULL)
+ configs = new_configs;
+ else
+ configs = driConcatConfigs(configs, new_configs);
+ }
+
+ /* Generate the minimum possible set of configs that include an
+* accumulation buffer.
+*/
+ for (color = 0; color ARRAY_SIZE(fb_format); color++) {
+ __DRIconfig **new_configs;
+
+ if (fb_type[color] == GL_UNSIGNED_SHORT_5_6_5) {
+ depth_bits[0] = 16;
+ stencil_bits[0] = 0;
+ } else {
+ depth_bits[0] = 24;
+ stencil_bits[0] = 8;
+ }
+
+ new_configs = driCreateConfigs(fb_format[color], fb_type[color],
+ depth_bits, stencil_bits, 1,
+ back_buffer_modes + 1, 1,
+ msaa_samples_array, 1,
+ true);
+ if (configs == NULL)
+ configs = new_configs;
+ else
+ configs = driConcatConfigs(configs, new_configs);
+ }
+
+ if (configs == NULL) {
+ fprintf(stderr, [%s:%u] Error creating FBConfig!\n, __func__,
+ __LINE__);
+ return NULL;
+ }
+
+ return configs;
+}
+
/**
* This is the driver specific part of the createNewScreen entry point.
* Called when using DRI2.
@@ -831,17 +928,8 @@ static const
__DRIconfig **intelInitScreen2(__DRIscreen *psp)
{
struct intel_screen *intelScreen;
- GLenum fb_format[3];
- GLenum fb_type[3];
unsigned int api_mask;
- static const GLenum back_buffer_modes[] = {
- GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
- };
- uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
- int color;
- __DRIconfig **configs = NULL;
-
if (psp-dri2.loader-base.version = 2 ||
psp-dri2.loader-getBuffersWithFormat == NULL) {
fprintf(stderr,
@@ -914,88 +1002,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
psp-extensions = intelScreenExtensions;
- msaa_samples_array[0] = 0;
-
- fb_format[0] = GL_RGB;
- fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
-
- fb_format[1] = GL_BGR;
- fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
-
- fb_format[2] = GL_BGRA;
- fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
-
- depth_bits[0] = 0;
- stencil_bits[0] = 0;
-
- /* Generate a rich set of useful configs that do not include an
-* accumulation
[Mesa-dev] [PATCH 14/15] intel: Clarify intel_screen_make_configs
This function felt sloppy, so this patch cleans it up a little bit.
- Rename `color` to `i`. It is not a color value, only an iterator int.
- Move `depth_bits[0] = 0` into the non-accum loop because that is where
it used. The accum loop later overwrites depth_bits[0].
- Redefine `msaa_samples_array` as static const because it is never
modified.
CC: Eric Anholt e...@anholt.net
CC: Ian Romanick i...@freedesktop.org
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 34 ++-
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index dea7b66..9cc5480 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -828,14 +828,13 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
+ static const msaa_samples_array[1] = {0};
+
GLenum fb_format[3];
GLenum fb_type[3];
- uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
- int color;
+ uint8_t depth_bits[4], stencil_bits[4];
__DRIconfig **configs = NULL;
- msaa_samples_array[0] = 0;
-
fb_format[0] = GL_RGB;
fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
@@ -845,21 +844,21 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
fb_format[2] = GL_BGRA;
fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
- depth_bits[0] = 0;
- stencil_bits[0] = 0;
-
/* Generate a rich set of useful configs that do not include an
* accumulation buffer.
*/
- for (color = 0; color ARRAY_SIZE(fb_format); color++) {
+ for (int i = 0; i ARRAY_SIZE(fb_format); i++) {
__DRIconfig **new_configs;
- int depth_factor;
+ const int num_depth_stencil_bits = 2;
/* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer. This isn't yet supported here.
*/
- if (fb_type[color] == GL_UNSIGNED_SHORT_5_6_5) {
+ depth_bits[0] = 0;
+ stencil_bits[0] = 0;
+
+ if (fb_type[i] == GL_UNSIGNED_SHORT_5_6_5) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
} else {
@@ -867,16 +866,13 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[1] = 8;
}
- depth_factor = 2;
-
- new_configs = driCreateConfigs(fb_format[color], fb_type[color],
+ new_configs = driCreateConfigs(fb_format[i], fb_type[i],
depth_bits,
stencil_bits,
- depth_factor,
+ num_depth_stencil_bits,
back_buffer_modes,
ARRAY_SIZE(back_buffer_modes),
- msaa_samples_array,
- ARRAY_SIZE(msaa_samples_array),
+ msaa_samples_array, 1,
false);
configs = driConcatConfigs(configs, new_configs);
}
@@ -884,10 +880,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
/* Generate the minimum possible set of configs that include an
* accumulation buffer.
*/
- for (color = 0; color ARRAY_SIZE(fb_format); color++) {
+ for (int i = 0; i ARRAY_SIZE(fb_format); i++) {
__DRIconfig **new_configs;
- if (fb_type[color] == GL_UNSIGNED_SHORT_5_6_5) {
+ if (fb_type[i] == GL_UNSIGNED_SHORT_5_6_5) {
depth_bits[0] = 16;
stencil_bits[0] = 0;
} else {
@@ -895,7 +891,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[0] = 8;
}
- new_configs = driCreateConfigs(fb_format[color], fb_type[color],
+ new_configs = driCreateConfigs(fb_format[i], fb_type[i],
depth_bits, stencil_bits, 1,
back_buffer_modes + 1, 1,
msaa_samples_array, 1,
--
1.7.11.4
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[Mesa-dev] [PATCH 00/16 v3] i965: Enable winsys MSAA on gen = 6
For test results, see the commit message in patch 16. The summary is that piglit, oglconform, and xonotic are all happy. It was nice to play xonotic without seeing ugly, jagged edges. Many of these patches have already been reviewed. I'm not seeking additional review for those, although additional review is welcome. Patches 1-4 accomplish allocating the miptrees for DRI2 buffers. Patches 5-11 accomplish the automatic downsample and upsample operations needed for glFlush, glReadPixels, and software fallbacks. Patches 12-15 enable winsys MSAA by advertising MSAA configs. v3: Incorporate review by Anholt. Kill file brw_blorp_orphans.cpp. Move definitions of intel_miptree_up/downsample into intel_mipmap_tree.c. Check against mt-num_samples 1 rather than 0. Probably a few more things I can't recall, but I've made notes for all the changes in individual commit messages. Chad Versace (15): intel: Refactor quantize_num_samples (v1) intel: Set num samples for winsys renderbuffers (v3) intel: Refactor creation of hiz and mcs miptrees intel: Allocate miptree for multisample DRI2 buffers (v3) i965: Add function brw_blorp_blit_miptrees intel: Define functions for up/downsampling on miptrees (v3) i965: Mark needed downsamples for msaa winsys buffers intel: Refactor intel_miptree_map/unmap intel: Refactor use of intel_miptree_map intel: Support mapping multisample miptrees (v2) intel: Downsample on DRI2 flush intel: Refactor creation of DRI2 configs dri: Simplify use of driConcatConfigs intel: Clarify intel_screen_make_configs intel: Advertise multisample DRI2 configs on gen = 6 src/gallium/state_trackers/dri/common/dri_screen.c | 12 +- src/mesa/drivers/dri/common/utils.c| 5 + src/mesa/drivers/dri/i965/brw_blorp.h | 17 + src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 26 +- src/mesa/drivers/dri/i965/brw_draw.c | 20 +- src/mesa/drivers/dri/intel/intel_context.c | 27 +- src/mesa/drivers/dri/intel/intel_fbo.c | 44 +-- src/mesa/drivers/dri/intel/intel_fbo.h | 10 +- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 406 +++-- src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 77 src/mesa/drivers/dri/intel/intel_screen.c | 277 +- src/mesa/drivers/dri/nouveau/nouveau_screen.c | 3 +- src/mesa/drivers/dri/radeon/radeon_screen.c| 5 +- 13 files changed, 745 insertions(+), 184 deletions(-) -- 1.7.11.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/15] intel: Set num samples for winsys renderbuffers (v3)
Add a new param, num_samples, to intel_create_renderbuffer and
intel_create_private_renderbuffer.
No multisample GL config is yet advertised, so the value of num_samples is
currently 0. For server-owned winsys buffers, gl_renderbuffer::NumSamples
is not yet used.
v2: Quantize num_samples just once, in intelCreateBuffer, per Anholt.
v3: Remote unneeded screen param from the
intel_create{,_private}_renderbuffer functions, per Anholt.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com (v1)
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_fbo.c| 11 ---
src/mesa/drivers/dri/intel/intel_fbo.h| 4 ++--
src/mesa/drivers/dri/intel/intel_screen.c | 17 +++--
3 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 80af192..cea57e6 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -397,9 +397,11 @@ intel_nop_alloc_storage(struct gl_context * ctx, struct
gl_renderbuffer *rb,
/**
* Create a new intel_renderbuffer which corresponds to an on-screen window,
* not a user-created renderbuffer.
+ *
+ * \param num_samples must be quantized.
*/
struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format)
+intel_create_renderbuffer(gl_format format, unsigned num_samples)
{
struct intel_renderbuffer *irb;
struct gl_renderbuffer *rb;
@@ -419,6 +421,7 @@ intel_create_renderbuffer(gl_format format)
rb-_BaseFormat = _mesa_get_format_base_format(format);
rb-Format = format;
rb-InternalFormat = rb-_BaseFormat;
+ rb-NumSamples = num_samples;
/* intel-specific methods */
rb-Delete = intel_delete_renderbuffer;
@@ -432,13 +435,15 @@ intel_create_renderbuffer(gl_format format)
* server created with intel_create_renderbuffer()) are most similar in their
* handling to user-created renderbuffers, but they have a resize handler that
* may be called at intel_update_renderbuffers() time.
+ *
+ * \param num_samples must be quantized.
*/
struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format)
+intel_create_private_renderbuffer(gl_format format, unsigned num_samples)
{
struct intel_renderbuffer *irb;
- irb = intel_create_renderbuffer(format);
+ irb = intel_create_renderbuffer(format, num_samples);
irb-Base.Base.AllocStorage = intel_alloc_renderbuffer_storage;
return irb;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h
b/src/mesa/drivers/dri/intel/intel_fbo.h
index b922dca..72ed04d 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -130,10 +130,10 @@ intel_rb_format(const struct intel_renderbuffer *rb)
}
extern struct intel_renderbuffer *
-intel_create_renderbuffer(gl_format format);
+intel_create_renderbuffer(gl_format format, unsigned num_samples);
struct intel_renderbuffer *
-intel_create_private_renderbuffer(gl_format format);
+intel_create_private_renderbuffer(gl_format format, unsigned num_samples);
struct gl_renderbuffer*
intel_create_wrapped_renderbuffer(struct gl_context * ctx,
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 90f1778..9aca463 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -550,6 +550,7 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
struct intel_renderbuffer *rb;
struct intel_screen *screen = (struct intel_screen*)
driScrnPriv-driverPrivate;
gl_format rgbFormat;
+ unsigned num_samples = intel_quantize_num_samples(screen, mesaVis-samples);
struct gl_framebuffer *fb;
if (isPixmap)
@@ -569,11 +570,11 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
rgbFormat = MESA_FORMAT_ARGB;
/* setup the hardware-based renderbuffers */
- rb = intel_create_renderbuffer(rgbFormat);
+ rb = intel_create_renderbuffer(rgbFormat, num_samples);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, rb-Base.Base);
if (mesaVis-doubleBufferMode) {
- rb = intel_create_renderbuffer(rgbFormat);
+ rb = intel_create_renderbuffer(rgbFormat, num_samples);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, rb-Base.Base);
}
@@ -586,23 +587,27 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
assert(mesaVis-stencilBits == 8);
if (screen-hw_has_separate_stencil) {
- rb = intel_create_private_renderbuffer(MESA_FORMAT_X8_Z24);
+ rb = intel_create_private_renderbuffer(MESA_FORMAT_X8_Z24,
+num_samples);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, rb-Base.Base);
- rb = intel_create_private_renderbuffer(MESA_FORMAT_S8);
+ rb = intel_create_private_renderbuffer(MESA_FORMAT_S8,
+
[Mesa-dev] [PATCH 15/15] intel: Advertise multisample DRI2 configs on gen = 6
This turns on window system MSAA.
This patch changes the id of many GLX visuals and configs, but that
couldn't be prevented. I attempted to preserve the id's of extant configs
by appending the multisample configs to the end of the extant ones. But
somewhere, perhaps in the X server, the configs are reordered with
multisample configs interspersed among the singlesample ones.
Test results:
Tested with xonotic and `glxgears -samples 1` on Ivybridge.
No piglit regressions on Ivybridge.
On Sandybridge, passes 68/70 of oglconform's
winsys multisample tests. The two failing tests are:
multisample(advanced.pixelmap.depth)
multisample(advanced.pixelmap.depthCopyPixels)
These tests hang the gpu (on kernel 3.4.6) due to
a glDrawPixels/glReadPixels pair on an MSAA depth buffer. I don't expect
realworld apps to do that, so I'm not too concerned about the hang.
On Ivybridge, passes 69/70. The failing case is
multisample(advanced.line.changeWidth).
v2:
- Place MSAA configs after singlesample configs to work around X server
bug.
- Document why supported swap methods differ between singlesample
and multisample configs.
CC: Ian Romanick i...@freedesktop.org
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 58 ---
1 file changed, 54 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 9cc5480..033eda3 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -828,8 +828,9 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
};
- static const msaa_samples_array[1] = {0};
+ static const uint8_t msaa_samples_array[3] = {0, 4, 8};
+ struct intel_screen *screen = dri_screen-driverPrivate;
GLenum fb_format[3];
GLenum fb_type[3];
uint8_t depth_bits[4], stencil_bits[4];
@@ -844,9 +845,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
fb_format[2] = GL_BGRA;
fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
- /* Generate a rich set of useful configs that do not include an
-* accumulation buffer.
-*/
+ /* Generate singlesample configs without accumulation buffer. */
for (int i = 0; i ARRAY_SIZE(fb_format); i++) {
__DRIconfig **new_configs;
const int num_depth_stencil_bits = 2;
@@ -899,6 +898,57 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
configs = driConcatConfigs(configs, new_configs);
}
+ /* Generate multisample configs.
+*
+* This loop breaks early, and hence is a no-op, on gen 6.
+*
+* Multisample configs must follow the singlesample configs in order to
+* work around an X server bug present in 1.12. The X server chooses to
+* associate the first listed RGBA888-Z24S8 config, regardless of its
+* sample count, with the 32-bit depth visual used for compositing.
+*
+* Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
+* supported. Singlebuffer configs are not supported because that would
+* require that rendering be eventually written to the singlesample buffer
+* even if DRI2Flush is never called; yet we downsample to the singlesample
+* buffer only on DRI2Flush. GLX_SWAP_COPY_OML is not supported because we
+* have no tests for its interaction with MSAA.
+*/
+ for (int i = 0; i ARRAY_SIZE(fb_format); i++) {
+ if (screen-gen 6)
+ break;
+
+ __DRIconfig **new_configs;
+ const int num_depth_stencil_bits = 2;
+ int num_msaa_modes;
+
+ depth_bits[0] = 0;
+ stencil_bits[0] = 0;
+
+ if (fb_type[i] == GL_UNSIGNED_SHORT_5_6_5) {
+ depth_bits[1] = 16;
+ stencil_bits[1] = 0;
+ } else {
+ depth_bits[1] = 24;
+ stencil_bits[1] = 8;
+ }
+
+ if (screen-gen = 7)
+ num_msaa_modes = 2;
+ else if (screen-gen == 6)
+ num_msaa_modes = 1;
+
+ new_configs = driCreateConfigs(fb_format[i], fb_type[i],
+ depth_bits,
+ stencil_bits,
+ num_depth_stencil_bits,
+ back_buffer_modes + 1, 1,
+ msaa_samples_array + 1,
+ num_msaa_modes,
+ false);
+ configs = driConcatConfigs(configs, new_configs);
+ }
+
if (configs == NULL) {
fprintf(stderr, [%s:%u] Error creating FBConfig!\n, __func__,
__LINE__);
--
1.7.11.4
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Re: [Mesa-dev] [PATCH 03/16] intel: Add singlesample fields to intel_mipmap_tree
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/06/2012 11:05 AM, Eric Anholt wrote: Chad Versace chad.vers...@linux.intel.com writes: Add the following fields: singlesamle_width0 singlesample_height0 singlesample_mt needs_downsample These will all be used by later commits that implement MSAA for window system buffers. I really don't like splitting the commits for creation of fields from their usage. I was pretty convinced that singlesample_width0/height0 wasn't needed (since it should just be in singlesample_mt, right?) until I searched later in the commit series to find the singlesample_tmp flag, which is introduced in the appropriate commit. Done. In series v3, I declare each field in the first commit that uses it. -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.19 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJQIF9gAAoJEAIvNt057x8i2GIP/Rywo/F9nlP+MBB3Md/N3SU0 UoJqCy/QTrDsWqp6efQADQw5V7pcG+FXlfAej8A1bIBhxER5G+829JJpRNmopiZf 9J1QqYV5i3imVyCsU5jVjrlHDzHGOO9Qx8BOv33w1+i/EgJnigVmmG36GfeMWEbA m8S0tjAEAfX3EEkbabfvHQp9prDXOAseOBoQgGaZNS7+l6v9B2Xen8JLT6v3hds0 HNJwnVbl/KJM0E96WdZPWSzSwyDKL4RA+z12XRo9j9JdmGwCo05pwXIoPBqbHwi6 3+yCvjwoetDyTXqAR7cwli5cHbdth/Omvkyr+kXdDM1+GGSK8V4c7nAwk1YwM7ed qaY+8qCZ9iATWPWiU+vLbLxVUNQbwTyUxr0vvlnsy4gJJFzV4fK2DVnBlCxdXk9K iCI6D1/VcuXMztoR/suBQmoastnJwTwBTN++PaUebzok9l6L8GctP2N3P/ZrDRVW V2ZZ/7VK9TlnYPMmDCmBdT4cStA3A+vA4/PCR4a/b0c7VC6QyJHQJ/aDXXq/LLWc NRc8MWBHH1iAKMOwWlImPQKSSFfe3Md4hKrSvGA/4GziUJF2b6ugInMgCCuqGPZR MiHJWu2ZL62M+opU5YoTHgZBMPe3fdAnxPi7Bf/gzq35XLduBhZpnCOn4e8Z/2dL VO/4KA5eStw1R3H9+DBB =3V+B -END PGP SIGNATURE- ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/16] i965: Add functions up/downsampling on miptrees (v2)
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On 08/06/2012 11:38 AM, Eric Anholt wrote:
Chad Versace chad.vers...@linux.intel.com writes:
These functions do an up or downsample between mt and
mt-singlesample_mt.
+static void +intel_miptree_updownsample(struct intel_context *intel, +
struct intel_mipmap_tree *mt, + enum
intel_updownsample direction) +{ + struct intel_mipmap_tree *src; +
struct intel_mipmap_tree *dst; + + /* Only flat, renderbuffer-like
miptrees are supported. */ + assert(mt-target == GL_TEXTURE_2D); +
assert(mt-first_level == 0); + assert(mt-last_level == 0); + +
switch (direction) { + case INTEL_DOWNSAMPLE: { + if
(!mt-need_downsample) + return; + src = mt; + dst =
mt-singlesample_mt; + break; + } + case INTEL_UPSAMPLE: { +
assert(!mt-need_downsample); + src = mt-singlesample_mt; +
dst = mt; + break; + }
Also, I think the direction-dependent code should be moved into the two
callers.
Done in series v3.
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Re: [Mesa-dev] [PATCH 11/16] intel: Support mapping multisample miptrees
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On 08/06/2012 11:35 AM, Eric Anholt wrote:
Chad Versace chad.vers...@linux.intel.com writes:
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
void @@ -1513,5 +1606,8 @@ intel_miptree_unmap(struct intel_context
*intel, unsigned int level, unsigned int slice) { -
intel_miptree_unmap_singlesample(intel, mt, level, slice); + if
(mt-num_samples == 0)
Isn't mt-num_samples sometimes 1 for a singlesample mt now?
Correct. Fixed in series v3.
+ intel_miptree_unmap_singlesample(intel, mt, level, slice); +
else + intel_miptree_unmap_multisample(intel, mt, level, slice); }
Other than that, downsamples get done in some cases where needs
needs_downsample was false, which is suboptimal. But I think the code is
correct, and this is a fallback path so I don't care too much.
Yeah... but since you pointed it out, I could not help but fix it. Unnecessary
downsamples are removed in series v3.
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Re: [Mesa-dev] [PATCH] glx/dri: Initialize reset to __DRI_CTX_RESET_NO_NOTIFICATION.
On Mon, Aug 6, 2012 at 4:49 PM, Kenneth Graunke kenn...@whitecape.org wrote:
I noticed that we have a bit of inconsistency in how we handle context
defaults. In some cases, we initialize variables with default values in
dri{2,sw}_create_context_attribs. In other cases, we rely on
dri2_convert_glx_attribs to do that for us.
For example, in dri2_convert_glx_attribs:
uint32_t minor_ver = 1;
uint32_t major_ver = 2;
uint32_t flags = 0;
unsigned api;
int reset;
we default the version to 2.1. Whereas in dri_convert_glx_attribs we have:
if (num_attribs == 0) {
*api = __DRI_API_OPENGL;
return true;
}
...
*major_ver = 1;
*minor_ver = 0;
*reset = __DRI_CTX_RESET_NO_NOTIFICATION;
So if they try to create a context with _no_ attributes, we pick 2.1.
If they specify _some_ attributes, but not version attributes, we hit
this code and pick 1.0. drisw_create_context_attribs also defaults to 1.0.
My feeling is that we should either make dri2_convert_glx_attribs not
short-circuit on num_attribs == 0, so it fully initializes all the
defaults, or we should make both the callers fully specify defaults and
remove the block that makes it set them. Either would work, but it'd be
nice to pick one.
Preferences?
I would vote to move the initialization fully to dri2_convert_glx_attribs.
-Jordan
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Re: [Mesa-dev] R600 VDPAU 422 regression since r600g: make sure copying of all texture formats is accelerated
Does the attached patch fix this issue? Marek On Mon, Aug 6, 2012 at 5:40 PM, Andy Furniss andy...@ukfsn.org wrote: Kernel is dcn card is rv790 - vdpau csc/scale regressed. This only shows with 422 colour so most things work. commit 7c371f46958910dd2ca9487c89af1b72bbfdada9 Author: Marek Olšák mar...@gmail.com Date: Sat Jul 28 00:38:42 2012 +0200 r600g: make sure copying of all texture formats is accelerated [drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream ! radeon :01:00.0: texture bo too small ((704 576) (1 1) 0 26 0 - 1622016 have 884736) radeon :01:00.0: alignments 384 1 1 1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev 0001-r600g-fix-yuv-blits.patch Description: Binary data ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/22] glsl: Add a ubo_load expression type for fetches from UBOs.
Kenneth Graunke kenn...@whitecape.org writes:
On 07/31/2012 03:01 PM, Eric Anholt wrote:
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index f019837..2807ba6 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1018,9 +1018,18 @@ enum ir_expression_operation {
ir_binop_pow,
/**
+* Load a value the size of a given GLSL type from a uniform block.
+*
+* operand0 is the uniform block index in the linked shader.
+* operand1 is a constant or variable byte offset within the
Constant or variable...you don't say :)
I'd just go with byte offset within the uniform block.
Err, yeah. operand 0 should have been clarified to be ir_constant,
while the qualifiers on operand 1 weren't helping.
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Re: [Mesa-dev] [PATCH 15/22] mesa: Add support for glUniformBlockBinding() in display lists.
Brian Paul bri...@vmware.com writes:
On 07/31/2012 04:01 PM, Eric Anholt wrote:
Fixes piglit GL_ARB_uniform_buffer_object/dlist.
---
src/mesa/main/dlist.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 510fd1e..e3dc9c0 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -482,6 +482,9 @@ typedef enum
OPCODE_DRAW_TRANSFORM_FEEDBACK_INSTANCED,
OPCODE_DRAW_TRANSFORM_FEEDBACK_STREAM_INSTANCED,
+ /* ARB_uniform_buffer_object */
+ OPCODE_UNIFORM_BLOCK_BINDING,
+
/* The following three are meta instructions */
OPCODE_ERROR,/* raise compiled-in error */
OPCODE_CONTINUE,
@@ -7582,6 +7585,23 @@ save_EndConditionalRender(void)
}
}
+static void GLAPIENTRY
+save_UniformBlockBinding(GLuint prog, GLuint index, GLuint binding)
+{
+ GET_CURRENT_CONTEXT(ctx);
+ Node *n;
+ ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+ n = alloc_instruction(ctx, OPCODE_UNIFORM_BLOCK_BINDING, 3);
+ if (n) {
+ n[1].i = prog;
+ n[2].i = index;
+ n[3].i = binding;
It won't make any real difference, but the 'i' fields should be 'ui'
for type consistency.
+ }
+ if (ctx-ExecuteFlag) {
+ CALL_UniformBlockBinding(ctx-Exec, (prog, index, binding));
+ }
+}
+
/**
* Save an error-generating command into display list.
@@ -8877,6 +8897,10 @@ execute_list(struct gl_context *ctx, GLuint list)
CALL_EndConditionalRenderNV(ctx-Exec, ());
break;
+ case OPCODE_UNIFORM_BLOCK_BINDING:
+CALL_UniformBlockBinding(ctx-Exec, (n[1].i, n[2].i, n[3].i));
s/i/ui/ here too.
Fixed, thanks!
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Re: [Mesa-dev] [PATCH 17/22] i965: Bind UBOs as surfaces like we do for pull constants.
Kenneth Graunke kenn...@whitecape.org writes:
On 07/31/2012 03:01 PM, Eric Anholt wrote:
+const struct brw_tracked_state brw_vs_ubo_surfaces = {
+ .dirty = {
+ .mesa = (_NEW_PROGRAM |
+ _NEW_BUFFER_OBJECT),
+ .brw = (BRW_NEW_BATCH),
You don't actually need the extra parenthesis...IMHO,
.foo = bits | morebits | yetmorebits,
.bar = ...
is already quite readable, and definitely unambiguous (the = and , are
clear delimiters). Not a big deal either way though.
Yeah, just an artifact of how I copied some other struct and kept
dropping flags out of the middle of the parens. Fixed.
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[Mesa-dev] [PATCH] glsl: Add a lowering pass to turn complicated UBO references to vector loads.
v2: Reduce the impenetrable code in emit_ubo_loads() by 23 lines by keeping
the ir_variable as the variable part of the offset from handle_rvalue(),
and track the constant offsets from that with a plain old integer value,
avoiding a bunch of temporary variables in the array and struct handling.
Also, fix file description doxygen.
---
src/glsl/Makefile.sources|1 +
src/glsl/ir_optimization.h |1 +
src/glsl/lower_ubo_reference.cpp | 313 ++
3 files changed, 315 insertions(+)
create mode 100644 src/glsl/lower_ubo_reference.cpp
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index f2743f7..765f06a 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -66,6 +66,7 @@ LIBGLSL_CXX_FILES = \
$(GLSL_SRCDIR)/lower_vec_index_to_swizzle.cpp \
$(GLSL_SRCDIR)/lower_vector.cpp \
$(GLSL_SRCDIR)/lower_output_reads.cpp \
+ $(GLSL_SRCDIR)/lower_ubo_reference.cpp \
$(GLSL_SRCDIR)/opt_algebraic.cpp \
$(GLSL_SRCDIR)/opt_array_splitting.cpp \
$(GLSL_SRCDIR)/opt_constant_folding.cpp \
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index c435d77..2220d51 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -74,6 +74,7 @@ bool lower_variable_index_to_cond_assign(exec_list
*instructions,
bool lower_quadop_vector(exec_list *instructions, bool dont_lower_swz);
bool lower_clip_distance(exec_list *instructions);
void lower_output_reads(exec_list *instructions);
+void lower_ubo_reference(struct gl_shader *shader, exec_list *instructions);
bool optimize_redundant_jumps(exec_list *instructions);
bool optimize_split_arrays(exec_list *instructions, bool linked);
diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
new file mode 100644
index 000..f930da5
--- /dev/null
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -0,0 +1,313 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file lower_ubo_reference.cpp
+ *
+ * IR lower pass to replace dereferences of variables in a uniform
+ * buffer object with usage of ir_binop_ubo_load expressions, each of
+ * which can read data up to the size of a vec4.
+ *
+ * This relieves drivers of the responsibility to deal with tricky UBO
+ * layout issues like std140 structures and row_major matrices on
+ * their own.
+ */
+
+#include ir.h
+#include ir_builder.h
+#include ir_rvalue_visitor.h
+#include main/macros.h
+
+using namespace ir_builder;
+
+namespace {
+class lower_ubo_reference_visitor : public ir_rvalue_enter_visitor {
+public:
+ lower_ubo_reference_visitor(struct gl_shader *shader)
+ : shader(shader)
+ {
+ }
+
+ void handle_rvalue(ir_rvalue **rvalue);
+ void emit_ubo_loads(ir_dereference *deref, ir_variable *base_offset,
+ unsigned int deref_offset);
+ ir_expression *ubo_load(const struct glsl_type *type,
+ ir_rvalue *offset);
+
+ void *mem_ctx;
+ struct gl_shader *shader;
+ struct gl_uniform_buffer_variable *ubo_var;
+ unsigned uniform_block;
+ bool progress;
+};
+
+static inline unsigned int
+align(unsigned int a, unsigned int align)
+{
+ return (a + align - 1) / align * align;
+}
+
+void
+lower_ubo_reference_visitor::handle_rvalue(ir_rvalue **rvalue)
+{
+ if (!*rvalue)
+ return;
+
+ ir_dereference *deref = (*rvalue)-as_dereference();
+ if (!deref)
+ return;
+
+ ir_variable *var = deref-variable_referenced();
+ if (!var || var-uniform_block == -1)
+ return;
+
+ mem_ctx = ralloc_parent(*rvalue);
+ uniform_block = var-uniform_block;
+ struct gl_uniform_block *block = shader-UniformBlocks[uniform_block];
+ this-ubo_var = block-Uniforms[var-location];
+ ir_rvalue *offset = new(mem_ctx) ir_constant(0u);
+ unsigned const_offset = 0;
+
Re: [Mesa-dev] [PATCH 19/22] i965/vs: Communicate the pull constant block read parameters through src_regs.
Kenneth Graunke kenn...@whitecape.org writes: On 07/31/2012 03:01 PM, Eric Anholt wrote: Similar to the previous commit for the fragment shader. --- src/mesa/drivers/dri/i965/brw_vec4.h |3 ++- src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 19 --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |5 +++-- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 920d703..deac55d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -476,7 +476,8 @@ public: struct brw_reg index); void generate_pull_constant_load(vec4_instruction *inst, struct brw_reg dst, -struct brw_reg index); +struct brw_reg index, +struct brw_reg offset); Commit message says through src_regs. These are brw_regs. Other than that, this looks fine. Reviewed-by: Kenneth Graunke kenn...@whitecape.org Yeah, we were already communicating offset through a src_reg as src0 of VS_OPCODE_PULL_CONSTANT, it's the introduction of the surface index as a src_reg that changed here. Too much copy and paste. pgpNn558O0cZp.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 10/15] intel: Support mapping multisample miptrees (v2)
Chad Versace chad.vers...@linux.intel.com writes:
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
v2:
- Move the introduction of
intel_mipmap_tree::singlesample_{width0,height0} to this patch, per
Anholt.
- Replace relations `mt-num_samples == 0` and `mt-num_samples 0`
with `= 1` and ` 0`, per Anholt.
- Don't downsample unnecessarily, found by Anholt.
CC: Eric Anholt e...@anholt.net
CC: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 115
+++--
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 18
2 files changed, 127 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 23d84c0..6ecb48f 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+ if (!mt-singlesample_mt) {
+ map-singlesample_mt_is_tmp = true;
+ mt-need_downsample = true;
Move this mt-need_downsample flag setup to after you've successfully
alloced?
+ mt-singlesample_mt =
+ intel_miptree_create_for_renderbuffer(intel,
+ mt-format,
+ mt-singlesample_width0,
+ mt-singlesample_height0,
+ 0 /*num_samples*/);
+ if (!mt-singlesample_mt) {
+ mt-need_downsample = false;
+ goto fail;
+ }
+ }
+
+ if (mode GL_MAP_INVALIDATE_RANGE_BIT)
+ mt-need_downsample = false;
+
+ intel_miptree_downsample(intel, mt);
I don't think you can clear need_downsample for
GL_MAP_INVALIDATE_RANGE_BIT, because the GL_MAP_WRITE_BIT case in the
unmap (implied by INVALIDATE_RANGE) will upsample the whole singlesample
buffer back, not just the mapped subset. Dropping the INVALIDATE_RANGE
gets the series up to this patch my r-b.
+static void
+intel_miptree_unmap_multisample(struct intel_context *intel,
+struct intel_mipmap_tree *mt,
+unsigned int level,
+unsigned int slice)
+{
+ struct intel_miptree_map *map = mt-level[level].slice[slice].map;
+
+ assert(mt-num_samples 1);
+
+ if (!map)
+ return;
+
+ intel_miptree_unmap_singlesample(intel, mt-singlesample_mt, level,
slice);
+
+ mt-need_downsample = false;
+ if (map-mode GL_MAP_WRITE_BIT)
+ intel_miptree_upsample(intel, mt);
+
+ if (map-singlesample_mt_is_tmp)
+ intel_miptree_release(mt-singlesample_mt);
+
+ intel_miptree_release_map(mt, level, slice);
+}
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Re: [Mesa-dev] [PATCH 12/15] intel: Refactor creation of DRI2 configs
Chad Versace chad.vers...@linux.intel.com writes: DRI2 configs were constructed in intelInitScreen2. That function already does too much, so move verbatim the code for creating configs to a new function, intel_screen_make_configs. CC: Eric Anholt e...@anholt.net Reviewed-by: Paul Berry stereotype...@gmail.com Signed-off-by: Chad Versace chad.vers...@linux.intel.com I haven't done a line-by-line check on verbatimness, but I trust it :) Reviewed-by: Eric Anholt e...@anholt.net pgpaK3JI85SmB.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 13/15] dri: Simplify use of driConcatConfigs
Chad Versace chad.vers...@linux.intel.com writes: If either argument to driConcatConfigs(a, b) is null or the empty list, then simply return the other argument as the resultant list. All callers were accomplishing that same behavior anyway. And each caller accopmplished it with the same pattern. So this patch moves that external pattern into the function. CC: Ian Romanick i...@freedesktop.org Reviewed-by: e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com I was going to say reviewed-by on the last patchset with this change. pgplaoPWzu610.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 14/15] intel: Clarify intel_screen_make_configs
Chad Versace chad.vers...@linux.intel.com writes:
This function felt sloppy, so this patch cleans it up a little bit.
- Rename `color` to `i`. It is not a color value, only an iterator int.
I'm meh on this change.
- Move `depth_bits[0] = 0` into the non-accum loop because that is where
it used. The accum loop later overwrites depth_bits[0].
This makes sense -- move it next to the place that sets up the rest of
the array.
- Redefine `msaa_samples_array` as static const because it is never
modified.
Maybe instead, singlesample_samples[] = {0} and multisample_samples[] =
{4, 8}? The array math in the next patch was not pretty.
Feel free to ignore me on this patch.
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Re: [Mesa-dev] [PATCH 08/15] intel: Refactor intel_miptree_map/unmap
Chad Versace chad.vers...@linux.intel.com writes: Move the body of intel_miptree_map into a new function, intel_miptree_map_singlesample. Now intel_miptree_map dispatches to the new function. A future commit adds a multisample variant. Ditto for intel_miptree_unmap. CC: Paul Berry stereotype...@gmail.com CC: Eric Anholt e...@anholt.net Signed-off-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 67 +++--- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index b424e4d..2a00c78 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c + assert(mt-num_samples == 0); = 1 + assert(mt-num_samples == 0); = 1 Other than that, patches up to this one are: Reviewed-by: Eric Anholt e...@anholt.net pgpIfbZo23FdG.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 15/15] intel: Advertise multisample DRI2 configs on gen = 6
Chad Versace chad.vers...@linux.intel.com writes: + /* Generate multisample configs. +* +* This loop breaks early, and hence is a no-op, on gen 6. +* +* Multisample configs must follow the singlesample configs in order to +* work around an X server bug present in 1.12. The X server chooses to +* associate the first listed RGBA888-Z24S8 config, regardless of its +* sample count, with the 32-bit depth visual used for compositing. +* +* Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are +* supported. Singlebuffer configs are not supported because that would +* require that rendering be eventually written to the singlesample buffer +* even if DRI2Flush is never called; yet we downsample to the singlesample +* buffer only on DRI2Flush. GLX_SWAP_COPY_OML is not supported because we +* have no tests for its interaction with MSAA. +*/ We actually need to remove our claiming of GLX_SWAP_COPY_OML in general, because pageflipping means that we don't actually support SWAP_COPY. We only do UNDEFINED. I'd say instead singlebuffer configs are not supported because nobody wants them. I think all you need is (pessimistically) intel_downsample_for_dri2_flush in intel_flush_front() to make front buffer rendering actually work, and it's a problem that exists even in a doublebuffer config. I think this concludes my review. Great work! I'm excited to see this finally land. pgpnRDmNu36bc.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] egl: remove redundant PFNEGLQUERYSTREAMTIMEKHRPROC typedef
From: Brian Paul bri...@vmware.com This typedef is present earlier in the header and isn't part of the EGL_KHR_stream_cross_process_fd extension. Looks like a Khronos glitch. --- include/EGL/eglext.h |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h index 815859d..e96c3a4 100644 --- a/include/EGL/eglext.h +++ b/include/EGL/eglext.h @@ -451,7 +451,6 @@ typedef int EGLNativeFileDescriptorKHR; EGLAPI EGLNativeFileDescriptorKHR EGLAPIENTRY eglGetStreamFileDescriptorKHR(EGLDisplay dpy, EGLStreamKHR stream); EGLAPI EGLStreamKHR EGLAPIENTRY eglCreateStreamFromFileDescriptorKHR(EGLDisplay dpy, EGLNativeFileDescriptorKHR file_descriptor); #endif /* EGL_EGLEXT_PROTOTYPES */ -typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYSTREAMTIMEKHRPROC)(EGLDisplay dpy, EGLStreamKHR stream, EGLenum attribute, EGLTimeKHR *value); typedef EGLNativeFileDescriptorKHR (EGLAPIENTRYP PFNEGLGETSTREAMFILEDESCRIPTORKHRPROC)(EGLDisplay dpy, EGLStreamKHR stream); typedef EGLStreamKHR (EGLAPIENTRYP PFNEGLCREATESTREAMFROMFILEDESCRIPTORKHRPROC)(EGLDisplay dpy, EGLNativeFileDescriptorKHR file_descriptor); #endif -- 1.7.4.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/2] i965: Back-port GPU hang workarounds (bug 50271)
On 08/05/2012 08:36 AM, Paul Berry wrote: Just looking for a quick patch review to make sure I've backported these patches to 8.0 correctly (and also confirmation that this backport is a good idea). These patches are intended to apply to the 8.0 branch. The issue is that on Gen6 and Gen7, images rendered to depth and stencil buffers must be aligned to a multiple of 8 pixels, otherwise certain rendering operations produce a GPU hang. Unfortunately, due to the layout of miptrees (and the fact that we render to depth and stencil miptrees using coordinate offsets), it would take a lot of code rework to both produce correct rendering and guarantee no GPU hangs. These patches avoid the GPU hangs by forcing the image offsets to be multiples of 8. As a result, correct rendering to depth and stencil miptrees is sacrificed but the GPU doesn't hang. The sacrifice is minor, since it only affects miptree levels that would otherwise be unaligned (in practice this is usually just the smallest miplevels), and it only matters for (a) rendering to a depth/stencil buffer that is later used as a texture, or (b) ping-ponging between miplevels while rendering, both of which are fairly rare. On the master branch, we decided that this was a worthwhile compromise. As a result of this sacrifice, this will regress the following piglit tests: fbo/fbo-depth-array (Gen6 only), spec/ARB_depth_buffer_float/fbo-clear-formats, spec/ARB_depth_texture/fbo-clear-formats, and spec/EXT_packed_depth_stencil/fbo-clear-formats. These tests currently fail on master for the same reason. For more information see: https://bugs.freedesktop.org/show_bug.cgi?id=50271 [PATCH 1/2] i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets. [PATCH 2/2] i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets. This trade-off makes sense to me. Take small amounts of misrendering in a few piglit tests doing non-real-world cases but avoid nasty GPU hangs. I hate to regress Piglit tests on stable, but it's for the best. For some reason, I thought this needed the more invasive coarse/fine-grained tile offset patches. Have you tested this to confirm it fixes the cases? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] someone regressed tinderbox
http://tinderbox.x.org/builds/2012-08-06-0020/logs/libGL/#build Making all in glx gmake[4]: Entering directory `/home/tinderbox/mesa/mesa/src/egl/drivers/glx' CC egl_glx.lo In file included from ../../../../src/egl/main/egltypedefs.h:37, from ../../../../src/egl/main/eglconfig.h:37, from egl_glx.c:44: ../../../../include/EGL/eglext.h:454: error: redefinition of typedef 'PFNEGLQUERYSTREAMTIMEKHRPROC' ../../../../include/EGL/eglext.h:407: note: previous declaration of 'PFNEGLQUERYSTREAMTIMEKHRPROC' was here gmake[4]: Leaving directory `/home/tinderbox/mesa/mesa/src/egl/drivers/glx' Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/2] i965: Back-port GPU hang workarounds (bug 50271)
On 6 August 2012 21:20, Kenneth Graunke kenn...@whitecape.org wrote: On 08/05/2012 08:36 AM, Paul Berry wrote: Just looking for a quick patch review to make sure I've backported these patches to 8.0 correctly (and also confirmation that this backport is a good idea). These patches are intended to apply to the 8.0 branch. The issue is that on Gen6 and Gen7, images rendered to depth and stencil buffers must be aligned to a multiple of 8 pixels, otherwise certain rendering operations produce a GPU hang. Unfortunately, due to the layout of miptrees (and the fact that we render to depth and stencil miptrees using coordinate offsets), it would take a lot of code rework to both produce correct rendering and guarantee no GPU hangs. These patches avoid the GPU hangs by forcing the image offsets to be multiples of 8. As a result, correct rendering to depth and stencil miptrees is sacrificed but the GPU doesn't hang. The sacrifice is minor, since it only affects miptree levels that would otherwise be unaligned (in practice this is usually just the smallest miplevels), and it only matters for (a) rendering to a depth/stencil buffer that is later used as a texture, or (b) ping-ponging between miplevels while rendering, both of which are fairly rare. On the master branch, we decided that this was a worthwhile compromise. As a result of this sacrifice, this will regress the following piglit tests: fbo/fbo-depth-array (Gen6 only), spec/ARB_depth_buffer_float/fbo-clear-formats, spec/ARB_depth_texture/fbo-clear-formats, and spec/EXT_packed_depth_stencil/fbo-clear-formats. These tests currently fail on master for the same reason. For more information see: https://bugs.freedesktop.org/show_bug.cgi?id=50271 [PATCH 1/2] i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets. [PATCH 2/2] i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets. This trade-off makes sense to me. Take small amounts of misrendering in a few piglit tests doing non-real-world cases but avoid nasty GPU hangs. I hate to regress Piglit tests on stable, but it's for the best. Ok, cool. Thanks for the confirmation that this is a good idea. I hate doing cherry-picks to stable that have merge conflicts anyhow, and in this case the fact that it would cause known regressions made it seem even less certain--but I couldn't think of a better alternative. I'll plan on pushing it to stable tomorrow. For some reason, I thought this needed the more invasive coarse/fine-grained tile offset patches. Have you tested this to confirm it fixes the cases? Yes, I tested it on both Sandy Bridge and Ivy Bridge. (Believe it or not, I brought both with me to SIGGRAPH :)) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
