CVS commit: src/sys
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 03:55:47 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: files.marvell mvsoc.c
src/sys/dev/marvell: files.armada if_mvxpe.c if_mvxpereg.h
if_mvxpevar.h
Added Files:
src/sys/dev/marvell: mvxpbm.c mvxpbmvar.h
Log Message:
separate buffer management codes 'mvxpbm.c' from if_mvxpe.c.
the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in
ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet
implemented, so all devices use the S/W management mode at this time.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/marvell/files.marvell
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.1 -r1.2 src/sys/dev/marvell/files.armada \
src/sys/dev/marvell/if_mvxpe.c src/sys/dev/marvell/if_mvxpereg.h \
src/sys/dev/marvell/if_mvxpevar.h
cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/mvxpbm.c \
src/sys/dev/marvell/mvxpbmvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/files.marvell
diff -u src/sys/arch/arm/marvell/files.marvell:1.15 src/sys/arch/arm/marvell/files.marvell:1.16
--- src/sys/arch/arm/marvell/files.marvell:1.15 Wed Jun 3 03:34:38 2015
+++ src/sys/arch/arm/marvell/files.marvell Wed Jun 3 03:55:47 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.15 2015/06/03 03:34:38 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.16 2015/06/03 03:55:47 hsuenaga Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -58,6 +58,9 @@ attach mvsata at mvsoc with mvsata_mbus
# Gigabit Ethernet Controller Interface
attach mvgbec at mvsoc with mvgbec_mbus
+# ARMADA XP Buffer Manager
+attach mvxpbm at mvsoc with mvxpbm_mbus
+
# ARMADA XP Gigabit Ethernet Controller Interface
attach mvxpe at mvsoc with mvxpe_mbus
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.21 src/sys/arch/arm/marvell/mvsoc.c:1.22
--- src/sys/arch/arm/marvell/mvsoc.c:1.21 Wed Jun 3 03:04:21 2015
+++ src/sys/arch/arm/marvell/mvsoc.c Wed Jun 3 03:55:47 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $);
#include opt_cputypes.h
#include opt_mvsoc.h
@@ -685,6 +685,7 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78130), mvsdio, 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
{ ARMADAXP(MV78130), mvxpe, 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
#if NMVXPE 0
+{ ARMADAXP(MV78130), mvxpbm, 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78130), mvxpe, 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78130), mvxpe, 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
#else
@@ -716,6 +717,7 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78160), mvspi, 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78160), mvsdio, 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE 0
+{ ARMADAXP(MV78160), mvxpbm, 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78160), mvxpe, 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78160), mvxpe, 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78160), mvxpe, 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -751,6 +753,7 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78230), mvspi, 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78230), mvsdio, 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE 0
+{ ARMADAXP(MV78230), mvxpbm, 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78230), mvxpe, 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78230), mvxpe, 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78230), mvxpe, 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -784,6 +787,7 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78260), mvspi, 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{ ARMADAXP(MV78260), mvsdio, 0, ARMADAXP_SDIO_BASE,ARMADAXP_IRQ_SDIO },
#if NMVXPE 0
+{ ARMADAXP(MV78260), mvxpbm, 0, MVA_OFFSET_DEFAULT,IRQ_DEFAULT },
{ ARMADAXP(MV78260), mvxpe, 0, ARMADAXP_GBE0_BASE,ARMADAXP_IRQ_GBE0_TH_RXTX },
{ ARMADAXP(MV78260), mvxpe, 1, ARMADAXP_GBE1_BASE,ARMADAXP_IRQ_GBE1_TH_RXTX },
{ ARMADAXP(MV78260), mvxpe, 2, ARMADAXP_GBE2_BASE,ARMADAXP_IRQ_GBE2_TH_RXTX },
@@ -820,6 +824,7 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78460), mvspi, 0, ARMADAXP_SPI_BASE,ARMADAXP_IRQ_SPI },
{
CVS commit: src/sys
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 03:55:47 UTC 2015 Modified Files: src/sys/arch/arm/marvell: files.marvell mvsoc.c src/sys/dev/marvell: files.armada if_mvxpe.c if_mvxpereg.h if_mvxpevar.h Added Files: src/sys/dev/marvell: mvxpbm.c mvxpbmvar.h Log Message: separate buffer management codes 'mvxpbm.c' from if_mvxpe.c. the buffer management(ex. fill the rx descriptors/buffers) is done by H/W in ARMADA XP/380, and is done by S/W in ARMADA 370. the H/W BM support is not yet implemented, so all devices use the S/W management mode at this time. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/marvell/files.marvell cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/marvell/mvsoc.c cvs rdiff -u -r1.1 -r1.2 src/sys/dev/marvell/files.armada \ src/sys/dev/marvell/if_mvxpe.c src/sys/dev/marvell/if_mvxpereg.h \ src/sys/dev/marvell/if_mvxpevar.h cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/mvxpbm.c \ src/sys/dev/marvell/mvxpbmvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/dev/marvell
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 04:00:06 UTC 2015 Modified Files: src/sys/dev/marvell: marvellreg.h Log Message: reduce magic numbers. SDRAM address space attribute register has cache coherency control bits. this bit is important for AURORA_IO_CACHE_COHERENCY. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/dev/marvell/marvellreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/dev/marvell/marvellreg.h diff -u src/sys/dev/marvell/marvellreg.h:1.8 src/sys/dev/marvell/marvellreg.h:1.9 --- src/sys/dev/marvell/marvellreg.h:1.8 Sat Mar 15 10:40:39 2014 +++ src/sys/dev/marvell/marvellreg.h Wed Jun 3 04:00:06 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: marvellreg.h,v 1.8 2014/03/15 10:40:39 kiyohara Exp $ */ +/* $NetBSD: marvellreg.h,v 1.9 2015/06/03 04:00:06 hsuenaga Exp $ */ /* * Copyright (c) 2009 KIYOHARA Takashi * All rights reserved. @@ -73,11 +73,13 @@ #define MARVELL_DISCOVERY_REVB 0x20 #define MARVELL_ATTR_MASK 0xff +#define MARVELL_ATTR_SDRAM_CFU_SHARE 0x10 /* shared and snoop enabled.*/ +#define MARVELL_ATTR_SDRAM_CFU_L2_DEP 0x20 /* enable L2 deposit */ #ifdef AURORA_IO_CACHE_COHERENCY -#define MARVELL_ATTR_SDRAM_CS0 0x1e -#define MARVELL_ATTR_SDRAM_CS1 0x1d -#define MARVELL_ATTR_SDRAM_CS2 0x1b -#define MARVELL_ATTR_SDRAM_CS3 0x17 +#define MARVELL_ATTR_SDRAM_CS0 (0x0e | MARVELL_ATTR_SDRAM_CFU_SHARE) +#define MARVELL_ATTR_SDRAM_CS1 (0x0d | MARVELL_ATTR_SDRAM_CFU_SHARE) +#define MARVELL_ATTR_SDRAM_CS2 (0x0b | MARVELL_ATTR_SDRAM_CFU_SHARE) +#define MARVELL_ATTR_SDRAM_CS3 (0x07 | MARVELL_ATTR_SDRAM_CFU_SHARE) #else #define MARVELL_ATTR_SDRAM_CS0 0x0e #define MARVELL_ATTR_SDRAM_CS1 0x0d
CVS commit: src/sys/dev/marvell
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 04:00:06 UTC 2015 Modified Files: src/sys/dev/marvell: marvellreg.h Log Message: reduce magic numbers. SDRAM address space attribute register has cache coherency control bits. this bit is important for AURORA_IO_CACHE_COHERENCY. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/dev/marvell/marvellreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 04:20:02 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: files.marvell mvsoc.c mvsocvar.h
src/sys/dev/marvell: files.armada
Added Files:
src/sys/dev/marvell: mvxpsec.c mvxpsecreg.h mvxpsecvar.h
Log Message:
add new cryptographic accelerator driver 'mvxpsec.'
this driver controls CESA unit as same as mvcesa, but uses DMA engines and
does CBC operations, HMAC operations by hardware. about 2 kbytes of data
are processed at one. supported algorithms are:
- DES-CBC, 3DES-CBC, AES-CBC
- HMAC-SHA1, HMAC-MD5
non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration
engine. mvcesa is still useful to implement such algorithms as combination of
accelerated block cipher and software chaining.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/marvell/files.marvell
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/mvsocvar.h
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/marvell/files.armada
cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/mvxpsec.c \
src/sys/dev/marvell/mvxpsecreg.h src/sys/dev/marvell/mvxpsecvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/files.marvell
diff -u src/sys/arch/arm/marvell/files.marvell:1.16 src/sys/arch/arm/marvell/files.marvell:1.17
--- src/sys/arch/arm/marvell/files.marvell:1.16 Wed Jun 3 03:55:47 2015
+++ src/sys/arch/arm/marvell/files.marvell Wed Jun 3 04:20:02 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.16 2015/06/03 03:55:47 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.17 2015/06/03 04:20:02 hsuenaga Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -70,6 +70,9 @@ attach ehci at mvsoc with mvusb_mbus
# Cryptographic Engines and Security Accelerator
attach mvcesa at mvsoc with mvcesa_mbus
+# ARMADA XP Cryptographic Engines and Security Accelerator
+attach mvxpsec at mvsoc with mvxpsec_mbus
+
# TWSI Two-Wire Serial Interface
attach gttwsi at mvsoc with gttwsi_mbus
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.22 src/sys/arch/arm/marvell/mvsoc.c:1.23
--- src/sys/arch/arm/marvell/mvsoc.c:1.22 Wed Jun 3 03:55:47 2015
+++ src/sys/arch/arm/marvell/mvsoc.c Wed Jun 3 04:20:02 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.23 2015/06/03 04:20:02 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,12 +26,13 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.22 2015/06/03 03:55:47 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.23 2015/06/03 04:20:02 hsuenaga Exp $);
#include opt_cputypes.h
#include opt_mvsoc.h
#ifdef ARMADAXP
#include mvxpe.h
+#include mvxpsec.h
#endif
#include sys/param.h
@@ -274,6 +275,10 @@ static struct {
ARMADAXP_ATTR_PEX3_MEM, ARMADAXP_UNITID_PEX3 },
{ ARMADAXP_TAG_PEX3_IO,
ARMADAXP_ATTR_PEX3_IO, ARMADAXP_UNITID_PEX3 },
+ { ARMADAXP_TAG_CRYPT0,
+ ARMADAXP_ATTR_CRYPT0_NOSWAP, ARMADAXP_UNITID_CRYPT },
+ { ARMADAXP_TAG_CRYPT1,
+ ARMADAXP_ATTR_CRYPT1_NOSWAP, ARMADAXP_UNITID_CRYPT },
#endif
};
@@ -692,8 +697,13 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78130), mvgbec, 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78130), mvgbec, 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC 0
+{ ARMADAXP(MV78130), mvxpsec, 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+{ ARMADAXP(MV78130), mvxpsec, 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78130), mvcesa, 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78130), mvcesa, 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78160), mvsoctmr,0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78160), com,0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -728,8 +738,13 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78160), mvgbec, 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78160), mvgbec, 3, ARMADAXP_GBE3_BASE,IRQ_DEFAULT },
#endif
+#if NMVXPSEC 0
+{ ARMADAXP(MV78160), mvxpsec, 0, ARMADAXP_XPSEC0_BASE,ARMADAXP_IRQ_CESA0 },
+{ ARMADAXP(MV78160), mvxpsec, 1, ARMADAXP_XPSEC1_BASE,ARMADAXP_IRQ_CESA1 },
+#else
{ ARMADAXP(MV78160), mvcesa, 0, ARMADAXP_CESA0_BASE,ARMADAXP_IRQ_CESA0 },
{ ARMADAXP(MV78160), mvcesa, 1, ARMADAXP_CESA1_BASE,ARMADAXP_IRQ_CESA1 },
+#endif
{ ARMADAXP(MV78230), mvsoctmr,0,MVSOC_TMR_BASE, ARMADAXP_IRQ_TIMER0 },
{ ARMADAXP(MV78230), com,0, MVSOC_COM0_BASE, ARMADAXP_IRQ_UART0 },
@@ -762,8 +777,13 @@ static const struct mvsoc_periph {
{ ARMADAXP(MV78230), mvgbec, 1, ARMADAXP_GBE1_BASE,IRQ_DEFAULT },
{ ARMADAXP(MV78230), mvgbec, 2, ARMADAXP_GBE2_BASE,IRQ_DEFAULT },
CVS commit: src/sys
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 04:20:02 UTC 2015 Modified Files: src/sys/arch/arm/marvell: files.marvell mvsoc.c mvsocvar.h src/sys/dev/marvell: files.armada Added Files: src/sys/dev/marvell: mvxpsec.c mvxpsecreg.h mvxpsecvar.h Log Message: add new cryptographic accelerator driver 'mvxpsec.' this driver controls CESA unit as same as mvcesa, but uses DMA engines and does CBC operations, HMAC operations by hardware. about 2 kbytes of data are processed at one. supported algorithms are: - DES-CBC, 3DES-CBC, AES-CBC - HMAC-SHA1, HMAC-MD5 non-CBC algorithm such as AES-GCM is not supported by CESA's acceleration engine. mvcesa is still useful to implement such algorithms as combination of accelerated block cipher and software chaining. To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/marvell/files.marvell cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/marvell/mvsoc.c cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/mvsocvar.h cvs rdiff -u -r1.2 -r1.3 src/sys/dev/marvell/files.armada cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/mvxpsec.c \ src/sys/dev/marvell/mvxpsecreg.h src/sys/dev/marvell/mvxpsecvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 02:30:11 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: initialize sdcache operations for PJ4B. otherwise the kernel crashes without 'options L2CACHE_ENABLE.' To generate a diff of this commit: cvs rdiff -u -r1.154 -r1.155 src/sys/arch/arm/arm/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */ @@ -134,8 +209,37 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #define ARMADAXP_IRQ_PEX2 99 /* PCIe Port2 INTA/B/C/D */ #define ARMADAXP_IRQ_PEX3 103 /* PCIe Port3 INTA/B/C/D */ +#define ARMADAXP_IRQ_SOURCES 116 -#define ARMADAXP_MLMB_NWINDOW 19 +/* + * IRQ mappings for Error Interrupt Cause(ARMADAXP_MLMB_MPIC_ERR_CAUSE) + */ +#define ARMADAXP_IRQ_ERROR_BASE 120 +#define ARMADAXP_IRQ_ERROR_SOURCES 32 +#define ARMADAXP_IRQ_ERROR(x) (120 + (x)) +#define ARMADAXP_IRQ_ERROR_BIT(irq) (1 irq) + +#define ARMADAXP_IRQ_CESA0_ERR ARMADAXP_IRQ_ERROR(0) +#define ARMADAXP_IRQ_DEVBUS_ERR ARMADAXP_IRQ_ERROR(1) +#define ARMADAXP_IRQ_IDMA_ERR ARMADAXP_IRQ_ERROR(2) +#define ARMADAXP_IRQ_XOR1_ERR ARMADAXP_IRQ_ERROR(3) +#define ARMADAXP_IRQ_PEX0_ERR ARMADAXP_IRQ_ERROR(4) +#define ARMADAXP_IRQ_PEX1_ERR ARMADAXP_IRQ_ERROR(5) +#define ARMADAXP_IRQ_GBE_ERR ARMADAXP_IRQ_ERROR(6) +#define ARMADAXP_IRQ_CESA1_ERR ARMADAXP_IRQ_ERROR(7) +#define ARMADAXP_IRQ_USB_ERR ARMADAXP_IRQ_ERROR(8) +#define ARMADAXP_IRQ_DRAM_ERR ARMADAXP_IRQ_ERROR(9) +#define ARMADAXP_IRQ_XOR0_ERR ARMADAXP_IRQ_ERROR(10) +#define ARMADAXP_IRQ_BM_ERR ARMADAXP_IRQ_ERROR(12) +#define ARMADAXP_IRQ_CIB_ERR ARMADAXP_IRQ_ERROR(13) +#define ARMADAXP_IRQ_PEX2_ERR ARMADAXP_IRQ_ERROR(15) +#define ARMADAXP_IRQ_PEX3_ERR ARMADAXP_IRQ_ERROR(16) +#define ARMADAXP_IRQ_SATA0_ERR ARMADAXP_IRQ_ERROR(17) +#define ARMADAXP_IRQ_SATA1_ERR ARMADAXP_IRQ_ERROR(18) +#define ARMADAXP_IRQ_TDM_ERR ARMADAXP_IRQ_ERROR(20) +#define ARMADAXP_IRQ_NAND_ERR ARMADAXP_IRQ_ERROR(21) + +#define ARMADAXP_MLMB_NWINDOW 20 #define ARMADAXP_MLMB_NREMAP 8 /* @@ -207,7 +311,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #define ARMADAXP_MLMB_MPIC_IIACK 0xb4 #define ARMADAXP_MLMB_MPIC_ISM 0xb8 #define ARMADAXP_MLMB_MPIC_ICM 0xbc -#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xec0 +#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xc0 /* Multiprocessor Interrupt Controller Shifts */ #define MPIC_CTP_SHIFT 28 /* Global priority level field */ @@ -252,15 +356,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #define L2_CTRL_ENABLE (1 0) /* ARMADAXP_L2_AUX_CTRL */ -#define L2_AUX_WBWT_MODE_MASK (3 0) -#define L2_AUX_WBWT_MODE_BY_ATTR (0 0) -#define L2_AUX_WBWT_MODE_WB (1 0) -#define L2_AUX_WBWT_MODE_WT (2 0) -#define L2_AUX_FLUSH_ON_POWERDOWN (1 3) -#define L2_AUX_ECC_ENABLE (1 20) -#define L2_AUX_PARITY_ENABLE (1 21) -#define L2_AUX_INVAL_UCE (1 22) -#define L2_AUX_FORCE_WA (1 23) +#define L2_AUX_WBWT_MODE_MASK __BITS(1,0) +#define L2_AUX_WBWT_MODE_BY_ATTR (0 0) +#define L2_AUX_WBWT_MODE_WB (1 0) +#define L2_AUX_WBWT_MODE_WT (2 0) +#define L2_AUX_FLUSH_ON_POWERDOWN __BIT(3) +#define L2_AUX_ECC_ENABLE __BIT(20) +#define L2_AUX_PARITY_ENABLE __BIT(21) +#define L2_AUX_INVAL_UCE __BIT(22) +#define L2_AUX_FORCE_WA_MASK __BITS(24,23) +#define L2_AUX_FORCE_WA_BY_ATTR (0 23) +#define L2_AUX_FORCE_WA_DISABLE (1 23) +#define L2_AUX_FORCE_WA_ENABLE (2 23) +#define L2_AUX_FORCE_WA_ENABLE_DT (3 23) #define L2_AUX_REP_STRAT_MASK (3 27) #define L2_AUX_REP_STRAT_LFSR (1 27) #define L2_AUX_REP_STRAT_PLRU (2 27) @@ -325,6 +433,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */ #define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */ +#define ARMADAXP_XPSEC0_BASE (UNITID2PHYS(CRYPT) + 0x) /* 0x9 */ +#define ARMADAXP_XPSEC1_BASE (UNITID2PHYS(CRYPT) + 0x2000) /* 0x92000 */ + /* * Serial-ATA Host Controller (SATAHC) Registers */ @@ -338,7 +449,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI /* * NAND Flash Controller Version 2.0 Registers */ -#define ARMADAXP_NAND_BASE 0xc +#define ARMADAXP_NAND_BASE (UINTID2PHYS(NAND)) /* * PnC Unit Registers Index: src/sys/arch/arm/marvell/armadaxpvar.h diff -u src/sys/arch/arm/marvell/armadaxpvar.h:1.1 src/sys/arch/arm/marvell/armadaxpvar.h:1.2 --- src/sys/arch/arm/marvell/armadaxpvar.h:1.1 Wed Apr 15 10:40:36 2015 +++ src/sys/arch/arm/marvell/armadaxpvar.h Wed Jun 3 02:53:19 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: armadaxpvar.h,v 1.1 2015/04/15 10:40:36 hsuenaga Exp $ */ +/* $NetBSD: armadaxpvar.h,v 1.2 2015/06/03 02:53:19 hsuenaga Exp $ */ /* * Copyright (c) 2015 SUENAGA Hiroki * All rights reserved. @@ -26,6 +26,7 @@ */ #ifndef _ARMDAXPVAR_H_ #define _ARMDAXPVAR_H_ +#include arm/marvell/mvsocvar.h #include machine/bus_defs.h /* device initalization */ @@ -40,5 +41,8 @@ extern void armadaxp_sdcache_inv_range(v extern void armadaxp_sdcache_wb_range(vaddr_t, paddr_t, psize_t); extern void armadaxp_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); -#endif /* _ARMDAXPVAR_H_ */ +/* mbus initialization */ +extern int armadaxp_init_mbus(void); +extern int armadaxp_attr_dump(struct mvsoc_softc *, uint32_t, uint32_t); +#endif /* _ARMDAXPVAR_H_ */
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 02:53:19 UTC 2015 Modified Files: src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h armadaxpvar.h Log Message: add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function. some versions of u-boot initializes the address decoder incorrectly(probably these values are come from Kirkwood SoC or older.) the codes generates SoC's default address spaces and some modifications for NetBSD's assumption. add error interrupt definitions, interrupt name strings for 'vmstat -e', verbose output of Mbus settings for such low-level debugging of SoC. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/marvell/armadaxp.c cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/marvell/armadaxpreg.h cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/marvell/armadaxpvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 03:04:21 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: mvsoc.c mvsoc_intr.h mvsocreg.h mvsocvar.h
Log Message:
dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled.
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/marvell/mvsoc.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/marvell/mvsoc_intr.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/marvell/mvsocreg.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/marvell/mvsocvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.20 src/sys/arch/arm/marvell/mvsoc.c:1.21
--- src/sys/arch/arm/marvell/mvsoc.c:1.20 Mon May 11 05:49:48 2015
+++ src/sys/arch/arm/marvell/mvsoc.c Wed Jun 3 03:04:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,13 +26,17 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.21 2015/06/03 03:04:21 hsuenaga Exp $);
#include opt_cputypes.h
#include opt_mvsoc.h
+#ifdef ARMADAXP
#include mvxpe.h
+#endif
#include sys/param.h
+#include sys/boot_flag.h
+#include sys/systm.h
#include sys/bus.h
#include sys/device.h
#include sys/errno.h
@@ -47,6 +51,7 @@ __KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.
#include arm/marvell/orionreg.h
#include arm/marvell/kirkwoodreg.h
#include arm/marvell/mv78xx0reg.h
+#include arm/marvell/armadaxpvar.h
#include arm/marvell/armadaxpreg.h
#include uvm/uvm.h
@@ -917,6 +922,9 @@ mvsoc_attach(device_t parent, device_t s
panic(unknown SoC: model 0x%04x, rev 0x%02x, model, rev);
tags = tagstbl[i].tags;
+ if (boothowto (AB_VERBOSE | AB_DEBUG))
+ mvsoc_target_dump(sc);
+
for (i = 0; i __arraycount(mvsoc_periphs); i++) {
if (mvsoc_periphs[i].model != model)
continue;
@@ -1247,3 +1255,43 @@ mvsoc_target_peripheral(uint32_t target,
}
return i;
}
+
+int
+mvsoc_target_dump(struct mvsoc_softc *sc)
+{
+ uint32_t reg, base, size, target, attr, enable;
+ int i, n;
+
+ for (i = 0, n = 0; i nwindow; i++) {
+ reg = read_mlmbreg(MVSOC_MLMB_WCR(i));
+ enable = reg MVSOC_MLMB_WCR_WINEN;
+ target = MVSOC_MLMB_WCR_GET_TARGET(reg);
+ attr = MVSOC_MLMB_WCR_GET_ATTR(reg);
+ size = MVSOC_MLMB_WCR_GET_SIZE(reg);
+
+ reg = read_mlmbreg(MVSOC_MLMB_WBR(i));
+ base = MVSOC_MLMB_WBR_GET_BASE(reg);
+
+ if (!enable)
+ continue;
+
+ aprint_verbose_dev(sc-sc_dev,
+ Mbus window %2d: Base 0x%08x Size 0x%08x , i, base, size);
+#ifdef ARMADAXP
+ armadaxp_attr_dump(sc, target, attr);
+#else
+ mvsoc_attr_dump(sc, target, attr);
+#endif
+ printf(\n);
+ n++;
+ }
+
+ return n;
+}
+
+int
+mvsoc_attr_dump(struct mvsoc_softc *sc, uint32_t target, uint32_t attr)
+{
+ aprint_verbose_dev(sc-sc_dev, target 0x%x(attr 0x%x), target, attr);
+ return 0;
+}
Index: src/sys/arch/arm/marvell/mvsoc_intr.h
diff -u src/sys/arch/arm/marvell/mvsoc_intr.h:1.5 src/sys/arch/arm/marvell/mvsoc_intr.h:1.6
--- src/sys/arch/arm/marvell/mvsoc_intr.h:1.5 Wed Apr 8 21:43:30 2015
+++ src/sys/arch/arm/marvell/mvsoc_intr.h Wed Jun 3 03:04:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc_intr.h,v 1.5 2015/04/08 21:43:30 matt Exp $ */
+/* $NetBSD: mvsoc_intr.h,v 1.6 2015/06/03 03:04:21 hsuenaga Exp $ */
/*
* Copyright (c) 2010 KIYOHARA Takashi
* All rights reserved.
@@ -34,6 +34,7 @@
#if defined(ARMADAXP)
#define __HAVE_PIC_SET_PRIORITY
#define __HAVE_PIC_PENDING_INTRS
+#define PIC_MAXMAXSOURCES 256
#endif
#endif
Index: src/sys/arch/arm/marvell/mvsocreg.h
diff -u src/sys/arch/arm/marvell/mvsocreg.h:1.11 src/sys/arch/arm/marvell/mvsocreg.h:1.12
--- src/sys/arch/arm/marvell/mvsocreg.h:1.11 Tue May 19 09:20:19 2015
+++ src/sys/arch/arm/marvell/mvsocreg.h Wed Jun 3 03:04:21 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsocreg.h,v 1.11 2015/05/19 09:20:19 hsuenaga Exp $ */
+/* $NetBSD: mvsocreg.h,v 1.12 2015/06/03 03:04:21 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008 KIYOHARA Takashi
* All rights reserved.
@@ -86,15 +86,23 @@
#define MVSOC_MLMB_WCR(w) ((w) 8 ? ((w) 4) + 0x0 :\
(((w) - 8) 3) + 0x90)
#define MVSOC_MLMB_WCR_WINEN (1 0)
+#define MVSOC_MLMB_WCR_SYNC (1 1) /* sync barrier */
#define MVSOC_MLMB_WCR_TARGET(t) (((t) 0xf) 4)
+#define MVSOC_MLMB_WCR_GET_TARGET(reg) (((reg) 4) 0xf)
#define MVSOC_MLMB_WCR_ATTR(a) (((a) 0xff) 8)
+#define MVSOC_MLMB_WCR_GET_ATTR(reg) (((reg) 8) 0xff)
#define MVSOC_MLMB_WCR_SIZE_MASK 0x
#define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) MVSOC_MLMB_WCR_SIZE_MASK)
+#define MVSOC_MLMB_WCR_GET_SIZE(reg) \
+(((reg) MVSOC_MLMB_WCR_SIZE_MASK) + (1 16))
#define MVSOC_MLMB_WBR(w) ((w) 8
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 03:04:21 UTC 2015 Modified Files: src/sys/arch/arm/marvell: mvsoc.c mvsoc_intr.h mvsocreg.h mvsocvar.h Log Message: dump Mbus settins on boot if AV_VERBOSE or AV_DEBUG is enabled. To generate a diff of this commit: cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/marvell/mvsoc.c cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/marvell/mvsoc_intr.h cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/marvell/mvsocreg.h cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/marvell/mvsocvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 03:34:38 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: files.marvell
Added Files:
src/sys/dev/marvell: files.armada
Log Message:
move Marvell ARMADA SoC's device driver definitions from arm/marvell
to dev/marvell.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/marvell/files.marvell
cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/files.armada
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/files.marvell
diff -u src/sys/arch/arm/marvell/files.marvell:1.14 src/sys/arch/arm/marvell/files.marvell:1.15
--- src/sys/arch/arm/marvell/files.marvell:1.14 Sun May 3 14:38:09 2015
+++ src/sys/arch/arm/marvell/files.marvell Wed Jun 3 03:34:38 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.marvell,v 1.14 2015/05/03 14:38:09 hsuenaga Exp $
+# $NetBSD: files.marvell,v 1.15 2015/06/03 03:34:38 hsuenaga Exp $
#
# Configuration info for Marvell System on Chip support
#
@@ -27,6 +27,7 @@ file arch/arm/marvell/armadaxp.c armada
# Integrated peripherals
include dev/marvell/files.discovery
+include dev/marvell/files.armada
# Timers
device mvsoctmr: sysmon_wdog
@@ -58,10 +59,7 @@ attach mvsata at mvsoc with mvsata_mbus
attach mvgbec at mvsoc with mvgbec_mbus
# ARMADA XP Gigabit Ethernet Controller Interface
-define mvxpe { [port = -1 ], [irq = -1] }
-device mvxpe: ether, ifnet, arp, mii
attach mvxpe at mvsoc with mvxpe_mbus
-file dev/marvell/if_mvxpe.c mvxpe needs-flag
# USB 2.0 Interface
attach ehci at mvsoc with mvusb_mbus
Added files:
Index: src/sys/dev/marvell/files.armada
diff -u /dev/null src/sys/dev/marvell/files.armada:1.1
--- /dev/null Wed Jun 3 03:34:38 2015
+++ src/sys/dev/marvell/files.armada Wed Jun 3 03:34:38 2015
@@ -0,0 +1,7 @@
+# $NetBSD: files.armada,v 1.1 2015/06/03 03:34:38 hsuenaga Exp $
+# Configuration info for Marvell ARMADA integrated peripherals
+
+# ARMADA XP Gigabit Ethernet Controller Interface
+define mvxpe { [port = -1 ], [irq = -1] }
+device mvxpe: ether, ifnet, arp, mii
+file dev/marvell/if_mvxpe.c mvxpe needs-flag
CVS commit: src/sys
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 03:34:38 UTC 2015 Modified Files: src/sys/arch/arm/marvell: files.marvell Added Files: src/sys/dev/marvell: files.armada Log Message: move Marvell ARMADA SoC's device driver definitions from arm/marvell to dev/marvell. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/marvell/files.marvell cvs rdiff -u -r0 -r1.1 src/sys/dev/marvell/files.armada Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 04:31:46 UTC 2015 Modified Files: src/sys/arch/evbarm/conf: ARMADAXP OPENBLOCKS_AX3 Log Message: add kernel config of if_mvxpe(new ethernet) and mvxpsec(new cryptographic). still disabled by default. I need to do more test... To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/evbarm/conf/ARMADAXP cvs rdiff -u -r1.13 -r1.14 src/sys/arch/evbarm/conf/OPENBLOCKS_AX3 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/conf
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 04:31:46 UTC 2015 Modified Files: src/sys/arch/evbarm/conf: ARMADAXP OPENBLOCKS_AX3 Log Message: add kernel config of if_mvxpe(new ethernet) and mvxpsec(new cryptographic). still disabled by default. I need to do more test... To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/evbarm/conf/ARMADAXP cvs rdiff -u -r1.13 -r1.14 src/sys/arch/evbarm/conf/OPENBLOCKS_AX3 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/evbarm/conf/ARMADAXP diff -u src/sys/arch/evbarm/conf/ARMADAXP:1.15 src/sys/arch/evbarm/conf/ARMADAXP:1.16 --- src/sys/arch/evbarm/conf/ARMADAXP:1.15 Sat Aug 30 13:45:56 2014 +++ src/sys/arch/evbarm/conf/ARMADAXP Wed Jun 3 04:31:46 2015 @@ -1,5 +1,5 @@ # -# $NetBSD: ARMADAXP,v 1.15 2014/08/30 13:45:56 kiyohara Exp $ +# $NetBSD: ARMADAXP,v 1.16 2015/06/03 04:31:46 hsuenaga Exp $ # # ARMADA XP DEV BOARD # @@ -201,9 +201,13 @@ m25p0 at spi? slave 0 # TWSI SDRAM Serial Presence Detect spdmem0 at iic? addr 0x56 -# On-chip Cryptographic Engines and Security Accelerator +# On-chip Cryptographic Engines and Security Accelerator (S/W chaining) mvcesa* at mvsoc? offset ? irq ? +# On-chip Cryptographic Engines and Security Accelerator (H/W chaining) +#mvxpsec* at mvsoc? offset ? irq ? +#options MVXPSEC_DEBUG=MVXPSEC_DEBUG_ALL + # On-chip USB 2.0 Interface ehci* at mvsoc? offset ? irq ? @@ -250,10 +254,16 @@ wd* at atabus? drive ? flags 0x sd* at atapibus? drive ? flags 0x # ATAPI disk drives uk* at atapibus? drive ? flags 0x # ATAPI unknown -# On-chip Gigabit Ethernet Controller Interface +# On-chip Gigabit Ethernet Controller Interface (backward compatible mode) mvgbec* at mvsoc? offset ? mvgbe* at mvgbec? port ? irq ? +# On-chip Gigabit Ethernet Controller Interface (counter mode) +#mvxpbm* at mvsoc? offset ? +#mvxpe* at mvsoc? irq ? +#options MVXPE_EVENT_COUNTERS +#options MVXPE_DEBUG=0 + # On-chip RTC mvsocrtc* at mvsoc? offset ? irq ? Index: src/sys/arch/evbarm/conf/OPENBLOCKS_AX3 diff -u src/sys/arch/evbarm/conf/OPENBLOCKS_AX3:1.13 src/sys/arch/evbarm/conf/OPENBLOCKS_AX3:1.14 --- src/sys/arch/evbarm/conf/OPENBLOCKS_AX3:1.13 Sat Aug 30 13:40:18 2014 +++ src/sys/arch/evbarm/conf/OPENBLOCKS_AX3 Wed Jun 3 04:31:46 2015 @@ -1,4 +1,4 @@ -# $NetBSD: OPENBLOCKS_AX3,v 1.13 2014/08/30 13:40:18 kiyohara Exp $ +# $NetBSD: OPENBLOCKS_AX3,v 1.14 2015/06/03 04:31:46 hsuenaga Exp $ # # OPENBLOCKS_AX3 -- Plat'Home. OpenBlockS AX3 kernel # @@ -182,11 +182,17 @@ options MVSOC_FIXUP_DEVID=0x7826 # On-chip Serial-ATA II Host Controller (SATAHC) mvsata* at mvsoc? offset ? irq ? -# On-chip Gigabit Ethernet Controller Interface +# On-chip Gigabit Ethernet Controller Interface (backward compatible mode) mvgbec* at mvsoc? offset ? mvgbe* at mvgbec? port ? irq ? makphy* at mii? phy ? +# On-chip Gigabit Ethernet Controller Interface (counter mode) +#mvxpbm* at mvsoc? offset ? +#mvxpe* at mvsoc? irq ? +#options MVXPE_EVENT_COUNTERS +#options MVXPE_DEBUG=0 + # On-chip USB 2.0 Interface ehci* at mvsoc? offset ? irq ? @@ -199,6 +205,10 @@ gttwsi* at mvsoc? offset ? irq ? iic* at gttwsi? s390rtc* at iic1 addr 0x30 +# On-chip Cryptographic Engines and Security Accelerator (DMA) +#mvxpsec* at mvsoc? offset ? irq ? +#options MVXPSEC_DEBUG=MVXPSEC_DEBUG_ALL + # On-chip UART Interface com* at mvsoc? offset ? irq ? options COM_16750 # : required
CVS commit: src/sys/net
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 02:17:51 UTC 2015
Modified Files:
src/sys/net: if_gif.c
Log Message:
Obtain softnet_lock before entering IP networking stack from gif software
interrupt.
To generate a diff of this commit:
cvs rdiff -u -r1.84 -r1.85 src/sys/net/if_gif.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/net/if_gif.c
diff -u src/sys/net/if_gif.c:1.84 src/sys/net/if_gif.c:1.85
--- src/sys/net/if_gif.c:1.84 Mon Apr 20 10:19:54 2015
+++ src/sys/net/if_gif.c Wed Jun 3 02:17:51 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: if_gif.c,v 1.84 2015/04/20 10:19:54 roy Exp $ */
+/* $NetBSD: if_gif.c,v 1.85 2015/06/03 02:17:51 hsuenaga Exp $ */
/* $KAME: if_gif.c,v 1.76 2001/08/20 02:01:02 kjc Exp $ */
/*
@@ -31,7 +31,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: if_gif.c,v 1.84 2015/04/20 10:19:54 roy Exp $);
+__KERNEL_RCSID(0, $NetBSD: if_gif.c,v 1.85 2015/06/03 02:17:51 hsuenaga Exp $);
#include opt_inet.h
@@ -344,12 +344,16 @@ gifintr(void *arg)
switch (sc-gif_psrc-sa_family) {
#ifdef INET
case AF_INET:
+ mutex_enter(softnet_lock);
error = in_gif_output(ifp, family, m);
+ mutex_exit(softnet_lock);
break;
#endif
#ifdef INET6
case AF_INET6:
+ mutex_enter(softnet_lock);
error = in6_gif_output(ifp, family, m);
+ mutex_exit(softnet_lock);
break;
#endif
default:
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 02:30:11 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
initialize sdcache operations for PJ4B.
otherwise the kernel crashes without 'options L2CACHE_ENABLE.'
To generate a diff of this commit:
cvs rdiff -u -r1.154 -r1.155 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.154 src/sys/arch/arm/arm/cpufunc.c:1.155
--- src/sys/arch/arm/arm/cpufunc.c:1.154 Thu May 14 05:39:32 2015
+++ src/sys/arch/arm/arm/cpufunc.c Wed Jun 3 02:30:11 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -1380,6 +1380,10 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
+ .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_sdcache_inv_range = (void *)cpufunc_nullop,
+ .cf_sdcache_wb_range = (void *)cpufunc_nullop,
+
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
CVS commit: src/sys/net
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 02:17:51 UTC 2015 Modified Files: src/sys/net: if_gif.c Log Message: Obtain softnet_lock before entering IP networking stack from gif software interrupt. To generate a diff of this commit: cvs rdiff -u -r1.84 -r1.85 src/sys/net/if_gif.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/marvell
Module Name:src
Committed By: hsuenaga
Date: Wed Jun 3 03:25:51 UTC 2015
Modified Files:
src/sys/arch/evbarm/marvell: marvell_machdep.c
Log Message:
initialize ARMADA XP's Mbus address decoder and code clean up
probably we need more sophisticated Mbus driver or KPI...
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/evbarm/marvell/marvell_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/marvell/marvell_machdep.c
diff -u src/sys/arch/evbarm/marvell/marvell_machdep.c:1.31 src/sys/arch/evbarm/marvell/marvell_machdep.c:1.32
--- src/sys/arch/evbarm/marvell/marvell_machdep.c:1.31 Thu May 14 05:39:32 2015
+++ src/sys/arch/evbarm/marvell/marvell_machdep.c Wed Jun 3 03:25:51 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: marvell_machdep.c,v 1.31 2015/05/14 05:39:32 hsuenaga Exp $ */
+/* $NetBSD: marvell_machdep.c,v 1.32 2015/06/03 03:25:51 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi
* All rights reserved.
@@ -25,7 +25,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: marvell_machdep.c,v 1.31 2015/05/14 05:39:32 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: marvell_machdep.c,v 1.32 2015/06/03 03:25:51 hsuenaga Exp $);
#include opt_evbarm_boardtype.h
#include opt_ddb.h
@@ -130,6 +130,45 @@ static void marvell_device_register(devi
static void marvell_startend_by_tag(int, uint64_t *, uint64_t *);
#endif
+static void
+marvell_fixup_mbus_pex(int memtag, int iotag)
+{
+ uint32_t target, attr;
+ int window;
+
+ /* Reset PCI-Express space to window register. */
+ window = mvsoc_target(memtag, target, attr, NULL, NULL);
+ write_mlmbreg(MVSOC_MLMB_WCR(window),
+ MVSOC_MLMB_WCR_WINEN |
+ MVSOC_MLMB_WCR_TARGET(target) |
+ MVSOC_MLMB_WCR_ATTR(attr) |
+ MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE));
+ write_mlmbreg(MVSOC_MLMB_WBR(window),
+ MARVELL_PEXMEM_PBASE MVSOC_MLMB_WBR_BASE_MASK);
+#ifdef PCI_NETBSD_CONFIGURE
+ if (window nremap) {
+ write_mlmbreg(MVSOC_MLMB_WRLR(window),
+ MARVELL_PEXMEM_PBASE MVSOC_MLMB_WRLR_REMAP_MASK);
+ write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
+ }
+#endif
+ window = mvsoc_target(iotag, target, attr, NULL, NULL);
+ write_mlmbreg(MVSOC_MLMB_WCR(window),
+ MVSOC_MLMB_WCR_WINEN |
+ MVSOC_MLMB_WCR_TARGET(target) |
+ MVSOC_MLMB_WCR_ATTR(attr) |
+ MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE));
+ write_mlmbreg(MVSOC_MLMB_WBR(window),
+ MARVELL_PEXIO_PBASE MVSOC_MLMB_WBR_BASE_MASK);
+#ifdef PCI_NETBSD_CONFIGURE
+ if (window nremap) {
+ write_mlmbreg(MVSOC_MLMB_WRLR(window),
+ MARVELL_PEXIO_PBASE MVSOC_MLMB_WRLR_REMAP_MASK);
+ write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
+ }
+#endif
+}
+
#if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)
static void
marvell_system_reset(void)
@@ -146,8 +185,20 @@ marvell_system_reset(void)
cpu_reset();
/*NOTREACHED*/
}
+
+static void
+marvell_fixup_mbus(int memtag, int iotag)
+{
+ /* assume u-boot initializes mbus registers correctly */
+
+ /* set marvell common PEX params */
+ marvell_fixup_mbus_pex(memtag, iotag);
+
+ /* other configurations? */
+}
#endif
+
#if defined(ARMADAXP)
static void
armadaxp_system_reset(void)
@@ -166,6 +217,18 @@ armadaxp_system_reset(void)
/*NOTREACHED*/
}
+
+static void
+armadaxp_fixup_mbus(int memtag, int iotag)
+{
+ /* force set SoC default parameters */
+ armadaxp_init_mbus();
+
+ /* set marvell common PEX params */
+ marvell_fixup_mbus_pex(memtag, iotag);
+
+ /* other configurations? */
+}
#endif
@@ -223,8 +286,7 @@ extern uint32_t *u_boot_args[];
u_int
initarm(void *arg)
{
- uint32_t target, attr, base, size;
- int cs, cs_end, memtag = 0, iotag = 0, window;
+ int cs, cs_end, memtag = 0, iotag = 0;
mvsoc_bootstrap(MARVELL_INTERREGS_VBASE);
@@ -277,6 +339,7 @@ initarm(void *arg)
cs_end = MARVELL_TAG_SDRAM_CS3;
orion_getclks(MARVELL_INTERREGS_VBASE);
+ marvell_fixup_mbus(memtag, iotag);
break;
#endif /* ORION */
@@ -299,6 +362,7 @@ initarm(void *arg)
kirkwood_getclks(MARVELL_INTERREGS_VBASE);
mvsoc_clkgating = kirkwood_clkgating;
+ marvell_fixup_mbus(memtag, iotag);
break;
#endif /* KIRKWOOD */
@@ -318,6 +382,7 @@ initarm(void *arg)
cs_end = MARVELL_TAG_SDRAM_CS3;
mv78xx0_getclks(MARVELL_INTERREGS_VBASE);
+ marvell_fixup_mbus(memtag, iotag);
break;
#endif /* MV78XX0 */
@@ -343,6 +408,7 @@ initarm(void *arg)
misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
armadaxp_getclks();
mvsoc_clkgating = armadaxp_clkgating;
+ armadaxp_fixup_mbus(memtag, iotag);
#ifdef L2CACHE_ENABLE
/* Initialize L2 Cache */
@@ -374,14 +440,11 @@ initarm(void *arg)
misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
armada370_getclks();
mvsoc_clkgating = armadaxp_clkgating;
+ armadaxp_fixup_mbus(memtag, iotag);
#ifdef L2CACHE_ENABLE
/*
CVS commit: src/sys/arch/evbarm/marvell
Module Name:src Committed By: hsuenaga Date: Wed Jun 3 03:25:51 UTC 2015 Modified Files: src/sys/arch/evbarm/marvell: marvell_machdep.c Log Message: initialize ARMADA XP's Mbus address decoder and code clean up probably we need more sophisticated Mbus driver or KPI... To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/evbarm/marvell/marvell_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Re: CVS commit: src/sys/arch/arm
On 2015/05/20 2:30, Matt Thomas wrote: On May 19, 2015, at 2:20 AM, SUENAGA Hiroki hsuen...@netbsd.org wrote: Module Name: src Committed By:hsuenaga Date:Tue May 19 09:20:19 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S src/sys/arch/arm/marvell: armadaxp.c mvsocreg.h Log Message: fix Marvell Coherency Barrier register address. configure coherency bus maintance broadcast using MPIDR. we need to configure this regardless of 'options MULTIPROCESSOR.' Please move the MPIDR defines to arm/armreg.h and use __BIT or __BITS. Done for implementation neutral(just rewrite to use __BIT/__BITS), Cortex A9 implementation, and PJ4B implementation. -- SUENAGA Hiroki hsuen...@netbsd.net PGP: 66B3 8939 6758 20BA F243 89EC 557A 8CFB ABA9 5E92
CVS commit: src/sys/arch/arm
Module Name:src Committed By: hsuenaga Date: Tue May 19 09:20:19 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S src/sys/arch/arm/marvell: armadaxp.c mvsocreg.h Log Message: fix Marvell Coherency Barrier register address. configure coherency bus maintance broadcast using MPIDR. we need to configure this regardless of 'options MULTIPROCESSOR.' To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/marvell/armadaxp.c cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/mvsocreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.9 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.10 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.9 Thu May 14 17:15:56 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Tue May 19 09:20:19 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.9 2015/05/14 17:15:56 matt Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.10 2015/05/19 09:20:19 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -41,6 +41,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI #include arm/asm.h #include arm/locore.h +#define MV_FMC0_SMP (1 1) /* SMP/nAMP enable */ +#define MV_FMC0_PARITY (1 2) /* Enable L1 Cache Parity */ +#define MV_FMC0_LFDIS (1 7) /* Disable DC Speculative linefill*/ +#define MV_FMC0_FW (1 8) /* Cache TLB maintenance broadcast */ + +#define MPIDR_CPUID_MASK (0x3 0) /* CPUID */ +#define MPIDR_CLUSTERID_MASK (0xf 8) /* CLUSTERID */ +#define MPIDR_UNI_PROCESSOR (1 30) /* Uni-Processor System */ +#define MPIDR_MPCORE (1 31) /* New Style MPCore like CortexA9 */ + /* LINTSTUB: void pj4b_cpu_sleep(int); */ ENTRY(pj4b_cpu_sleep) dsb @@ -51,21 +61,21 @@ END(pj4b_cpu_sleep) /* LINTSTUB: void pj4b_config(void); */ ENTRY(pj4b_config) - /* Set Auxiliary Debug Modes Control 0 register */ + /* Set Marvell Auxiliary Debug Modes Control 0 register */ mrc p15, 1, r0, c15, c1, 0 bic r0, r0, #(1 12) @ Erratum#ARM-CPU-6136 @ LDSTM 1st issue is single word orr r0, r0, #(1 22) @ DVM_WAKEUP enable mcr p15, 1, r0, c15, c1, 0 - /* Set Auxiliary Debug Modes Control 1 register */ + /* Set Marvell Auxiliary Debug Modes Control 1 register */ mrc p15, 1, r0, c15, c1, 1 bic r0, r0, #(1 2) @ Erratum#ARM-CPU-6409 @ Disable static branch prediction orr r0, r0, #(1 5) @ STREX backoff disable mcr p15, 1, r0, c15, c1, 1 - /* Set Auxiliary Debug Modes Control 2 register */ + /* Set Marvell Auxiliary Debug Modes Control 2 register */ mrc p15, 1, r0, c15, c1, 2 bic r0, r0, #(1 23) @ Enable fast LDR orr r0, r0, #(1 25) @ Intervention Interleave disable @@ -75,13 +85,18 @@ ENTRY(pj4b_config) orr r0, r0, #(1 31) @ Enable write evict mcr p15, 1, r0, c15, c1, 2 - /* Set Auxiliary FUnction Modes Control 0 register */ - mrc p15, 1, r0, c15, c2, 0 -#ifdef MULTIPROCESSOR - orr r0, r0, #(1 1) @ SMP/nAMP enable -#endif - orr r0, r0, #(1 2) @ L2 parity enable - orr r0, r0, #(1 8) @ Cache TLB maintenance broadcast + /* Set Marvell Auxiliary Function Modes Control 0 register */ + mrc p15, 1, r0, c15, c2, 0 @ get FMC0 + mrc p15, 0, ip, c0, c0, 5 @ get MPIDR + tst ip, #MPIDR_MPCORE + beq 1f@ if not set, not a MPCORE + tst ip, #MPIDR_UNI_PROCESSOR + bne 1f@ if set, uni-processor system + orr r0, r0, #(MV_FMC0_SMP) @ enable SMP/nAMP + orr r0, r0, #(MV_FMC0_FW) @ enable maintenance bcast +1: + bic r0, r0, #(MV_FMC0_LFDIS) @ enable speculative linefill + orr r0, r0, #(MV_FMC0_PARITY) @ enable L1 parity mcr p15, 1, r0, c15, c2, 0 RET @@ -97,7 +112,7 @@ ENTRY_NP(pj4b_io_coherency_barrier) 1: ldr r1, [r0] tst r1, #1 - beq 1b + bne 1b @ if set, CIB is busy. dsb RET END(pj4b_io_coherency_barrier) Index: src/sys/arch/arm/marvell/armadaxp.c diff -u src/sys/arch/arm/marvell/armadaxp.c:1.13 src/sys/arch/arm/marvell/armadaxp.c:1.14 --- src/sys/arch/arm/marvell/armadaxp.c:1.13 Thu May 14 05:39:32 2015 +++ src/sys/arch/arm/marvell/armadaxp.c Tue May 19 09:20:19 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $ */ +/* $NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI ***/ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.13 2015/05/14 05:39:32 hsuenaga Exp $); +__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.14 2015/05/19 09:20:19 hsuenaga Exp $); #define _INTR_PRIVATE @@ -49,7 +49,6 @@
CVS commit: src/sys/arch/arm
Module Name:src Committed By: hsuenaga Date: Tue May 19 09:20:19 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S src/sys/arch/arm/marvell: armadaxp.c mvsocreg.h Log Message: fix Marvell Coherency Barrier register address. configure coherency bus maintance broadcast using MPIDR. we need to configure this regardless of 'options MULTIPROCESSOR.' To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/marvell/armadaxp.c cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/mvsocreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm
Module Name:src Committed By: hsuenaga Date: Wed May 20 02:59:57 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S src/sys/arch/arm/include: armreg.h Log Message: move register accessor macros for MPIDR and AUXFMC0 to armreg.h To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.104 -r1.105 src/sys/arch/arm/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.10 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.11 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.10 Tue May 19 09:20:19 2015 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Wed May 20 02:59:57 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.10 2015/05/19 09:20:19 hsuenaga Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.11 2015/05/20 02:59:57 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -88,15 +88,15 @@ ENTRY(pj4b_config) /* Set Marvell Auxiliary Function Modes Control 0 register */ mrc p15, 1, r0, c15, c2, 0 @ get FMC0 mrc p15, 0, ip, c0, c0, 5 @ get MPIDR - tst ip, #MPIDR_MPCORE + tst ip, #PJ4B_MPIDR_MP beq 1f@ if not set, not a MPCORE - tst ip, #MPIDR_UNI_PROCESSOR + tst ip, #PJ4B_MPIDR_U bne 1f@ if set, uni-processor system - orr r0, r0, #(MV_FMC0_SMP) @ enable SMP/nAMP - orr r0, r0, #(MV_FMC0_FW) @ enable maintenance bcast + orr r0, r0, #(PJ4B_AUXFMC0_SMPNAMP) @ enable SMP/nAMP + orr r0, r0, #(PJ4B_AUXFMC0_FW) @ enable maintenance bcast 1: - bic r0, r0, #(MV_FMC0_LFDIS) @ enable speculative linefill - orr r0, r0, #(MV_FMC0_PARITY) @ enable L1 parity + bic r0, r0, #(PJ4B_AUXFMC0_DCSLFD) @ enable speculative linefill + orr r0, r0, #(PJ4B_AUXFMC0_L1PARITY) @ enable L1 parity mcr p15, 1, r0, c15, c2, 0 RET Index: src/sys/arch/arm/include/armreg.h diff -u src/sys/arch/arm/include/armreg.h:1.104 src/sys/arch/arm/include/armreg.h:1.105 --- src/sys/arch/arm/include/armreg.h:1.104 Mon Apr 27 06:56:53 2015 +++ src/sys/arch/arm/include/armreg.h Wed May 20 02:59:57 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.104 2015/04/27 06:56:53 skrll Exp $ */ +/* $NetBSD: armreg.h,v 1.105 2015/05/20 02:59:57 hsuenaga Exp $ */ /* * Copyright (c) 1998, 2001 Ben Harris @@ -434,8 +434,17 @@ #define MPCORE_AUXCTL_EX 0x0010 /* exclusive L1/L2 cache */ #define MPCORE_AUXCTL_SA 0x0020 /* SMP/AMP */ -/* Marvell PJ4B Auxillary Control Register */ -#define PJ4B_AUXCTL_SMPNAMP 0x0040 /* SMP/AMP */ +/* Marvell PJ4B Auxillary Control Register (CP15.0.R1.c0.1) */ +#define PJ4B_AUXCTL_FW __BIT(0) /* Cache and TLB updates broadcast */ +#define PJ4B_AUXCTL_SMPNAMP __BIT(6) /* 0 = AMP, 1 = SMP */ +#define PJ4B_AUXCTL_L1PARITY __BIT(9) /* L1 parity checking */ + +/* Marvell PJ4B Auxialiary Function Modes Control 0 (CP15.1.R15.c2.0) */ +#define PJ4B_AUXFMC0_L2EN __BIT(0) /* Tightly-Coupled L2 cache enable */ +#define PJ4B_AUXFMC0_SMPNAMP __BIT(1) /* 0 = AMP, 1 = SMP */ +#define PJ4B_AUXFMC0_L1PARITY __BIT(2) /* alias of PJ4B_AUXCTL_L1PARITY */ +#define PJ4B_AUXFMC0_DCSLFD __BIT(2) /* Disable DC Speculative linefill */ +#define PJ4B_AUXFMC0_FW __BIT(8) /* alias of PJ4B_AUXCTL_FW*/ /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ #define CORTEXA9_AUXCTL_FW 0x0001 /* Cache and TLB updates broadcast */ @@ -671,6 +680,27 @@ #define PRRR_TR_DEVICE 1 // Device #define PRRR_TR_NORMAL 2 // Normal Memory +/* ARMv7 MPIDR, Multiprocessor Affinity Register generic format */ +#define MPIDR_MP __BIT(31) /* 1 = Have MP Extention */ +#define MPIDR_U __BIT(30) /* 1 = Uni-Processor System */ +#define MPIDR_MT __BIT(24) /* 1 = SMT(AFF0 is logical) */ +#define MPIDR_AFF2 __BITS(23,16) /* Affinity Level 2 */ +#define MPIDR_AFF1 __BITS(15,8) /* Affinity Level 1 */ +#define MPIDR_AFF0 __BITS(7,0) /* Affinity Level 0 */ + +/* MPIDR implementation of ARM Cortex A9: SMT and AFF2 is not used */ +#define CORTEXA9_MPIDR_MP MPIDR_MP +#define CORTEXA9_MPIDR_U MPIDR_U +#define CORTEXA9_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ +#define CORTEXA9_MPIDR_CPUID __BITS(0,1) /* AFF0 = phisycal core id */ + +/* MPIDR implementation of Marvell PJ4B-MP: AFF2 is not used */ +#define PJ4B_MPIDR_MP MPIDR_MP +#define PJ4B_MPIDR_U MPIDR_U +#define PJ4B_MPIDR_MT MPIDR_MT /* 1 = SMT(AFF0 is logical) */ +#define PJ4B_MPIDR_CLID __BITS(11,8) /* AFF1 = cluster id */ +#define PJ4B_MPIDR_CPUID __BITS(0,3) /* AFF0 = core id */ + /* Defines for ARM Generic Timer */ #define ARM_CNTCTL_ENABLE __BIT(0) // Timer Enabled #define ARM_CNTCTL_IMASK __BIT(1) // Mask Interrupt @@ -1018,12 +1048,4 @@ ARMREG_WRITE_INLINE(sheeva_xctrl, p15,1 #endif /* !__ASSEMBLER__ */ - -#define MPIDR_31 0x8000 -#define
CVS commit: src/sys/arch/arm
Module Name:src Committed By: hsuenaga Date: Wed May 20 02:59:57 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S src/sys/arch/arm/include: armreg.h Log Message: move register accessor macros for MPIDR and AUXFMC0 to armreg.h To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.104 -r1.105 src/sys/arch/arm/include/armreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch
Module Name:src Committed By: hsuenaga Date: Thu May 14 05:39:32 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S src/sys/arch/arm/include: cpufunc_proto.h src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h mvsocreg.h src/sys/arch/evbarm/marvell: marvell_machdep.c Log Message: add synchronization barrier for AURORA_IO_CACHE_COHERENCY. cleanup MARVELL L2 cache code. To generate a diff of this commit: cvs rdiff -u -r1.153 -r1.154 src/sys/arch/arm/arm/cpufunc.c cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/include/cpufunc_proto.h cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/marvell/armadaxp.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/marvell/armadaxpreg.h cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/mvsocreg.h cvs rdiff -u -r1.30 -r1.31 src/sys/arch/evbarm/marvell/marvell_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch
Module Name:src
Committed By: hsuenaga
Date: Thu May 14 05:39:32 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S
src/sys/arch/arm/include: cpufunc_proto.h
src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h mvsocreg.h
src/sys/arch/evbarm/marvell: marvell_machdep.c
Log Message:
add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.
To generate a diff of this commit:
cvs rdiff -u -r1.153 -r1.154 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/include/cpufunc_proto.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/marvell/armadaxp.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/marvell/armadaxpreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/mvsocreg.h
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/evbarm/marvell/marvell_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.153 src/sys/arch/arm/arm/cpufunc.c:1.154
--- src/sys/arch/arm/arm/cpufunc.c:1.153 Fri Apr 17 13:39:01 2015
+++ src/sys/arch/arm/arm/cpufunc.c Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.154 2015/05/14 05:39:32 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -1371,8 +1371,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_tlb_flushD = armv7_tlb_flushID,
.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
- /* Cache operations */
-
+ /* Cache operations (see also pj4bv7_setup) */
.cf_icache_sync_all = armv7_idcache_wbinv_all,
.cf_icache_sync_range = armv7_icache_sync_range,
@@ -1381,18 +1380,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
-#if defined(L2CACHE_ENABLE) \
-!defined(AURORA_IO_CACHE_COHERENCY) \
-defined(ARMADAXP)
- .cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
- .cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
- .cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
-#else
- .cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
- .cf_sdcache_inv_range = (void *)cpufunc_nullop,
- .cf_sdcache_wb_range = (void *)cpufunc_nullop,
-#endif
-
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
@@ -3096,6 +3083,36 @@ pj4bv7_setup(char *args)
cpuctrl |= CPU_CONTROL_VECRELOC;
#endif
+#ifdef L2CACHE_ENABLE
+ /* Setup L2 cache */
+ arm_scache.cache_type = CPU_CT_CTYPE_WT;
+ arm_scache.cache_unified = 1;
+ arm_scache.dcache_type = arm_scache.icache_type = CACHE_TYPE_PIPT;
+ arm_scache.dcache_size = arm_scache.icache_size = ARMADAXP_L2_SIZE;
+ arm_scache.dcache_ways = arm_scache.icache_ways = ARMADAXP_L2_WAYS;
+ arm_scache.dcache_way_size = arm_scache.icache_way_size =
+ ARMADAXP_L2_WAY_SIZE;
+ arm_scache.dcache_line_size = arm_scache.icache_line_size =
+ ARMADAXP_L2_LINE_SIZE;
+ arm_scache.dcache_sets = arm_scache.icache_sets =
+ ARMADAXP_L2_SETS;
+
+ cpufuncs.cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range;
+ cpufuncs.cf_sdcache_inv_range = armadaxp_sdcache_inv_range;
+ cpufuncs.cf_sdcache_wb_range = armadaxp_sdcache_wb_range;
+#endif
+
+#ifdef AURORA_IO_CACHE_COHERENCY
+ /* use AMBA and I/O Coherency Fabric to maintain cache */
+ cpufuncs.cf_dcache_wbinv_range = pj4b_dcache_cfu_wbinv_range;
+ cpufuncs.cf_dcache_inv_range = pj4b_dcache_cfu_inv_range;
+ cpufuncs.cf_dcache_wb_range = pj4b_dcache_cfu_wb_range;
+
+ cpufuncs.cf_sdcache_wbinv_range = (void *)cpufunc_nullop;
+ cpufuncs.cf_sdcache_inv_range = (void *)cpufunc_nullop;
+ cpufuncs.cf_sdcache_wb_range = (void *)cpufunc_nullop;
+#endif
+
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -3104,6 +3121,9 @@ pj4bv7_setup(char *args)
/* And again. */
cpu_idcache_wbinv_all();
+#ifdef L2CACHE_ENABLE
+ armadaxp_sdcache_wbinv_all();
+#endif
curcpu()-ci_ctrl = cpuctrl;
}
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7 Wed Apr 15 10:52:18 2015
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu May 14 05:39:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.7 2015/04/15 10:52:18 hsuenaga Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.8 2015/05/14 05:39:32 hsuenaga Exp $ */
/***
Copyright (C) Marvell International
CVS commit: src/sys/arch/arm/marvell
Module Name:src
Committed By: hsuenaga
Date: Mon May 11 05:49:48 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: mvsoc.c
Log Message:
add MARVELL Armada XP MV78260 B0(rev.2)
recent OpenBlocks AX3 uses it.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/marvell/mvsoc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/mvsoc.c
diff -u src/sys/arch/arm/marvell/mvsoc.c:1.19 src/sys/arch/arm/marvell/mvsoc.c:1.20
--- src/sys/arch/arm/marvell/mvsoc.c:1.19 Sun May 3 14:38:09 2015
+++ src/sys/arch/arm/marvell/mvsoc.c Mon May 11 05:49:48 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $ */
+/* $NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $ */
/*
* Copyright (c) 2007, 2008, 2013, 2014 KIYOHARA Takashi
* All rights reserved.
@@ -26,7 +26,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.19 2015/05/03 14:38:09 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: mvsoc.c,v 1.20 2015/05/11 05:49:48 hsuenaga Exp $);
#include opt_cputypes.h
#include opt_mvsoc.h
@@ -348,6 +348,7 @@ static struct {
{ ARMADAXP(MV78160), 1, MV78160, A0, Armada XP },
{ ARMADAXP(MV78230), 1, MV78260, A0, Armada XP },
{ ARMADAXP(MV78260), 1, MV78260, A0, Armada XP },
+ { ARMADAXP(MV78260), 2, MV78260, B0, Armada XP },
{ ARMADAXP(MV78460), 1, MV78460, A0, Armada XP },
{ ARMADAXP(MV78460), 2, MV78460, B0, Armada XP },
@@ -433,6 +434,7 @@ static struct {
{ ARMADAXP(MV78160), 1, ddr3_tags },
{ ARMADAXP(MV78230), 1, ddr3_tags },
{ ARMADAXP(MV78260), 1, ddr3_tags },
+ { ARMADAXP(MV78260), 2, ddr3_tags },
{ ARMADAXP(MV78460), 1, ddr3_tags },
{ ARMADAXP(MV78460), 2, ddr3_tags },
CVS commit: src/sys/arch/arm/marvell
Module Name:src
Committed By: hsuenaga
Date: Sun May 3 06:29:32 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: armadaxp.c
Log Message:
write back unaligned boundary of L2 cache even if invalidate operation
is requested.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/marvell/armadaxp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.11 src/sys/arch/arm/marvell/armadaxp.c:1.12
--- src/sys/arch/arm/marvell/armadaxp.c:1.11 Fri Apr 17 13:43:55 2015
+++ src/sys/arch/arm/marvell/armadaxp.c Sun May 3 06:29:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.11 2015/04/17 13:43:55 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.12 2015/05/03 06:29:31 hsuenaga Exp $ */
/***
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
***/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.11 2015/04/17 13:43:55 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.12 2015/05/03 06:29:31 hsuenaga Exp $);
#define _INTR_PRIVATE
@@ -500,23 +500,42 @@ armadaxp_sdcache_wbinv_all(void)
void
armadaxp_sdcache_inv_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base, pa_end;
+ paddr_t pa_base = pa;
+ paddr_t pa_end = pa + sz - 1;
- pa_base = pa ~0x1f;
- pa_end = (pa_base + sz + 0x20) ~0x1f;
- L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
- L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end);
+ /* need write back if boundary is not aligned */
+ if (pa_base 0x1f)
+ L2_WRITE(ARMADAXP_L2_WB_PHYS, (pa_base ~0x1f));
+ if (pa_end 0x1f)
+ L2_WRITE(ARMADAXP_L2_WB_PHYS, (pa_end ~0x1f));
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
+ __asm__ __volatile__(dsb);
+
+ /* invalidate other cache */
+ pa_base = ~0x1f;
+ pa_end = ~0x1f;
+ if (pa_base == pa_end)
+ L2_WRITE(ARMADAXP_L2_INV_PHYS, pa_base);
+ else {
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end);
+ }
}
void
armadaxp_sdcache_wb_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base, pa_end;
+ paddr_t pa_base = pa;
+ paddr_t pa_end = pa + sz - 1;
- pa_base = pa ~0x1f;
- pa_end = (pa_base + sz + 0x20) ~0x1f;
- L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
- L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+ pa_base = ~0x1f;
+ pa_end = ~0x1f;
+ if (pa_base == pa_end)
+ L2_WRITE(ARMADAXP_L2_WB_PHYS, pa_base);
+ else {
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+ }
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
@@ -524,12 +543,17 @@ armadaxp_sdcache_wb_range(vaddr_t va, pa
void
armadaxp_sdcache_wbinv_range(vaddr_t va, paddr_t pa, psize_t sz)
{
- paddr_t pa_base, pa_end;
+ paddr_t pa_base = pa;
+ paddr_t pa_end = pa + sz - 1;
- pa_base = pa ~0x1f;
- pa_end = (pa_base + sz + 0x20) ~0x1f;
- L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
- L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+ pa_base = ~0x1f;
+ pa_end = ~0x1f;
+ if (pa_base == pa_end)
+ L2_WRITE(ARMADAXP_L2_WBINV_PHYS, pa_base);
+ else {
+ L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
+ L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+ }
L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
CVS commit: src/sys/arch/arm/arm
Module Name:src
Committed By: hsuenaga
Date: Fri Apr 17 13:39:02 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
Log Message:
don't call L2 maintance function if L2 cache is disabled.
To generate a diff of this commit:
cvs rdiff -u -r1.152 -r1.153 src/sys/arch/arm/arm/cpufunc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.152 src/sys/arch/arm/arm/cpufunc.c:1.153
--- src/sys/arch/arm/arm/cpufunc.c:1.152 Wed Apr 15 10:52:18 2015
+++ src/sys/arch/arm/arm/cpufunc.c Fri Apr 17 13:39:01 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.153 2015/04/17 13:39:01 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -1381,7 +1381,9 @@ struct cpu_functions pj4bv7_cpufuncs = {
.cf_dcache_inv_range = armv7_dcache_inv_range,
.cf_dcache_wb_range = armv7_dcache_wb_range,
-#if !defined(AURORA_IO_CACHE_COHERENCY) defined(ARMADAXP)
+#if defined(L2CACHE_ENABLE) \
+!defined(AURORA_IO_CACHE_COHERENCY) \
+defined(ARMADAXP)
.cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
.cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
.cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: hsuenaga Date: Fri Apr 17 13:39:02 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc.c Log Message: don't call L2 maintance function if L2 cache is disabled. To generate a diff of this commit: cvs rdiff -u -r1.152 -r1.153 src/sys/arch/arm/arm/cpufunc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Fri Apr 17 13:43:55 UTC 2015 Modified Files: src/sys/arch/arm/marvell: armadaxp.c Log Message: sync L2 cache on the tail of region. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/armadaxp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/marvell/armadaxp.c diff -u src/sys/arch/arm/marvell/armadaxp.c:1.10 src/sys/arch/arm/marvell/armadaxp.c:1.11 --- src/sys/arch/arm/marvell/armadaxp.c:1.10 Wed Apr 15 12:11:31 2015 +++ src/sys/arch/arm/marvell/armadaxp.c Fri Apr 17 13:43:55 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $ */ +/* $NetBSD: armadaxp.c,v 1.11 2015/04/17 13:43:55 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI ***/ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $); +__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.11 2015/04/17 13:43:55 hsuenaga Exp $); #define _INTR_PRIVATE @@ -503,7 +503,7 @@ armadaxp_sdcache_inv_range(vaddr_t va, p paddr_t pa_base, pa_end; pa_base = pa ~0x1f; - pa_end = (pa_base + sz) ~0x1f; + pa_end = (pa_base + sz + 0x20) ~0x1f; L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base); L2_WRITE(ARMADAXP_L2_INV_RANGE, pa_end); } @@ -514,7 +514,7 @@ armadaxp_sdcache_wb_range(vaddr_t va, pa paddr_t pa_base, pa_end; pa_base = pa ~0x1f; - pa_end = (pa_base + sz) ~0x1f; + pa_end = (pa_base + sz + 0x20) ~0x1f; L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base); L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end); L2_WRITE(ARMADAXP_L2_SYNC, 0); @@ -527,7 +527,7 @@ armadaxp_sdcache_wbinv_range(vaddr_t va, paddr_t pa_base, pa_end; pa_base = pa ~0x1f; - pa_end = (pa_base + sz) ~0x1f; + pa_end = (pa_base + sz + 0x20) ~0x1f; L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base); L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end); L2_WRITE(ARMADAXP_L2_SYNC, 0);
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Fri Apr 17 13:43:55 UTC 2015 Modified Files: src/sys/arch/arm/marvell: armadaxp.c Log Message: sync L2 cache on the tail of region. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/marvell/armadaxp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
Module Name:src
Committed By: hsuenaga
Date: Wed Apr 15 12:11:31 UTC 2015
Modified Files:
src/sys/arch/arm/marvell: armadaxp.c
Log Message:
add L2 cache write eviction buffer sync barrier
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/armadaxp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/marvell/armadaxp.c
diff -u src/sys/arch/arm/marvell/armadaxp.c:1.9 src/sys/arch/arm/marvell/armadaxp.c:1.10
--- src/sys/arch/arm/marvell/armadaxp.c:1.9 Wed Apr 15 10:40:36 2015
+++ src/sys/arch/arm/marvell/armadaxp.c Wed Apr 15 12:11:31 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $ */
+/* $NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $ */
/***
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
***/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $);
#define _INTR_PRIVATE
@@ -485,6 +485,7 @@ void
armadaxp_sdcache_wb_all(void)
{
L2_WRITE(ARMADAXP_L2_WB_WAY, L2_ALL_WAYS);
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
@@ -492,6 +493,7 @@ void
armadaxp_sdcache_wbinv_all(void)
{
L2_WRITE(ARMADAXP_L2_WBINV_WAY, L2_ALL_WAYS);
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
@@ -515,6 +517,7 @@ armadaxp_sdcache_wb_range(vaddr_t va, pa
pa_end = (pa_base + sz) ~0x1f;
L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
@@ -527,6 +530,7 @@ armadaxp_sdcache_wbinv_range(vaddr_t va,
pa_end = (pa_base + sz) ~0x1f;
L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+ L2_WRITE(ARMADAXP_L2_SYNC, 0);
__asm__ __volatile__(dsb);
}
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Wed Apr 15 12:11:31 UTC 2015 Modified Files: src/sys/arch/arm/marvell: armadaxp.c Log Message: add L2 cache write eviction buffer sync barrier To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/marvell/armadaxp.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/evbarm/armadaxp
Module Name:src
Committed By: hsuenaga
Date: Wed Apr 15 10:30:42 UTC 2015
Modified Files:
src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c
Log Message:
lookup clock frequencies of ARMADA 370 correctly.
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
diff -u src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.9 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.10
--- src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.9 Wed Apr 15 10:15:40 2015
+++ src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c Wed Apr 15 10:30:42 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp_machdep.c,v 1.9 2015/04/15 10:15:40 hsuenaga Exp $ */
+/* $NetBSD: armadaxp_machdep.c,v 1.10 2015/04/15 10:30:42 hsuenaga Exp $ */
/***
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
***/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: armadaxp_machdep.c,v 1.9 2015/04/15 10:15:40 hsuenaga Exp $);
+__KERNEL_RCSID(0, $NetBSD: armadaxp_machdep.c,v 1.10 2015/04/15 10:30:42 hsuenaga Exp $);
#include opt_machdep.h
#include opt_mvsoc.h
@@ -92,6 +92,7 @@ __KERNEL_RCSID(0, $NetBSD: armadaxp_mac
#include evbarm/marvell/marvellreg.h
#include evbarm/marvell/marvellvar.h
+#include dev/marvell/marvellreg.h
#include mvpex.h
#include com.h
@@ -344,7 +345,21 @@ initarm(void *arg)
/* Get CPU, system and timebase frequencies */
extern vaddr_t misc_base;
misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE;
- armadaxp_getclks();
+ switch (mvsoc_model()) {
+ case MARVELL_ARMADA370_MV6707:
+ case MARVELL_ARMADA370_MV6710:
+ case MARVELL_ARMADA370_MV6W11:
+ armada370_getclks();
+ break;
+ case MARVELL_ARMADAXP_MV78130:
+ case MARVELL_ARMADAXP_MV78160:
+ case MARVELL_ARMADAXP_MV78230:
+ case MARVELL_ARMADAXP_MV78260:
+ case MARVELL_ARMADAXP_MV78460:
+ default:
+ armadaxp_getclks();
+ break;
+ }
mvsoc_clkgating = armadaxp_clkgating;
/* Preconfigure interrupts */
CVS commit: src/sys/arch/evbarm/armadaxp
Module Name:src Committed By: hsuenaga Date: Wed Apr 15 10:30:42 UTC 2015 Modified Files: src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c Log Message: lookup clock frequencies of ARMADA 370 correctly. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
Module Name:src Committed By: hsuenaga Date: Wed Apr 15 10:40:36 UTC 2015 Modified Files: src/sys/arch/arm/marvell: armadaxp.c armadaxpreg.h Added Files: src/sys/arch/arm/marvell: armadaxpvar.h Log Message: implement L2 cache maintenance operations of ARMADA XP. the L2 cahce maintenance operations are defined on SoC internal registers. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/marvell/armadaxp.c cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/marvell/armadaxpreg.h cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/marvell/armadaxpvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/marvell
:36 hsuenaga Exp $ */ +/* + * Copyright (c) 2015 SUENAGA Hiroki + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _ARMDAXPVAR_H_ +#define _ARMDAXPVAR_H_ +#include machine/bus_defs.h + +/* device initalization */ +extern void armadaxp_io_coherency_init(void); +extern int armadaxp_l2_init(bus_addr_t); + +/* l2cache maintanance */ +extern void armadaxp_sdcache_inv_all(void); +extern void armadaxp_sdcache_wb_all(void); +extern void armadaxp_sdcache_wbinv_all(void); +extern void armadaxp_sdcache_inv_range(vaddr_t, paddr_t, psize_t); +extern void armadaxp_sdcache_wb_range(vaddr_t, paddr_t, psize_t); +extern void armadaxp_sdcache_wbinv_range(vaddr_t, paddr_t, psize_t); + +#endif /* _ARMDAXPVAR_H_ */ +
CVS commit: src/sys/arch/arm
Module Name:src
Committed By: hsuenaga
Date: Wed Apr 15 10:52:19 UTC 2015
Modified Files:
src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S
src/sys/arch/arm/include: cpufunc_proto.h
Log Message:
clean up cpufuncs of CPU_PJ4B.
PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
- Marvell specific registers
- workaround of errata
- and Marvell specific L2 cache maintainance
if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY),
probaly we don't need to maintain L2 cache by software.
To generate a diff of this commit:
cvs rdiff -u -r1.151 -r1.152 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/include/cpufunc_proto.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.151 src/sys/arch/arm/arm/cpufunc.c:1.152
--- src/sys/arch/arm/arm/cpufunc.c:1.151 Wed Feb 25 13:52:42 2015
+++ src/sys/arch/arm/arm/cpufunc.c Wed Apr 15 10:52:18 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.151 2015/02/25 13:52:42 joerg Exp $ */
+/* $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.151 2015/02/25 13:52:42 joerg Exp $);
+__KERNEL_RCSID(0, $NetBSD: cpufunc.c,v 1.152 2015/04/15 10:52:18 hsuenaga Exp $);
#include opt_compat_netbsd.h
#include opt_cpuoptions.h
@@ -88,6 +88,16 @@ __KERNEL_RCSID(0, $NetBSD: cpufunc.c,v
#include arm/xscale/xscalereg.h
#endif
+#if defined(CPU_PJ4B)
+#include opt_cputypes.h
+#include opt_mvsoc.h
+#include machine/bus_defs.h
+#if defined(ARMADAXP)
+#include arm/marvell/armadaxpreg.h
+#include arm/marvell/armadaxpvar.h
+#endif
+#endif
+
#if defined(PERFCTRS)
struct arm_pmc_funcs *arm_pmc;
#endif
@@ -1342,57 +1352,63 @@ struct cpu_functions pj4bv7_cpufuncs = {
/* CPU functions */
.cf_id = cpufunc_id,
- .cf_cpwait = pj4b_drain_writebuf,
+ .cf_cpwait = armv7_drain_writebuf,
/* MMU functions */
.cf_control = cpufunc_control,
.cf_domains = cpufunc_domains,
- .cf_setttb = pj4b_setttb,
+ .cf_setttb = armv7_setttb,
.cf_faultstatus = cpufunc_faultstatus,
.cf_faultaddress = cpufunc_faultaddress,
/* TLB functions */
- .cf_tlb_flushID = pj4b_tlb_flushID,
- .cf_tlb_flushID_SE = pj4b_tlb_flushID_SE,
- .cf_tlb_flushI = pj4b_tlb_flushID,
- .cf_tlb_flushI_SE = pj4b_tlb_flushID_SE,
- .cf_tlb_flushD = pj4b_tlb_flushID,
- .cf_tlb_flushD_SE = pj4b_tlb_flushID_SE,
+ .cf_tlb_flushID = armv7_tlb_flushID,
+ .cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushI = armv7_tlb_flushID,
+ .cf_tlb_flushI_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushD = armv7_tlb_flushID,
+ .cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
/* Cache operations */
.cf_icache_sync_all = armv7_idcache_wbinv_all,
- .cf_icache_sync_range = pj4b_icache_sync_range,
+ .cf_icache_sync_range = armv7_icache_sync_range,
.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
- .cf_dcache_wbinv_range = pj4b_dcache_wbinv_range,
- .cf_dcache_inv_range = pj4b_dcache_inv_range,
- .cf_dcache_wb_range = pj4b_dcache_wb_range,
+ .cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
+ .cf_dcache_inv_range = armv7_dcache_inv_range,
+ .cf_dcache_wb_range = armv7_dcache_wb_range,
+#if !defined(AURORA_IO_CACHE_COHERENCY) defined(ARMADAXP)
+ .cf_sdcache_wbinv_range = armadaxp_sdcache_wbinv_range,
+ .cf_sdcache_inv_range = armadaxp_sdcache_inv_range,
+ .cf_sdcache_wb_range = armadaxp_sdcache_wb_range,
+#else
.cf_sdcache_wbinv_range = (void *)cpufunc_nullop,
.cf_sdcache_inv_range = (void *)cpufunc_nullop,
.cf_sdcache_wb_range = (void *)cpufunc_nullop,
+#endif
.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
- .cf_idcache_wbinv_range = pj4b_idcache_wbinv_range,
+ .cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
/* Other functions */
- .cf_flush_prefetchbuf = pj4b_drain_readbuf,
- .cf_drain_writebuf = pj4b_drain_writebuf,
- .cf_flush_brnchtgt_C = pj4b_flush_brnchtgt_all,
- .cf_flush_brnchtgt_E = pj4b_flush_brnchtgt_va,
+ .cf_flush_prefetchbuf = cpufunc_nullop,
+ .cf_drain_writebuf = armv7_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
- .cf_sleep = (void *)cpufunc_nullop,
+ .cf_sleep = pj4b_cpu_sleep,
/* Soft functions */
.cf_dataabt_fixup = cpufunc_null_fixup,
.cf_prefetchabt_fixup = cpufunc_null_fixup,
- .cf_context_switch = pj4b_context_switch,
+ .cf_context_switch = armv7_context_switch,
.cf_setup = pj4bv7_setup
};
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.7
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 Thu Mar 26 08:50:42 2015
CVS commit: src/sys/arch/arm
Module Name:src Committed By: hsuenaga Date: Wed Apr 15 10:52:19 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc.c cpufunc_asm_pj4b.S src/sys/arch/arm/include: cpufunc_proto.h Log Message: clean up cpufuncs of CPU_PJ4B. PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant. we need funcs for: - Marvell specific registers - workaround of errata - and Marvell specific L2 cache maintainance if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY), probaly we don't need to maintain L2 cache by software. To generate a diff of this commit: cvs rdiff -u -r1.151 -r1.152 src/sys/arch/arm/arm/cpufunc.c cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/include/cpufunc_proto.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys
Module Name:src
Committed By: hsuenaga
Date: Wed Apr 15 10:15:40 UTC 2015
Modified Files:
src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c armadaxp_start.S
src/sys/dev/marvell: if_mvgbe.c
Log Message:
add u-boot argument parser for Marvell ARMADA XP/370.
use 'ethaddr' and 'eth1addr' in u-boot argument to setup MAC address of mvgbe.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbarm/armadaxp/armadaxp_start.S
cvs rdiff -u -r1.40 -r1.41 src/sys/dev/marvell/if_mvgbe.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c
diff -u src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.8 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.9
--- src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c:1.8 Sat Mar 29 15:00:07 2014
+++ src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c Wed Apr 15 10:15:40 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp_machdep.c,v 1.8 2014/03/29 15:00:07 matt Exp $ */
+/* $NetBSD: armadaxp_machdep.c,v 1.9 2015/04/15 10:15:40 hsuenaga Exp $ */
/***
Copyright (C) Marvell International Ltd. and its affiliates
@@ -37,7 +37,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
***/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: armadaxp_machdep.c,v 1.8 2014/03/29 15:00:07 matt Exp $);
+__KERNEL_RCSID(0, $NetBSD: armadaxp_machdep.c,v 1.9 2015/04/15 10:15:40 hsuenaga Exp $);
#include opt_machdep.h
#include opt_mvsoc.h
@@ -100,6 +100,8 @@ __KERNEL_RCSID(0, $NetBSD: armadaxp_mac
#include dev/ic/comvar.h
#endif
+#include net/if_ether.h
+
/*
* Address to call from cpu_reset() to reset the machine.
* This is machine architecture dependent as it varies depending
@@ -110,6 +112,13 @@ BootConfig bootconfig; /* Boot config s
char *boot_args = NULL;
char *boot_file = NULL;
+/*
+ * U-Boot argument buffer
+ */
+extern unsigned int uboot_regs_pa[]; /* saved r0, r1, r2, r3 */
+unsigned int *uboot_regs_va;
+char boot_argbuf[MAX_BOOT_STRING];
+
extern int KERNEL_BASE_phys[];
/*
@@ -393,6 +402,13 @@ initarm(void *arg)
/* we've a specific device_register routine */
evbarm_device_register = axp_device_register;
+ /* copy U-Boot args from U-Boot heap to kernel memory */
+ uboot_regs_va = (int *)((unsigned int)uboot_regs_pa + KERNEL_BASE);
+ boot_args = (char *)(uboot_regs_va[3] + KERNEL_BASE);
+ strlcpy(boot_argbuf, (char *)boot_args, sizeof(boot_argbuf));
+ boot_args = boot_argbuf;
+ parse_mi_bootargs(boot_args);
+
return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
}
@@ -584,5 +600,30 @@ axp_device_register(device_t dev, void *
prop_dictionary_set_uint32(dict,
cache-line-size, arm_dcache_align);
}
+ if (device_is_a(dev, mvgbec)) {
+ uint8_t enaddr[ETHER_ADDR_LEN];
+ char optname[9];
+ int unit = device_unit(dev);
+
+ if (unit 9)
+ return;
+ switch (unit) {
+ case 0:
+ strlcpy(optname, ethaddr, sizeof(optname));
+ break;
+ default:
+ /* eth1addr ... eth9addr */
+ snprintf(optname, sizeof(optname),
+ eth%daddr, unit);
+ break;
+ }
+ if (get_bootconf_option(boot_args, optname,
+ BOOTOPT_TYPE_MACADDR, enaddr)) {
+ prop_data_t pd =
+ prop_data_create_data(enaddr, sizeof(enaddr));
+
+ prop_dictionary_set(dict, mac-address, pd);
+ }
+ }
#endif
}
Index: src/sys/arch/evbarm/armadaxp/armadaxp_start.S
diff -u src/sys/arch/evbarm/armadaxp/armadaxp_start.S:1.3 src/sys/arch/evbarm/armadaxp/armadaxp_start.S:1.4
--- src/sys/arch/evbarm/armadaxp/armadaxp_start.S:1.3 Sat Mar 29 14:53:57 2014
+++ src/sys/arch/evbarm/armadaxp/armadaxp_start.S Wed Apr 15 10:15:40 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $ */
+/* $NetBSD: armadaxp_start.S,v 1.4 2015/04/15 10:15:40 hsuenaga Exp $ */
/***
Copyright (C) Marvell International Ltd. and its affiliates
@@ -44,7 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#include evbarm/marvell/marvellvar.h
#include assym.h
-RCSID($NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $)
+RCSID($NetBSD: armadaxp_start.S,v 1.4 2015/04/15 10:15:40 hsuenaga Exp $)
#ifdef KERNEL_BASES_EQUAL
#error KERNEL_BASE_VIRT should not equal KERNEL_BASE_PHYS
@@ -78,6 +78,10 @@ _C_LABEL(armadaxp_start):
dsb
isb
+ /* Save U-Boot arguments */
+ adr r4, uboot_regs_pa
+ stmia r4!, {r0, r1, r2, r3}
+
/* build page table from scratch */
movw r0, #:lower16:STARTUP_PAGETABLE_ADDR
movt r0, #:upper16:STARTUP_PAGETABLE_ADDR
@@ -133,6 +137,10 @@ _C_LABEL(armadaxp_start):
/* NOTREACHED */
+ .global _C_LABEL(uboot_regs_pa)
+uboot_regs_pa:
+ .space 16 /* r0, r1, r2, r3 */
+
CVS commit: src/sys
Module Name:src Committed By: hsuenaga Date: Wed Apr 15 10:15:40 UTC 2015 Modified Files: src/sys/arch/evbarm/armadaxp: armadaxp_machdep.c armadaxp_start.S src/sys/dev/marvell: if_mvgbe.c Log Message: add u-boot argument parser for Marvell ARMADA XP/370. use 'ethaddr' and 'eth1addr' in u-boot argument to setup MAC address of mvgbe. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/armadaxp/armadaxp_machdep.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbarm/armadaxp/armadaxp_start.S cvs rdiff -u -r1.40 -r1.41 src/sys/dev/marvell/if_mvgbe.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/arm32
Module Name:src
Committed By: hsuenaga
Date: Thu Mar 26 08:45:05 UTC 2015
Modified Files:
src/sys/arch/arm/arm32: arm32_tlb.c
Log Message:
don't use armreg_tlbiasidis_write() and armreg_icialluis_write()
on single processor platforms.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm32/arm32_tlb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.8 src/sys/arch/arm/arm32/arm32_tlb.c:1.9
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.8 Sat Feb 7 00:08:34 2015
+++ src/sys/arch/arm/arm32/arm32_tlb.c Thu Mar 26 08:45:05 2015
@@ -30,7 +30,7 @@
#include opt_multiprocessor.h
#include sys/cdefs.h
-__KERNEL_RCSID(1, $NetBSD: arm32_tlb.c,v 1.8 2015/02/07 00:08:34 jmcneill Exp $);
+__KERNEL_RCSID(1, $NetBSD: arm32_tlb.c,v 1.9 2015/03/26 08:45:05 hsuenaga Exp $);
#include sys/param.h
#include sys/types.h
@@ -93,11 +93,19 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_
arm_dsb();
if (arm_has_tlbiasid_p) {
for (; lo = hi; lo++) {
+#ifdef MULTIPROCESSOR
armreg_tlbiasidis_write(lo);
+#else
+ armreg_tlbiasid_write(lo);
+#endif
}
arm_isb();
if (__predict_false(vivt_icache_p)) {
+#ifdef MULTIPROCESSOR
armreg_icialluis_write(0);
+#else
+ armreg_iciallu_write(0);
+#endif
}
} else {
armreg_tlbiall_write(0);
CVS commit: src/sys/arch/arm/arm32
Module Name:src Committed By: hsuenaga Date: Thu Mar 26 08:45:05 UTC 2015 Modified Files: src/sys/arch/arm/arm32: arm32_tlb.c Log Message: don't use armreg_tlbiasidis_write() and armreg_icialluis_write() on single processor platforms. To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm32/arm32_tlb.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: hsuenaga Date: Thu Mar 26 08:50:42 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S Log Message: set ttbr0/1 using correct register(r2). To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/arm
Module Name:src Committed By: hsuenaga Date: Thu Mar 26 08:50:42 UTC 2015 Modified Files: src/sys/arch/arm/arm: cpufunc_asm_pj4b.S Log Message: set ttbr0/1 using correct register(r2). To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.5 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.6 --- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.5 Wed Oct 29 16:22:31 2014 +++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu Mar 26 08:50:42 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: cpufunc_asm_pj4b.S,v 1.5 2014/10/29 16:22:31 skrll Exp $ */ +/* $NetBSD: cpufunc_asm_pj4b.S,v 1.6 2015/03/26 08:50:42 hsuenaga Exp $ */ /*** Copyright (C) Marvell International Ltd. and its affiliates @@ -58,10 +58,10 @@ ENTRY(pj4b_setttb) #else bic r2, r0, #0x18 #endif - mcr p15, 0, r0, c2, c0, 0 /* load TTBR0 */ + mcr p15, 0, r2, c2, c0, 0 /* load TTBR0 */ #ifdef ARM_MMU_EXTENDED cmp r1, #0 - mcreq p15, 0, r0, c2, c0, 1 /* load TTBR1 */ + mcreq p15, 0, r2, c2, c0, 1 /* load TTBR1 */ #else mov r0, #0 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
CVS commit: src/distrib/notes/common
Module Name:src
Committed By: hsuenaga
Date: Fri Mar 28 08:24:06 UTC 2014
Modified Files:
src/distrib/notes/common: main
Log Message:
Added myself, hsuenaga
To generate a diff of this commit:
cvs rdiff -u -r1.508 -r1.509 src/distrib/notes/common/main
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/distrib/notes/common/main
diff -u src/distrib/notes/common/main:1.508 src/distrib/notes/common/main:1.509
--- src/distrib/notes/common/main:1.508 Thu Mar 13 03:34:00 2014
+++ src/distrib/notes/common/main Fri Mar 28 08:24:06 2014
@@ -1,4 +1,4 @@
-.\ $NetBSD: main,v 1.508 2014/03/13 03:34:00 nat Exp $
+.\ $NetBSD: main,v 1.509 2014/03/28 08:24:06 hsuenaga Exp $
.\
.\ Copyright (c) 1999-2012 The NetBSD Foundation, Inc.
.\ All rights reserved.
@@ -1387,6 +1387,7 @@ If you're one of them, and would like to
.It Ta Bill Squier Ta Mt g...@netbsd.org
.It Ta Adrian Steinmann Ta Mt a...@netbsd.org
.It Ta Bill Studenmund Ta Mt wrstu...@netbsd.org
+.It Ta Hiroki Suenaga Ta Mt hsuen...@netbsd.org
.It Ta Kevin Sullivan Ta Mt sulli...@netbsd.org
.It Ta Kimmo Suominen Ta Mt k...@netbsd.org
.It Ta Gr\('egoire Sutre Ta Mt gsu...@netbsd.org
CVS commit: src/distrib/notes/common
Module Name:src Committed By: hsuenaga Date: Fri Mar 28 08:24:06 UTC 2014 Modified Files: src/distrib/notes/common: main Log Message: Added myself, hsuenaga To generate a diff of this commit: cvs rdiff -u -r1.508 -r1.509 src/distrib/notes/common/main Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
