CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: tnn
Date: Sat Nov 11 17:35:45 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3_its: assorted minor improvements
- KASSERT that the command queue is not stalled due to async error
before issuing more commands.
- implement gits_command_int under #if 0 (useful for troubleshooting)
- protect command queue with its_lock consistently
- KASSERT for 32-bit MSI that upper bits are 0
- KASSERT return value of gicv3_its_msi_alloc_lpi
- KASSERT that safe conditions for writing to CBASER are met
- move CWRITER initialization to before CBASER
- fix alignment of tables for the 16KB page size case
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.34 src/sys/arch/arm/cortex/gicv3_its.c:1.35
--- src/sys/arch/arm/cortex/gicv3_its.c:1.34 Sun Oct 31 17:24:11 2021
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Nov 11 17:35:45 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.35 2023/11/11 17:35:45 tnn Exp $");
#include
#include
@@ -117,6 +117,11 @@ gits_command(struct gicv3_its *its, cons
cwriter = gits_read_8(its, GITS_CWRITER);
woff = cwriter & GITS_CWRITER_Offset;
+#ifdef DIAGNOSTIC
+ uint64_t creadr = gits_read_8(its, GITS_CREADR);
+ KASSERT(!ISSET(creadr, GITS_CREADR_Stalled));
+ KASSERT(((woff + sizeof(cmd->dw)) & (its->its_cmd.len - 1)) != (creadr & GITS_CREADR_Offset));
+#endif
uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff);
for (int i = 0; i < __arraycount(cmd->dw); i++)
@@ -256,6 +261,26 @@ gits_command_sync(struct gicv3_its *its,
gits_command(its, );
}
+#if 0
+static inline void
+gits_command_int(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid)
+{
+ struct gicv3_its_command cmd;
+
+ /*
+ * Translate the deviceid and eventid into an icid and pintid through
+ * the device table and ITT. Mark the pintid as pending
+ * on the redistributor.
+ * If the interrupt is not configured the command queue stalls.
+ */
+ memset(, 0, sizeof(cmd));
+ cmd.dw[0] = GITS_CMD_INT | ((uint64_t)deviceid << 32);
+ cmd.dw[1] = eventid;
+
+ gits_command(its, );
+}
+#endif
+
static inline int
gits_wait(struct gicv3_its *its)
{
@@ -358,8 +383,10 @@ gicv3_its_device_map(struct gicv3_its *i
* Map the device to the ITT
*/
const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
+ mutex_enter(its->its_lock);
gits_command_mapd(its, devid, dev->dev_itt.segs[0].ds_addr, id_bits - 1, true);
gits_wait(its);
+ mutex_exit(its->its_lock);
return 0;
}
@@ -391,6 +418,7 @@ gicv3_its_msi_enable(struct gicv3_its *i
pci_conf_write(pc, tag, off + PCI_MSI_MDATA64,
lpi - its->its_pic->pic_irqbase);
} else {
+ KASSERT((addr >> 32) == 0);
pci_conf_write(pc, tag, off + PCI_MSI_MADDR,
addr & 0x);
pci_conf_write(pc, tag, off + PCI_MSI_MDATA,
@@ -485,8 +513,10 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
return NULL;
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
+ mutex_enter(its->its_lock);
for (n = 0; n < *count; n++) {
const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
+ KASSERT(lpi >= 0);
vectors[n] = ARM_PCI_INTR_MSI |
__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
__SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
@@ -508,6 +538,7 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
+ mutex_exit(its->its_lock);
return vectors;
}
@@ -555,8 +586,10 @@ gicv3_its_msix_alloc(struct arm_pci_msi
}
vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
+ mutex_enter(its->its_lock);
for (n = 0; n < *count; n++) {
const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
+ KASSERT(lpi >= 0);
const int msix_vec = table_indexes ? table_indexes[n] : n;
vectors[msix_vec] = ARM_PCI_INTR_MSIX |
__SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
@@ -578,6 +611,7 @@ gicv3_its_msix_alloc(struct arm_pci_msi
gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
}
gits_wait(its);
+ mutex_exit(its->its_lock);
bus_space_unmap(bst, bsh, bsz);
@@ -638,14 +672,17 @@ gicv3_its_command_init(struct gicv3_soft
gicv3_dma_alloc(sc, >its_cmd, GITS_COMMANDS_SIZE, GITS_COMMANDS_ALIGN);
+ KASSERT((gits_read_4(its, GITS_CTLR) & GITS_CTLR_Enabled) == 0);
+ KASSERT((gits_read_4(its, GITS_CTLR) & GITS_CTLR_Quiescent) != 0);
+
cbaser = its->its_cmd.segs[0].ds_addr;
cbaser |=
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: tnn Date: Sat Nov 11 17:35:45 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: gicv3_its: assorted minor improvements - KASSERT that the command queue is not stalled due to async error before issuing more commands. - implement gits_command_int under #if 0 (useful for troubleshooting) - protect command queue with its_lock consistently - KASSERT for 32-bit MSI that upper bits are 0 - KASSERT return value of gicv3_its_msi_alloc_lpi - KASSERT that safe conditions for writing to CBASER are met - move CWRITER initialization to before CBASER - fix alignment of tables for the 16KB page size case To generate a diff of this commit: cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Thu Oct 5 12:30:59 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: arm/gic: Check l_blcnt, not l_biglocks. l_biglocks is a now-defunct temporary storage used only when sleeping; l_blcnt is the number of kernel locks held by the lwp when not sleeping. Should fix arm builds. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Thu Oct 5 12:30:59 UTC 2023 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: arm/gic: Check l_blcnt, not l_biglocks. l_biglocks is a now-defunct temporary storage used only when sleeping; l_blcnt is the number of kernel locks held by the lwp when not sleeping. Should fix arm builds. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.56 src/sys/arch/arm/cortex/gic.c:1.57 --- src/sys/arch/arm/cortex/gic.c:1.56 Sun Jun 26 11:14:36 2022 +++ src/sys/arch/arm/cortex/gic.c Thu Oct 5 12:30:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.56 2022/06/26 11:14:36 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.57 2023/10/05 12:30:59 riastradh Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.56 2022/06/26 11:14:36 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.57 2023/10/05 12:30:59 riastradh Exp $"); #include #include @@ -320,7 +320,7 @@ armgic_irq_handler(void *tf) struct armgic_softc * const sc = _softc; const int old_ipl = ci->ci_cpl; const int old_mtx_count = ci->ci_mtx_count; - const int old_l_biglocks = ci->ci_curlwp->l_biglocks; + const int old_l_blcnt = ci->ci_curlwp->l_blcnt; #ifdef DEBUG size_t n = 0; #endif @@ -407,7 +407,7 @@ armgic_irq_handler(void *tf) pic_do_pending_ints(I32_bit, old_ipl, tf); KASSERTMSG(ci->ci_cpl == old_ipl, "ci_cpl %d old_ipl %d", ci->ci_cpl, old_ipl); KASSERT(old_mtx_count == ci->ci_mtx_count); - KASSERT(old_l_biglocks == ci->ci_curlwp->l_biglocks); + KASSERT(old_l_blcnt == ci->ci_curlwp->l_blcnt); } void
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:12:26 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gtmr_var.h
Log Message:
G/C gtmr_init function declaration
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr_var.h
diff -u src/sys/arch/arm/cortex/gtmr_var.h:1.15 src/sys/arch/arm/cortex/gtmr_var.h:1.16
--- src/sys/arch/arm/cortex/gtmr_var.h:1.15 Fri Nov 12 21:59:04 2021
+++ src/sys/arch/arm/cortex/gtmr_var.h Sat Nov 19 12:12:25 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr_var.h,v 1.15 2021/11/12 21:59:04 jmcneill Exp $ */
+/* $NetBSD: gtmr_var.h,v 1.16 2022/11/19 12:12:25 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -51,7 +51,6 @@ struct gtmr_softc {
#ifdef _KERNEL
#include "opt_arm_timer.h"
struct cpu_info;
-void gtmr_init(device_t);
int gtmr_intr(void *);
void gtmr_init_cpu_clock(struct cpu_info *);
void gtmr_delay(unsigned int n);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 19 12:12:26 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gtmr_var.h Log Message: G/C gtmr_init function declaration To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Nov 5 17:30:20 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h
Log Message:
Handle speed change events
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9ptmr.c
diff -u src/sys/arch/arm/cortex/a9ptmr.c:1.2 src/sys/arch/arm/cortex/a9ptmr.c:1.3
--- src/sys/arch/arm/cortex/a9ptmr.c:1.2 Wed Aug 14 09:20:00 2019
+++ src/sys/arch/arm/cortex/a9ptmr.c Sat Nov 5 17:30:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $ */
+/* $NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -30,13 +30,14 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.2 2019/08/14 09:20:00 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9ptmr.c,v 1.3 2022/11/05 17:30:20 jmcneill Exp $");
#include
#include
#include
#include
#include
+#include
#include
@@ -265,3 +266,25 @@ a9ptmr_intr(void *arg)
return 1;
}
+
+static void
+a9ptmr_update_freq_cb(void *arg1, void *arg2)
+{
+ a9ptmr_init_cpu_clock(curcpu());
+}
+
+void
+a9ptmr_update_freq(uint32_t freq)
+{
+ struct a9ptmr_softc * const sc = a9ptmr_sc;
+ uint64_t xc;
+
+ KASSERT(sc->sc_dev != NULL);
+ KASSERT(freq != 0);
+
+ sc->sc_freq = freq;
+ sc->sc_load = (sc->sc_freq / hz) - 1;
+
+ xc = xc_broadcast(0, a9ptmr_update_freq_cb, NULL, NULL);
+ xc_wait(xc);
+}
Index: src/sys/arch/arm/cortex/a9ptmr_var.h
diff -u src/sys/arch/arm/cortex/a9ptmr_var.h:1.1 src/sys/arch/arm/cortex/a9ptmr_var.h:1.2
--- src/sys/arch/arm/cortex/a9ptmr_var.h:1.1 Sat Aug 10 17:03:59 2019
+++ src/sys/arch/arm/cortex/a9ptmr_var.h Sat Nov 5 17:30:20 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: a9ptmr_var.h,v 1.1 2019/08/10 17:03:59 skrll Exp $ */
+/* $NetBSD: a9ptmr_var.h,v 1.2 2022/11/05 17:30:20 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,6 +39,7 @@ struct cpu_info;
void a9ptmr_init_cpu_clock(struct cpu_info *);
int a9ptmr_intr(void *);
+void a9ptmr_update_freq(uint32_t);
void a9ptmr_delay(unsigned int n);
#endif
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Nov 5 17:30:20 UTC 2022 Modified Files: src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h Log Message: Handle speed change events To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/cortex/a9ptmr_var.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jun 25 18:05:09 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.52 src/sys/arch/arm/cortex/gicv3.c:1.53
--- src/sys/arch/arm/cortex/gicv3.c:1.52 Sat Jun 25 13:24:34 2022
+++ src/sys/arch/arm/cortex/gicv3.c Sat Jun 25 18:05:09 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.53 2022/06/25 18:05:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.52 2022/06/25 13:24:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.53 2022/06/25 18:05:09 jmcneill Exp $");
#include
#include
@@ -60,6 +60,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
#define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define IPL_TO_HWPL(ipl) ((ipl) >= IPL_VM ? (ipl) : IPL_NONE)
#define GIC_SUPPORTS_1OFN(sc) (((sc)->sc_gicd_typer & GICD_TYPER_No1N) == 0)
@@ -232,12 +233,13 @@ gicv3_set_priority(struct pic_softc *pic
{
struct gicv3_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
+ const int hwpl = IPL_TO_HWPL(ipl);
- while (ipl < ci->ci_hwpl) {
+ while (hwpl < ci->ci_hwpl) {
/* Lowering priority mask */
- ci->ci_hwpl = ipl;
+ ci->ci_hwpl = hwpl;
__insn_barrier();
- icc_pmr_write(IPL_TO_PMR(sc, ipl));
+ icc_pmr_write(IPL_TO_PMR(sc, hwpl));
}
__insn_barrier();
ci->ci_cpl = ipl;
@@ -729,13 +731,14 @@ gicv3_irq_handler(void *frame)
struct gicv3_softc * const sc = gicv3_softc;
struct pic_softc *pic;
const int oldipl = ci->ci_cpl;
+ const int oldhwpl = IPL_TO_HWPL(oldipl);
ci->ci_data.cpu_nintr++;
- if (ci->ci_hwpl != oldipl) {
- ci->ci_hwpl = oldipl;
- icc_pmr_write(IPL_TO_PMR(sc, oldipl));
- if (oldipl == IPL_HIGH) {
+ if (ci->ci_hwpl != oldhwpl) {
+ ci->ci_hwpl = oldhwpl;
+ icc_pmr_write(IPL_TO_PMR(sc, oldhwpl));
+ if (oldhwpl == IPL_HIGH) {
return;
}
}
@@ -760,6 +763,7 @@ gicv3_irq_handler(void *frame)
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
} else if (ci->ci_cpl != ipl) {
+ KASSERT(ipl >= IPL_VM);
icc_pmr_write(IPL_TO_PMR(sc, ipl));
ci->ci_hwpl = ci->ci_cpl = ipl;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jun 25 18:05:09 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings To generate a diff of this commit: cvs rdiff -u -r1.52 -r1.53 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Mon Mar 28 19:59:36 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: arm/cortex: Use container_of, not bespoke offsetof arithmetic. To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.49 src/sys/arch/arm/cortex/gicv3.c:1.50 --- src/sys/arch/arm/cortex/gicv3.c:1.49 Sat Oct 2 20:52:09 2021 +++ src/sys/arch/arm/cortex/gicv3.c Mon Mar 28 19:59:35 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $ */ +/* $NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.50 2022/03/28 19:59:35 riastradh Exp $"); #include #include @@ -58,9 +58,9 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1. #endif #define PICTOSOFTC(pic) \ - ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) + container_of(pic, struct gicv3_softc, sc_pic) #define LPITOSOFTC(lpi) \ - ((void *)((uintptr_t)(lpi) - offsetof(struct gicv3_softc, sc_lpi))) + container_of(lpi, struct gicv3_softc, sc_lpi) #define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff) #define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: riastradh Date: Mon Mar 28 19:59:36 UTC 2022 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: arm/cortex: Use container_of, not bespoke offsetof arithmetic. To generate a diff of this commit: cvs rdiff -u -r1.49 -r1.50 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Sat Nov 13 18:30:28 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: fix aarch64 build To generate a diff of this commit: cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jakllsch
Date: Sat Nov 13 18:30:28 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fix aarch64 build
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.47 src/sys/arch/arm/cortex/gtmr.c:1.48
--- src/sys/arch/arm/cortex/gtmr.c:1.47 Fri Nov 12 21:59:04 2021
+++ src/sys/arch/arm/cortex/gtmr.c Sat Nov 13 18:30:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.47 2021/11/12 21:59:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.48 2021/11/13 18:30:27 jakllsch Exp $");
#include
#include
@@ -257,9 +257,11 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
/* XXX hmm... called from cpu_hatch which hasn't lowered ipl yet */
int s = splsched();
+#if defined(__arm__)
if ((sc->sc_flags & GTMR_FLAG_CPU_REGISTERS_NOT_FW_CONFIGURED) != 0) {
armreg_cnt_frq_write(sc->sc_freq);
}
+#endif
/*
* Allow the virtual and physical counters to be accessed from
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Oct 31 17:24:11 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to
build for me without DIAGNOSTIC.
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.33 src/sys/arch/arm/cortex/gicv3_its.c:1.34
--- src/sys/arch/arm/cortex/gicv3_its.c:1.33 Sun Oct 31 16:23:47 2021
+++ src/sys/arch/arm/cortex/gicv3_its.c Sun Oct 31 17:24:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.33 2021/10/31 16:23:47 skrll Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.33 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.34 2021/10/31 17:24:11 skrll Exp $");
#include
#include
@@ -589,7 +589,6 @@ gicv3_its_msi_intr_establish(struct arm_
pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg, const char *xname)
{
struct gicv3_its * const its = msi->msi_priv;
- const struct pci_attach_args *pa;
void *intrh;
const int lpi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ);
@@ -601,8 +600,7 @@ gicv3_its_msi_intr_establish(struct arm_
return NULL;
/* Invalidate LPI configuration tables */
- pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
- KASSERT(pa != NULL);
+ KASSERT(its->its_pa[lpi - its->its_pic->pic_irqbase] != NULL);
const uint32_t devid = its->its_devid[lpi - its->its_pic->pic_irqbase];
gits_command_inv(its, devid, lpi - its->its_pic->pic_irqbase);
@@ -771,7 +769,6 @@ gicv3_its_cpu_init(void *priv, struct cp
{
struct gicv3_its * const its = priv;
struct gicv3_softc * const sc = its->its_gic;
- const struct pci_attach_args *pa;
uint64_t rdbase;
size_t irq;
@@ -798,8 +795,7 @@ gicv3_its_cpu_init(void *priv, struct cp
for (irq = 0; irq < its->its_pic->pic_maxsources; irq++) {
if (its->its_targets[irq] != ci)
continue;
- pa = its->its_pa[irq];
- KASSERT(pa != NULL);
+ KASSERT(its->its_pa[irq] != NULL);
const uint32_t devid = its->its_devid[irq];
gits_command_movi(its, devid, irq, cpu_index(ci));
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Oct 31 17:24:11 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to build for me without DIAGNOSTIC. To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Oct 31 15:32:14 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs_armv8.S
Log Message:
Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_splfuncs_armv8.S
diff -u src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.2 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.3
--- src/sys/arch/arm/cortex/gic_splfuncs_armv8.S:1.2 Sat Oct 30 20:23:12 2021
+++ src/sys/arch/arm/cortex/gic_splfuncs_armv8.S Sun Oct 31 15:32:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_splfuncs_armv8.S,v 1.2 2021/10/30 20:23:12 jmcneill Exp $ */
+/* $NetBSD: gic_splfuncs_armv8.S,v 1.3 2021/10/31 15:32:14 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -29,7 +29,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: gic_splfuncs_armv8.S,v 1.2 2021/10/30 20:23:12 jmcneill Exp $")
+RCSID("$NetBSD: gic_splfuncs_armv8.S,v 1.3 2021/10/31 15:32:14 jmcneill Exp $")
#ifdef __HAVE_PREEMPTION
#define DISABLE_PREEMPTION \
@@ -84,12 +84,12 @@ ENTRY_NP(gic_splx)
DISABLE_PREEMPTION
ldr x1, [x3, #L_CPU] /* get curcpu */
+.Lagain:
/* If newipl >= cpl, just return */
ldr w2, [x1, #CI_CPL]
cmp w0, w2
b.hs .Ldone
-.Lagain:
/* Slow path if ci_intr_depth != 0 */
ldr w2, [x1, #CI_INTR_DEPTH]
cbnz w2, .Lslow
@@ -120,9 +120,9 @@ ENTRY_NP(gic_splx)
ret
.Lrestart:
- /* Reload w0 and x1 */
- mrs x1, tpidr_el1 /* get curlwp */
- ldr x1, [x1, #L_CPU] /* get curcpu */
+ /* Reload registers */
+ mrs x3, tpidr_el1 /* get curlwp */
+ ldr x1, [x3, #L_CPU] /* get curcpu */
ldr w0, [x1, #CI_SPLX_SAVEDIPL] /* get newipl */
b .Lagain
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Oct 31 15:32:14 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic_splfuncs_armv8.S Log Message: Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_splfuncs_armv8.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Thu Oct 21 04:47:57 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix some conditionals to match gicv3 and add some comments to describe
what's going on.
Fixes PR port-evbarm/56420
To generate a diff of this commit:
cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.50 src/sys/arch/arm/cortex/gic.c:1.51
--- src/sys/arch/arm/cortex/gic.c:1.50 Sun Sep 26 13:38:50 2021
+++ src/sys/arch/arm/cortex/gic.c Thu Oct 21 04:47:57 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.50 2021/09/26 13:38:50 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.51 2021/10/21 04:47:57 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -35,7 +35,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.50 2021/09/26 13:38:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.51 2021/10/21 04:47:57 skrll Exp $");
#include
#include
@@ -331,9 +331,17 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
- if (ci->ci_hwpl != old_ipl) {
+ /*
+ * Raise ci_hwpl (and PMR) to ci_cpl and IAR will tell us if the
+ * interrupt that got us here can have its handler run or not.
+ */
+ if (ci->ci_hwpl <= old_ipl) {
ci->ci_hwpl = old_ipl;
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));
+ /*
+ * we'll get no interrupts when PMR is IPL_HIGH, so bail
+ * early.
+ */
if (old_ipl == IPL_HIGH) {
return;
}
@@ -373,11 +381,13 @@ armgic_irq_handler(void *tf)
*
* However, if are just raising ipl, we can just update ci_cpl.
*/
+
+ /* Surely we can KASSERT(ipl < ci->ci_cpl); */
const int ipl = is->is_ipl;
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, tf);
KASSERT(ci->ci_cpl == ipl);
- } else {
+ } else if (ci->ci_cpl != ipl) {
KASSERTMSG(ipl > ci->ci_cpl, "ipl %d cpl %d hw-ipl %#x",
ipl, ci->ci_cpl,
gicc_read(sc, GICC_PMR));
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Thu Oct 21 04:47:57 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Fix some conditionals to match gicv3 and add some comments to describe what's going on. Fixes PR port-evbarm/56420 To generate a diff of this commit: cvs rdiff -u -r1.50 -r1.51 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sat Oct 2 20:52:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c
pl310.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9tmr_reg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S
cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/pl310.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9tmr_reg.h
diff -u src/sys/arch/arm/cortex/a9tmr_reg.h:1.2 src/sys/arch/arm/cortex/a9tmr_reg.h:1.3
--- src/sys/arch/arm/cortex/a9tmr_reg.h:1.2 Sat Jul 27 07:02:09 2019
+++ src/sys/arch/arm/cortex/a9tmr_reg.h Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_reg.h,v 1.2 2019/07/27 07:02:09 skrll Exp $ */
+/* $NetBSD: a9tmr_reg.h,v 1.3 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -87,7 +87,7 @@
#define TMR_GBL_CTL_PRESCALER __BIT(15,8)
#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled
#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled
-#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
+#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
#define TMR_GBL_CTL_ENABLE __BIT(0)
#endif /* !_ARM_CORTEX_A9TMR_REG_H_ */
Index: src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S
diff -u src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.3 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.4
--- src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S:1.3 Sat Dec 22 18:58:29 2012
+++ src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S Sat Oct 2 20:52:09 2021
@@ -29,7 +29,7 @@
#include
-RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.3 2012/12/22 18:58:29 matt Exp $")
+RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.4 2021/10/02 20:52:09 skrll Exp $")
/*
* uint32_t
@@ -52,7 +52,7 @@ ENTRY(cpu_in_cksum_neon)
* Normally the lower addressed is in d6 but in this case we want to
* reverse it since we might only have a single dword and the final
* fold will want the dword to trim in d7 so put the first dword in
- * d7 until we know we are going to read more than one.
+ * d7 until we know we are going to read more than one.
*/
veor d6, d6, d6 /* clear second dword */
vld1.64 {d7}, [ip:64]! /* load first dword */
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.48 src/sys/arch/arm/cortex/gicv3.c:1.49
--- src/sys/arch/arm/cortex/gicv3.c:1.48 Sun Sep 26 13:38:50 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $");
#include
#include
@@ -837,7 +837,7 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
/*
* If we see fewer PMR bits than IPRIORITYRn bits here, it means
* we have a secure view of IPRIORITYRn (this is not supposed to
- * happen!).
+ * happen!).
*/
if (pmrbits < pribits) {
aprint_verbose_dev(sc->sc_dev,
Index: src/sys/arch/arm/cortex/pl310.c
diff -u src/sys/arch/arm/cortex/pl310.c:1.19 src/sys/arch/arm/cortex/pl310.c:1.20
--- src/sys/arch/arm/cortex/pl310.c:1.19 Sat Jan 19 20:52:26 2019
+++ src/sys/arch/arm/cortex/pl310.c Sat Oct 2 20:52:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $ */
+/* $NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $");
#include
#include
@@ -157,7 +157,7 @@ arml2cc_attach(device_t parent, device_t
mutex_init(>sc_lock, MUTEX_DEFAULT, IPL_HIGH);
- bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
off, L2CC_SIZE, >sc_memh);
uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Oct 2 20:52:09 UTC 2021 Modified Files: src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c pl310.c Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9tmr_reg.h cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/pl310.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Sep 26 20:55:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs.c
Log Message:
Add missing insn barrier
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_splfuncs.c
diff -u src/sys/arch/arm/cortex/gic_splfuncs.c:1.3 src/sys/arch/arm/cortex/gic_splfuncs.c:1.4
--- src/sys/arch/arm/cortex/gic_splfuncs.c:1.3 Mon Sep 20 21:05:14 2021
+++ src/sys/arch/arm/cortex/gic_splfuncs.c Sun Sep 26 20:55:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_splfuncs.c,v 1.3 2021/09/20 21:05:14 jmcneill Exp $ */
+/* $NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $ */
/*-
* Copyright (c) 2021 Jared McNeill
@@ -27,7 +27,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_splfuncs.c,v 1.3 2021/09/20 21:05:14 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_splfuncs.c,v 1.4 2021/09/26 20:55:15 jmcneill Exp $");
#include
#include
@@ -93,6 +93,7 @@ gic_splx(int newipl)
*/
if (__predict_true(ci->ci_intr_depth == 0)) {
ci->ci_splx_savedipl = newipl;
+ __insn_barrier();
ci->ci_splx_restart = &
__insn_barrier();
checkhwpl:
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Sep 26 20:55:15 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic_splfuncs.c Log Message: Add missing insn barrier To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Sep 11 01:49:12 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
GIC: Support SPI affinity routing before secondary CPUs have hatched.
Instead of reading MPIDR from CPU init to determine a routing target, trust
system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid.
This allows for SPI affinity routing to work before secondary CPUs are
hatched; previously, one of two things would happen:
a) If 1ofN distribution is supported, the SPI could be distributed to any
participating PE.
b) If 1ofN distribution is not supported, the SPI would not be forwarded
and would stay pending.
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.46 src/sys/arch/arm/cortex/gicv3.c:1.47
--- src/sys/arch/arm/cortex/gicv3.c:1.46 Tue Aug 10 17:12:31 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sat Sep 11 01:49:11 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.47 2021/09/11 01:49:11 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.47 2021/09/11 01:49:11 jmcneill Exp $");
#include
#include
@@ -402,18 +402,6 @@ gicv3_cpu_init(struct pic_softc *pic, st
ci->ci_gic_redist = gicv3_find_redist(sc);
ci->ci_gic_sgir = gicv3_sgir(sc);
- /* Store route to CPU for SPIs */
- const uint64_t cpu_identity = gicv3_cpu_identity();
- const u_int aff0 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff0);
- const u_int aff1 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff1);
- const u_int aff2 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff2);
- const u_int aff3 = __SHIFTOUT(cpu_identity, GICR_TYPER_Affinity_Value_Aff3);
- sc->sc_irouter[cpu_index(ci)] =
- __SHIFTIN(aff0, GICD_IROUTER_Aff0) |
- __SHIFTIN(aff1, GICD_IROUTER_Aff1) |
- __SHIFTIN(aff2, GICD_IROUTER_Aff2) |
- __SHIFTIN(aff3, GICD_IROUTER_Aff3);
-
/* Enable System register access and disable IRQ/FIQ bypass */
icc_sre = ICC_SRE_EL1_SRE | ICC_SRE_EL1_DFB | ICC_SRE_EL1_DIB;
icc_sre_write(icc_sre);
@@ -482,8 +470,7 @@ gicv3_get_affinity(struct pic_softc *pic
if (group == 0) {
/* All CPUs are targets for group 0 (SGI/PPI) */
for (n = 0; n < ncpu; n++) {
- if (sc->sc_irouter[n] != UINT64_MAX)
-kcpuset_set(affinity, n);
+ kcpuset_set(affinity, n);
}
} else {
/* Find distributor targets (SPI) */
@@ -861,15 +848,19 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
int
gicv3_init(struct gicv3_softc *sc)
{
- int n;
+ CPU_INFO_ITERATOR cii;
+ struct cpu_info *ci;
KASSERT(CPU_IS_PRIMARY(curcpu()));
LIST_INIT(>sc_lpi_callbacks);
+ /* Store route to CPU for SPIs */
sc->sc_irouter = kmem_zalloc(sizeof(*sc->sc_irouter) * ncpu, KM_SLEEP);
- for (n = 0; n < ncpu; n++)
- sc->sc_irouter[n] = UINT64_MAX;
+ for (CPU_INFO_FOREACH(cii, ci)) {
+ KASSERT(cpu_index(ci) < ncpu);
+ sc->sc_irouter[cpu_index(ci)] = ci->ci_cpuid;
+ }
sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Sep 11 01:49:12 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: GIC: Support SPI affinity routing before secondary CPUs have hatched. Instead of reading MPIDR from CPU init to determine a routing target, trust system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid. This allows for SPI affinity routing to work before secondary CPUs are hatched; previously, one of two things would happen: a) If 1ofN distribution is supported, the SPI could be distributed to any participating PE. b) If 1ofN distribution is not supported, the SPI would not be forwarded and would stay pending. To generate a diff of this commit: cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Sep 9 21:39:03 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
If we get a spurious interrupt, log a debug message and ignore it.
Otherwise we risk tripping an assertion later on due to an interrupt
firing before it is scheduled.
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.44 src/sys/arch/arm/cortex/gtmr.c:1.45
--- src/sys/arch/arm/cortex/gtmr.c:1.44 Mon Aug 30 22:53:37 2021
+++ src/sys/arch/arm/cortex/gtmr.c Thu Sep 9 21:39:02 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.45 2021/09/09 21:39:02 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.45 2021/09/09 21:39:02 jmcneill Exp $");
#include
#include
@@ -334,6 +334,12 @@ gtmr_intr(void *arg)
struct clockframe * const cf = arg;
struct gtmr_softc * const sc = _sc;
+ const uint32_t ctl = gtmr_read_ctl(sc);
+ if ((ctl & (CNTCTL_ENABLE|CNTCTL_ISTATUS)) != (CNTCTL_ENABLE|CNTCTL_ISTATUS)) {
+ aprint_debug_dev(ci->ci_dev, "spurious timer interrupt (ctl=%#x)\n", ctl);
+ return 0;
+ }
+
const uint64_t now = gtmr_read_cntct(sc);
uint64_t delta = now - ci->ci_lastintr;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Sep 9 21:39:03 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: If we get a spurious interrupt, log a debug message and ignore it. Otherwise we risk tripping an assertion later on due to an interrupt firing before it is scheduled. To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Aug 30 22:53:37 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
- Add an isb before cnt[pv]_ctl read
- cntk_ctl is 64-bits
- Do not toggle CNTCTL_IMASK in intr handler, as this may be needed
elsewhere.
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.43 src/sys/arch/arm/cortex/gtmr.c:1.44
--- src/sys/arch/arm/cortex/gtmr.c:1.43 Mon Jan 18 23:43:34 2021
+++ src/sys/arch/arm/cortex/gtmr.c Mon Aug 30 22:53:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $ */
+/* $NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.44 2021/08/30 22:53:37 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.4
#include
#include
#include
+#include
#include
@@ -195,6 +196,8 @@ gtmr_read_cntct(struct gtmr_softc *sc)
static uint32_t
gtmr_read_ctl(struct gtmr_softc *sc)
{
+ isb();
+
if (sc->sc_physical)
return gtmr_cntp_ctl_read();
else
@@ -239,7 +242,8 @@ void
gtmr_init_cpu_clock(struct cpu_info *ci)
{
struct gtmr_softc * const sc = _sc;
- uint32_t val;
+ uint32_t cntk;
+ uint64_t ctl;
KASSERT(ci == curcpu());
@@ -249,29 +253,34 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
* Allow the virtual and physical counters to be accessed from
* usermode. (PL0)
*/
- val = gtmr_cntk_ctl_read();
- val &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN);
+ cntk = gtmr_cntk_ctl_read();
+ cntk &= ~(CNTKCTL_PL0PTEN | CNTKCTL_PL0VTEN | CNTKCTL_EVNTEN);
if (sc->sc_physical) {
- val |= CNTKCTL_PL0PCTEN;
- val &= ~CNTKCTL_PL0VCTEN;
+ cntk |= CNTKCTL_PL0PCTEN;
+ cntk &= ~CNTKCTL_PL0VCTEN;
} else {
- val |= CNTKCTL_PL0VCTEN;
- val &= ~CNTKCTL_PL0PCTEN;
+ cntk |= CNTKCTL_PL0VCTEN;
+ cntk &= ~CNTKCTL_PL0PCTEN;
}
- gtmr_cntk_ctl_write(val);
+ gtmr_cntk_ctl_write(cntk);
isb();
/*
* enable timer and stop masking the timer.
*/
- gtmr_write_ctl(sc, CNTCTL_ENABLE);
+ ctl = gtmr_read_ctl(sc);
+ ctl &= ~CNTCTL_IMASK;
+ ctl |= CNTCTL_ENABLE;
+ gtmr_write_ctl(sc, ctl);
/*
* Get now and update the compare timer.
*/
ci->ci_lastintr = gtmr_read_cntct(sc);
gtmr_write_tval(sc, sc->sc_autoinc);
+
splx(s);
+
KASSERT(gtmr_read_cntct(sc) != 0);
}
@@ -324,14 +333,6 @@ gtmr_intr(void *arg)
struct cpu_info * const ci = curcpu();
struct clockframe * const cf = arg;
struct gtmr_softc * const sc = _sc;
- uint32_t ctl;
-
- ctl = gtmr_read_ctl(sc);
- if ((ctl & CNTCTL_ISTATUS) == 0)
- return 0;
-
- ctl |= CNTCTL_IMASK;
- gtmr_write_ctl(sc, ctl);
const uint64_t now = gtmr_read_cntct(sc);
uint64_t delta = now - ci->ci_lastintr;
@@ -371,11 +372,6 @@ gtmr_intr(void *arg)
gtmr_write_tval(sc, sc->sc_autoinc - delta);
}
- ctl = gtmr_read_ctl(sc);
- ctl &= ~CNTCTL_IMASK;
- ctl |= CNTCTL_ENABLE;
- gtmr_write_ctl(sc, ctl);
-
ci->ci_lastintr = now;
#ifdef DIAGNOSTIC
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Aug 30 22:53:37 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: - Add an isb before cnt[pv]_ctl read - cntk_ctl is 64-bits - Do not toggle CNTCTL_IMASK in intr handler, as this may be needed elsewhere. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Aug 10 17:12:31 UTC 2021 Modified Files: src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c Log Message: Make gic_splfuncs optional and disable it by default until it has had more testing. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gic.c cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/files.cortex diff -u src/sys/arch/arm/cortex/files.cortex:1.15 src/sys/arch/arm/cortex/files.cortex:1.16 --- src/sys/arch/arm/cortex/files.cortex:1.15 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/files.cortex Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -# $NetBSD: files.cortex,v 1.15 2021/08/10 15:33:09 jmcneill Exp $ +# $NetBSD: files.cortex,v 1.16 2021/08/10 17:12:31 jmcneill Exp $ defflag opt_cpu_in_cksum.h NEON_IN_CKSUM @@ -11,16 +11,16 @@ device armperiph: mpcorebus attach armperiph at mainbus file arch/arm/cortex/armperiph.c armperiph -define gic_splfuncs +defflag opt_gic.hGIC_SPLFUNCS file arch/arm/cortex/gic_splfuncs.c gic_splfuncs # ARM Generic Interrupt Controller (initially on Cortex-A9) -device armgic: pic, pic_splfuncs, gic_splfuncs +device armgic: pic, pic_splfuncs attach armgic at mpcorebus file arch/arm/cortex/gic.c armgic # ARM Generic Interrupt Controller v3+ -device gicvthree: pic, pic_splfuncs, gic_splfuncs +device gicvthree: pic, pic_splfuncs file arch/arm/cortex/gicv3.c gicvthree file arch/arm/cortex/gicv3_its.c gicvthree & pci & __have_pci_msi_msix Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.48 src/sys/arch/arm/cortex/gic.c:1.49 --- src/sys/arch/arm/cortex/gic.c:1.48 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/gic.c Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $ */ +/* $NetBSD: gic.c,v 1.49 2021/08/10 17:12:31 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -30,11 +30,12 @@ #include "opt_ddb.h" #include "opt_multiprocessor.h" +#include "opt_gic.h" #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.49 2021/08/10 17:12:31 jmcneill Exp $"); #include #include @@ -50,9 +51,12 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 #include #include -#include #include +#ifdef GIC_SPLFUNCS +#include +#endif + void armgic_irq_handler(void *); #define ARMGIC_SGI_IPIBASE 0 @@ -730,7 +734,9 @@ armgic_attach(device_t parent, device_t "%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis, sgis); +#ifdef GIC_SPLFUNCS gic_spl_init(); +#endif } CFATTACH_DECL_NEW(armgic, 0, Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.45 src/sys/arch/arm/cortex/gicv3.c:1.46 --- src/sys/arch/arm/cortex/gicv3.c:1.45 Tue Aug 10 15:33:09 2021 +++ src/sys/arch/arm/cortex/gicv3.c Tue Aug 10 17:12:31 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -27,11 +27,12 @@ */ #include "opt_multiprocessor.h" +#include "opt_gic.h" #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.46 2021/08/10 17:12:31 jmcneill Exp $"); #include #include @@ -51,7 +52,10 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1. #include #include + +#ifdef GIC_SPLFUNCS #include +#endif #define PICTOSOFTC(pic) \ ((void *)((uintptr_t)(pic) - offsetof(struct gicv3_softc, sc_pic))) @@ -952,7 +956,9 @@ gicv3_init(struct gicv3_softc *sc) #endif #endif +#ifdef GIC_SPLFUNCS gic_spl_init(); +#endif return 0; }
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Aug 10 17:12:31 UTC 2021 Modified Files: src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c Log Message: Make gic_splfuncs optional and disable it by default until it has had more testing. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r1.48 -r1.49 src/sys/arch/arm/cortex/gic.c cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Aug 10 15:33:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c
Added Files:
src/sys/arch/arm/cortex: gic_splfuncs.c gic_splfuncs.h
Log Message:
Use custom spl funcs for GIC and avoid unnecessary pmr register accesses
in splx.
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gic_splfuncs.c \
src/sys/arch/arm/cortex/gic_splfuncs.h
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.14 src/sys/arch/arm/cortex/files.cortex:1.15
--- src/sys/arch/arm/cortex/files.cortex:1.14 Tue Sep 29 19:58:50 2020
+++ src/sys/arch/arm/cortex/files.cortex Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.14 2020/09/29 19:58:50 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.15 2021/08/10 15:33:09 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -11,13 +11,16 @@ device armperiph: mpcorebus
attach armperiph at mainbus
file arch/arm/cortex/armperiph.c armperiph
+define gic_splfuncs
+file arch/arm/cortex/gic_splfuncs.c gic_splfuncs
+
# ARM Generic Interrupt Controller (initially on Cortex-A9)
-device armgic: pic, pic_splfuncs
+device armgic: pic, pic_splfuncs, gic_splfuncs
attach armgic at mpcorebus
file arch/arm/cortex/gic.c armgic
# ARM Generic Interrupt Controller v3+
-device gicvthree: pic, pic_splfuncs
+device gicvthree: pic, pic_splfuncs, gic_splfuncs
file arch/arm/cortex/gicv3.c gicvthree
file arch/arm/cortex/gicv3_its.c gicvthree & pci & __have_pci_msi_msix
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.47 src/sys/arch/arm/cortex/gic.c:1.48
--- src/sys/arch/arm/cortex/gic.c:1.47 Sun Mar 28 09:11:38 2021
+++ src/sys/arch/arm/cortex/gic.c Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $ */
+/* $NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.48 2021/08/10 15:33:09 jmcneill Exp $");
#include
#include
@@ -50,6 +50,7 @@ __KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47
#include
#include
+#include
#include
void armgic_irq_handler(void *);
@@ -224,11 +225,10 @@ armgic_set_priority(struct pic_softc *pi
struct armgic_softc * const sc = PICTOSOFTC(pic);
struct cpu_info * const ci = curcpu();
- const uint32_t priority = armgic_ipl_to_priority(ipl);
- if (priority > ci->ci_hwpl) {
+ if (ipl < ci->ci_hwpl) {
/* Lowering priority mask */
- ci->ci_hwpl = priority;
- gicc_write(sc, GICC_PMR, priority);
+ ci->ci_hwpl = ipl;
+ gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
}
}
@@ -327,10 +327,9 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
- const uint32_t priority = armgic_ipl_to_priority(old_ipl);
- if (ci->ci_hwpl != priority) {
- ci->ci_hwpl = priority;
- gicc_write(sc, GICC_PMR, priority);
+ if (ci->ci_hwpl != old_ipl) {
+ ci->ci_hwpl = old_ipl;
+ gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(old_ipl));
if (old_ipl == IPL_HIGH) {
return;
}
@@ -545,7 +544,7 @@ armgic_cpu_init(struct pic_softc *pic, s
sc->sc_enabled_local);
}
}
- ci->ci_hwpl = armgic_ipl_to_priority(ci->ci_cpl);
+ ci->ci_hwpl = ci->ci_cpl;
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR
gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
ENABLE_INTERRUPT();// allow IRQ exceptions
@@ -730,6 +729,8 @@ armgic_attach(device_t parent, device_t
aprint_normal_dev(sc->sc_dev, "%u Priorities, %zu SPIs, %u PPIs, "
"%u SGIs\n", priorities, sc->sc_gic_lines - ppis - sgis, ppis,
sgis);
+
+ gic_spl_init();
}
CFATTACH_DECL_NEW(armgic, 0,
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.44 src/sys/arch/arm/cortex/gicv3.c:1.45
--- src/sys/arch/arm/cortex/gicv3.c:1.44 Sun Mar 28 11:13:24 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Aug 10 15:33:09 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.45 2021/08/10 15:33:09 jmcneill Exp $");
#include
#include
@@ -51,6 +51,7 @@ __KERNEL_RCSID(0, "$NetBSD:
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Aug 10 15:33:09 UTC 2021 Modified Files: src/sys/arch/arm/cortex: files.cortex gic.c gicv3.c Added Files: src/sys/arch/arm/cortex: gic_splfuncs.c gic_splfuncs.h Log Message: Use custom spl funcs for GIC and avoid unnecessary pmr register accesses in splx. To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gic.c cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gic_splfuncs.c \ src/sys/arch/arm/cortex/gic_splfuncs.h cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Mar 28 11:13:24 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Disable 1ofN distribution of SPIs by default. This is a workaround for an
issue in the USB stack -- signaling transfer complete on multiple PEs can
cause transfer completions to be processed out of order.
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.43 src/sys/arch/arm/cortex/gicv3.c:1.44
--- src/sys/arch/arm/cortex/gicv3.c:1.43 Tue Feb 23 10:03:04 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sun Mar 28 11:13:24 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
#include
#include
@@ -65,6 +65,13 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define GIC_PRIO_SHIFT_NS 4
#define GIC_PRIO_SHIFT_S 3
+/*
+ * Set to true if you want to use 1 of N interrupt distribution for SPIs
+ * when available. Disabled by default because it causes issues with the
+ * USB stack.
+ */
+bool gicv3_use_1ofn = false;
+
static struct gicv3_softc *gicv3_softc;
static inline uint32_t
@@ -195,7 +202,7 @@ gicv3_establish_irq(struct pic_softc *pi
* If 1 of N SPI routing is supported, route MP-safe interrupts to all
* participating PEs. Otherwise, just route to the primary PE.
*/
- if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
+ if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
irouter = sc->sc_irouter[0];
@@ -498,7 +505,7 @@ gicv3_set_affinity(struct pic_softc *pic
const int set = kcpuset_countset(affinity);
if (set == 1) {
irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
- } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
+ } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
return EINVAL;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Mar 28 11:13:24 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Disable 1ofN distribution of SPIs by default. This is a workaround for an issue in the USB stack -- signaling transfer complete on multiple PEs can cause transfer completions to be processed out of order. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Mar 28 09:11:38 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Only target the boot cpu for real with SPI interrupts. I tried to do
this back in 2014, but somehow I missed a spot.
This is a quick-and-dirty fix for the USB stack which expects transfer
completions to be in-order. If interrupts happen across the CPUs then
this isn't guaranteed (yet).
kern/55243 panic at usb_transfer_complete() on raspberry pi 4
To generate a diff of this commit:
cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.46 src/sys/arch/arm/cortex/gic.c:1.47
--- src/sys/arch/arm/cortex/gic.c:1.46 Tue Feb 23 10:03:04 2021
+++ src/sys/arch/arm/cortex/gic.c Sun Mar 28 09:11:38 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.47 2021/03/28 09:11:38 skrll Exp $");
#include
#include
@@ -517,7 +517,11 @@ armgic_cpu_init_targets(struct armgic_so
if (is != NULL && is->is_mpsafe) {
const u_int byte_shift = 8 * (irq & 3);
uint32_t targets = gicd_read(sc, targets_reg);
+#if 0
targets |= sc->sc_mptargets << byte_shift;
+#else
+ targets |= sc->sc_bptargets << byte_shift;
+#endif
gicd_write(sc, targets_reg, targets);
}
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Mar 28 09:11:38 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Only target the boot cpu for real with SPI interrupts. I tried to do this back in 2014, but somehow I missed a spot. This is a quick-and-dirty fix for the USB stack which expects transfer completions to be in-order. If interrupts happen across the CPUs then this isn't guaranteed (yet). kern/55243 panic at usb_transfer_complete() on raspberry pi 4 To generate a diff of this commit: cvs rdiff -u -r1.46 -r1.47 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Mar 14 08:09:20 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
Remove an unnecessary if statement in gic_v2m_msi_alloc when finding a
'count' that fits the available.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gic_v2m.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.10 src/sys/arch/arm/cortex/gic_v2m.c:1.11
--- src/sys/arch/arm/cortex/gic_v2m.c:1.10 Fri Dec 11 21:40:50 2020
+++ src/sys/arch/arm/cortex/gic_v2m.c Sun Mar 14 08:09:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.11 2021/03/14 08:09:20 skrll Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.11 2021/03/14 08:09:20 skrll Exp $");
#include
#include
@@ -240,10 +240,9 @@ gic_v2m_msi_alloc(struct arm_pci_msi *ms
if (exact && *count > avail)
return NULL;
- while (*count > avail) {
- if (avail < *count)
- (*count) >>= 1;
- }
+ while (*count > avail)
+ (*count) >>= 1;
+
if (*count == 0)
return NULL;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Mar 14 08:09:20 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c Log Message: Remove an unnecessary if statement in gic_v2m_msi_alloc when finding a 'count' that fits the available. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gic_v2m.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Feb 23 10:03:05 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c gicv3.c Log Message: If we are committing a deferred splhigh() to hardware, no need to continue. To generate a diff of this commit: cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gic.c cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Feb 23 10:03:05 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c gicv3.c
Log Message:
If we are committing a deferred splhigh() to hardware, no need to continue.
To generate a diff of this commit:
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/arm/cortex/gic.c
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.45 src/sys/arch/arm/cortex/gic.c:1.46
--- src/sys/arch/arm/cortex/gic.c:1.45 Sun Feb 21 15:45:30 2021
+++ src/sys/arch/arm/cortex/gic.c Tue Feb 23 10:03:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.46 2021/02/23 10:03:04 jmcneill Exp $");
#include
#include
@@ -331,6 +331,9 @@ armgic_irq_handler(void *tf)
if (ci->ci_hwpl != priority) {
ci->ci_hwpl = priority;
gicc_write(sc, GICC_PMR, priority);
+ if (old_ipl == IPL_HIGH) {
+ return;
+ }
}
for (;;) {
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.42 src/sys/arch/arm/cortex/gicv3.c:1.43
--- src/sys/arch/arm/cortex/gicv3.c:1.42 Sun Feb 21 15:00:05 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Feb 23 10:03:04 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.42 2021/02/21 15:00:05 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.42 2021/02/21 15:00:05 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
#include
#include
@@ -738,6 +738,9 @@ gicv3_irq_handler(void *frame)
if (ci->ci_hwpl != pmr) {
ci->ci_hwpl = pmr;
icc_pmr_write(pmr);
+ if (oldipl == IPL_HIGH) {
+ return;
+ }
}
for (;;) {
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Feb 21 15:45:30 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Apply PMR optimizations from gicv3
To generate a diff of this commit:
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.44 src/sys/arch/arm/cortex/gic.c:1.45
--- src/sys/arch/arm/cortex/gic.c:1.44 Tue Feb 9 14:24:14 2021
+++ src/sys/arch/arm/cortex/gic.c Sun Feb 21 15:45:30 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $ */
+/* $NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.45 2021/02/21 15:45:30 jmcneill Exp $");
#include
#include
@@ -222,9 +222,14 @@ static void
armgic_set_priority(struct pic_softc *pic, int ipl)
{
struct armgic_softc * const sc = PICTOSOFTC(pic);
+ struct cpu_info * const ci = curcpu();
const uint32_t priority = armgic_ipl_to_priority(ipl);
- gicc_write(sc, GICC_PMR, priority);
+ if (priority > ci->ci_hwpl) {
+ /* Lowering priority mask */
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
}
#ifdef MULTIPROCESSOR
@@ -322,6 +327,12 @@ armgic_irq_handler(void *tf)
ci->ci_data.cpu_nintr++;
+ const uint32_t priority = armgic_ipl_to_priority(old_ipl);
+ if (ci->ci_hwpl != priority) {
+ ci->ci_hwpl = priority;
+ gicc_write(sc, GICC_PMR, priority);
+ }
+
for (;;) {
uint32_t iar = gicc_read(sc, GICC_IAR);
uint32_t irq = __SHIFTOUT(iar, GICC_IAR_IRQ);
@@ -365,7 +376,7 @@ armgic_irq_handler(void *tf)
ipl, ci->ci_cpl,
gicc_read(sc, GICC_PMR));
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl));
- ci->ci_cpl = ipl;
+ ci->ci_hwpl = ci->ci_cpl = ipl;
}
ENABLE_INTERRUPT();
pic_dispatch(is, tf);
@@ -527,6 +538,7 @@ armgic_cpu_init(struct pic_softc *pic, s
sc->sc_enabled_local);
}
}
+ ci->ci_hwpl = armgic_ipl_to_priority(ci->ci_cpl);
gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR
gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt
ENABLE_INTERRUPT();// allow IRQ exceptions
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Feb 21 15:45:30 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Apply PMR optimizations from gicv3 To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: ryo
Date: Tue Feb 9 17:44:01 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
fix build without MULTIPROCESSOR
To generate a diff of this commit:
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.40 src/sys/arch/arm/cortex/gicv3.c:1.41
--- src/sys/arch/arm/cortex/gicv3.c:1.40 Sun Feb 7 21:24:50 2021
+++ src/sys/arch/arm/cortex/gicv3.c Tue Feb 9 17:44:01 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.41 2021/02/09 17:44:01 ryo Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.41 2021/02/09 17:44:01 ryo Exp $");
#include
#include
@@ -79,11 +79,13 @@ gicd_write_4(struct gicv3_softc *sc, bus
bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);
}
+#ifdef MULTIPROCESSOR
static inline uint64_t
gicd_read_8(struct gicv3_softc *sc, bus_size_t reg)
{
return bus_space_read_8(sc->sc_bst, sc->sc_bsh_d, reg);
}
+#endif
static inline void
gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: ryo Date: Tue Feb 9 17:44:01 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: fix build without MULTIPROCESSOR To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Tue Feb 9 14:24:14 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.43 src/sys/arch/arm/cortex/gic.c:1.44 --- src/sys/arch/arm/cortex/gic.c:1.43 Thu Dec 3 07:45:52 2020 +++ src/sys/arch/arm/cortex/gic.c Tue Feb 9 14:24:14 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $ */ +/* $NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.43 2020/12/03 07:45:52 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.44 2021/02/09 14:24:14 jakllsch Exp $"); #include #include @@ -367,9 +367,9 @@ armgic_irq_handler(void *tf) gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ipl)); ci->ci_cpl = ipl; } - cpsie(I32_bit); + ENABLE_INTERRUPT(); pic_dispatch(is, tf); - cpsid(I32_bit); + DISABLE_INTERRUPT(); gicc_write(sc, GICC_EOIR, iar); #ifdef DEBUG n++; @@ -529,7 +529,7 @@ armgic_cpu_init(struct pic_softc *pic, s } gicc_write(sc, GICC_PMR, armgic_ipl_to_priority(ci->ci_cpl)); // set PMR gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable interrupt - cpsie(I32_bit); // allow IRQ exceptions + ENABLE_INTERRUPT();// allow IRQ exceptions } void @@ -656,7 +656,7 @@ armgic_attach(device_t parent, device_t armgic_set_priority(>sc_pic, ci->ci_cpl); // set PMR gicd_write(sc, GICD_CTRL, GICD_CTRL_Enable); // enable Distributer gicc_write(sc, GICC_CTRL, GICC_CTRL_V1_Enable); // enable CPU interrupts - cpsie(I32_bit); // allow interrupt exceptions + ENABLE_INTERRUPT();// allow interrupt exceptions /* * For each line that isn't valid, we set the intrsource for it to
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jakllsch Date: Tue Feb 9 14:24:14 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros. To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Feb 7 21:24:50 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Optimize hardware priority updates. In gicv3_set_priority, read the current priority mask and only update it if we are lowering the priority. The hardware priority filter is raised only after taking an interrupt. This makes splfoo/splx without an interrupt in between considerably cheaper as PMR writes are relatively expensive compared to reads. While here, avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros. To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Feb 7 21:24:50 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Optimize hardware priority updates.
In gicv3_set_priority, read the current priority mask and only update it
if we are lowering the priority. The hardware priority filter is raised
only after taking an interrupt. This makes splfoo/splx without an interrupt
in between considerably cheaper as PMR writes are relatively expensive
compared to reads.
While here, avoid an extra daif read when dispatching interrupts by using
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.39 src/sys/arch/arm/cortex/gicv3.c:1.40
--- src/sys/arch/arm/cortex/gicv3.c:1.39 Sat Jan 16 21:05:15 2021
+++ src/sys/arch/arm/cortex/gicv3.c Sun Feb 7 21:24:50 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.40 2021/02/07 21:24:50 jmcneill Exp $");
#include
#include
@@ -220,8 +220,13 @@ static void
gicv3_set_priority(struct pic_softc *pic, int ipl)
{
struct gicv3_softc * const sc = PICTOSOFTC(pic);
+ const uint8_t curpmr = icc_pmr_read();
+ const uint8_t newpmr = IPL_TO_PMR(sc, ipl);
- icc_pmr_write(IPL_TO_PMR(sc, ipl));
+ if (newpmr > curpmr) {
+ /* Lowering priority mask */
+ icc_pmr_write(newpmr);
+ }
}
static void
@@ -407,7 +412,7 @@ gicv3_cpu_init(struct pic_softc *pic, st
;
/* Set initial priority mask */
- gicv3_set_priority(pic, IPL_HIGH);
+ icc_pmr_write(IPL_TO_PMR(sc, IPL_HIGH));
/* Set the binary point field to the minimum value */
icc_bpr1_write(0);
@@ -424,7 +429,7 @@ gicv3_cpu_init(struct pic_softc *pic, st
gicv3_redist_enable(sc, ci);
/* Allow IRQ exceptions */
- cpsie(I32_bit);
+ ENABLE_INTERRUPT();
}
#ifdef MULTIPROCESSOR
@@ -722,9 +727,14 @@ gicv3_irq_handler(void *frame)
struct gicv3_softc * const sc = gicv3_softc;
struct pic_softc *pic;
const int oldipl = ci->ci_cpl;
+ const uint8_t pmr = IPL_TO_PMR(sc, oldipl);
ci->ci_data.cpu_nintr++;
+ if (icc_pmr_read() != pmr) {
+ icc_pmr_write(pmr);
+ }
+
for (;;) {
const uint32_t iar = icc_iar1_read();
dsb(sy);
@@ -745,7 +755,7 @@ gicv3_irq_handler(void *frame)
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
} else if (ci->ci_cpl != ipl) {
- gicv3_set_priority(pic, ipl);
+ icc_pmr_write(IPL_TO_PMR(sc, ipl));
ci->ci_cpl = ipl;
}
@@ -756,9 +766,9 @@ gicv3_irq_handler(void *frame)
const int64_t nintr = ci->ci_data.cpu_nintr;
- cpsie(I32_bit);
+ ENABLE_INTERRUPT();
pic_dispatch(is, frame);
- cpsid(I32_bit);
+ DISABLE_INTERRUPT();
if (nintr != ci->ci_data.cpu_nintr)
ci->ci_intr_preempt.ev_count++;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jan 18 23:43:35 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Fix a comment To generate a diff of this commit: cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gtmr.c diff -u src/sys/arch/arm/cortex/gtmr.c:1.42 src/sys/arch/arm/cortex/gtmr.c:1.43 --- src/sys/arch/arm/cortex/gtmr.c:1.42 Fri Oct 30 18:54:36 2020 +++ src/sys/arch/arm/cortex/gtmr.c Mon Jan 18 23:43:34 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $ */ +/* $NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.42 2020/10/30 18:54:36 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gtmr.c,v 1.43 2021/01/18 23:43:34 jmcneill Exp $"); #include #include @@ -178,7 +178,7 @@ gtmr_read_cntct(struct gtmr_softc *sc) /* * The Allwinner A64 SoC has an unstable architectural timer. * To workaround this problem, ignore reads where the lower - * 11 bits are all 0s or 1s. + * 10 bits are all 0s or 1s. */ uint64_t val; u_int bits;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jan 18 23:43:35 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gtmr.c Log Message: Fix a comment To generate a diff of this commit: cvs rdiff -u -r1.42 -r1.43 src/sys/arch/arm/cortex/gtmr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sat Jan 16 21:05:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h
Log Message:
Remove MAXCPUS dependency.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3.h
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3_its.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3_its.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.38 src/sys/arch/arm/cortex/gicv3.c:1.39
--- src/sys/arch/arm/cortex/gicv3.c:1.38 Tue Dec 22 10:46:51 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.39 2021/01/16 21:05:15 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
#include
@@ -838,7 +839,8 @@ gicv3_init(struct gicv3_softc *sc)
LIST_INIT(>sc_lpi_callbacks);
- for (n = 0; n < MAXCPUS; n++)
+ sc->sc_irouter = kmem_zalloc(sizeof(*sc->sc_irouter) * ncpu, KM_SLEEP);
+ for (n = 0; n < ncpu; n++)
sc->sc_irouter[n] = UINT64_MAX;
sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
@@ -876,6 +878,9 @@ gicv3_init(struct gicv3_softc *sc)
pic_add(>sc_pic, 0);
if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0) {
+ sc->sc_lpipend = kmem_zalloc(sizeof(*sc->sc_lpipend) * ncpu, KM_SLEEP);
+ sc->sc_processor_id = kmem_zalloc(sizeof(*sc->sc_processor_id) * ncpu, KM_SLEEP);
+
sc->sc_lpi.pic_ops = _lpiops;
sc->sc_lpi.pic_maxsources = 8192; /* Min. required by GICv3 spec */
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.10 src/sys/arch/arm/cortex/gicv3.h:1.11
--- src/sys/arch/arm/cortex/gicv3.h:1.10 Fri Dec 4 21:39:26 2020
+++ src/sys/arch/arm/cortex/gicv3.h Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.10 2020/12/04 21:39:26 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.11 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -70,20 +70,20 @@ struct gicv3_softc {
u_int sc_pmr_shift;
uint32_t sc_enabled_sgippi;
- uint64_t sc_irouter[MAXCPUS];
+ uint64_t *sc_irouter;
/* LPI configuration table */
struct gicv3_dma sc_lpiconf;
bool sc_lpiconf_flush;
/* LPI pending tables */
- struct gicv3_dma sc_lpipend[MAXCPUS];
+ struct gicv3_dma *sc_lpipend;
/* LPI IDs */
vmem_t *sc_lpi_pool;
/* Unique identifier for PEs */
- u_int sc_processor_id[MAXCPUS];
+ u_int *sc_processor_id;
/* Callbacks */
LIST_HEAD(, gicv3_lpi_callback) sc_lpi_callbacks;
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.31 src/sys/arch/arm/cortex/gicv3_its.c:1.32
--- src/sys/arch/arm/cortex/gicv3_its.c:1.31 Thu Dec 24 14:44:49 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Sat Jan 16 21:05:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.32 2021/01/16 21:05:15 jmcneill Exp $");
#include
#include
@@ -712,7 +712,7 @@ gicv3_its_table_init(struct gicv3_softc
/*
* Allocate space for one interrupt collection per CPU.
*/
- table_size = roundup(entry_size * MAXCPUS, page_size);
+ table_size = roundup(entry_size * ncpu, page_size);
table_type = "Collections";
break;
default:
@@ -866,6 +866,8 @@ gicv3_its_init(struct gicv3_softc *sc, b
its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP);
its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP);
its->its_gic = sc;
+ its->its_rdbase = kmem_zalloc(sizeof(*its->its_rdbase) * ncpu, KM_SLEEP);
+ its->its_cpuonline = kmem_zalloc(sizeof(*its->its_cpuonline) * ncpu, KM_SLEEP);
its->its_cb.cpu_init = gicv3_its_cpu_init;
its->its_cb.get_affinity = gicv3_its_get_affinity;
its->its_cb.set_affinity = gicv3_its_set_affinity;
Index: src/sys/arch/arm/cortex/gicv3_its.h
diff -u src/sys/arch/arm/cortex/gicv3_its.h:1.6
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sat Jan 16 21:05:15 UTC 2021 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c gicv3_its.h Log Message: Remove MAXCPUS dependency. To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/cortex/gicv3.h cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3_its.c cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/cortex/gicv3_its.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Dec 24 14:44:49 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.30 src/sys/arch/arm/cortex/gicv3_its.c:1.31 --- src/sys/arch/arm/cortex/gicv3_its.c:1.30 Fri Dec 11 22:42:31 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Dec 24 14:44:49 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.31 2020/12/24 14:44:49 jmcneill Exp $"); #include #include @@ -292,7 +292,7 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its if (vmem_alloc(its->its_gic->sc_lpi_pool, 1, VM_INSTANTFIT|VM_SLEEP, ) != 0) return -1; - + KASSERT(its->its_pa[n] == NULL); new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP); @@ -437,7 +437,7 @@ gicv3_its_msix_enable(struct gicv3_its * bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); - val &= ~PCI_MSIX_VECTCTL_MASK; + val &= ~PCI_MSIX_VECTCTL_MASK; bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Dec 24 14:44:49 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Tue Dec 22 10:46:51 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: When lpiconf flushing is required, make sure to flush to PoC and not PoU. Spotted by nick. To generate a diff of this commit: cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Tue Dec 22 10:46:51 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
When lpiconf flushing is required, make sure to flush to PoC and not PoU.
Spotted by nick.
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.37 src/sys/arch/arm/cortex/gicv3.c:1.38
--- src/sys/arch/arm/cortex/gicv3.c:1.37 Fri Dec 11 21:22:36 2020
+++ src/sys/arch/arm/cortex/gicv3.c Tue Dec 22 10:46:51 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.38 2020/12/22 10:46:51 jmcneill Exp $");
#include
#include
@@ -514,6 +514,13 @@ static const struct pic_ops gicv3_picops
};
static void
+gicv3_dcache_wb_range(vaddr_t va, vsize_t len)
+{
+ cpu_dcache_wb_range(va, len);
+ dsb(sy);
+}
+
+static void
gicv3_lpi_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask)
{
struct gicv3_softc * const sc = LPITOSOFTC(pic);
@@ -522,7 +529,7 @@ gicv3_lpi_unblock_irqs(struct pic_softc
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] |= GIC_LPICONF_Enable;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
@@ -539,7 +546,7 @@ gicv3_lpi_block_irqs(struct pic_softc *p
while ((bit = ffs(mask)) != 0) {
sc->sc_lpiconf.base[irqbase + bit - 1] &= ~GIC_LPICONF_Enable;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[irqbase + bit - 1], 1);
mask &= ~__BIT(bit - 1);
}
@@ -555,7 +562,7 @@ gicv3_lpi_establish_irq(struct pic_softc
sc->sc_lpiconf.base[is->is_irq] = IPL_TO_PRIORITY(sc, is->is_ipl) | GIC_LPICONF_Res1;
if (sc->sc_lpiconf_flush)
- cpu_dcache_wb_range((vaddr_t)>sc_lpiconf.base[is->is_irq], 1);
+ gicv3_dcache_wb_range((vaddr_t)>sc_lpiconf.base[is->is_irq], 1);
else
dsb(ishst);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 22:42:31 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Simplify gits_command by getting rid of the _BYTE_ORDER test and just always use the loop + htole64 path. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.29 src/sys/arch/arm/cortex/gicv3_its.c:1.30 --- src/sys/arch/arm/cortex/gicv3_its.c:1.29 Fri Dec 11 21:40:50 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Fri Dec 11 22:42:31 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.30 2020/12/11 22:42:31 jmcneill Exp $"); #include #include @@ -118,13 +118,9 @@ gits_command(struct gicv3_its *its, cons cwriter = gits_read_8(its, GITS_CWRITER); woff = cwriter & GITS_CWRITER_Offset; -#if _BYTE_ORDER == _BIG_ENDIAN uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff); for (int i = 0; i < __arraycount(cmd->dw); i++) dw[i] = htole64(cmd->dw[i]); -#else - memcpy(its->its_cmd.base + woff, cmd->dw, sizeof(cmd->dw)); -#endif bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); woff += sizeof(cmd->dw);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 22:42:31 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: Simplify gits_command by getting rid of the _BYTE_ORDER test and just always use the loop + htole64 path. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:40:50 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c gicv3_its.c Log Message: Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X vector control register. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_v2m.c cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_v2m.c diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.9 src/sys/arch/arm/cortex/gic_v2m.c:1.10 --- src/sys/arch/arm/cortex/gic_v2m.c:1.9 Thu May 7 16:20:40 2020 +++ src/sys/arch/arm/cortex/gic_v2m.c Fri Dec 11 21:40:50 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $ */ +/* $NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.10 2020/12/11 21:40:50 jmcneill Exp $"); #include #include @@ -183,6 +183,7 @@ gic_v2m_msix_enable(struct gic_v2m_frame pci_chipset_tag_t pc = pa->pa_pc; pcitag_t tag = pa->pa_tag; pcireg_t ctl; + uint32_t val; int off; if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL)) @@ -198,7 +199,9 @@ gic_v2m_msix_enable(struct gic_v2m_frame bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data); - bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); + val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); + val &= ~PCI_MSIX_VECTCTL_MASK; + bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); ctl |= PCI_MSIX_CTL_ENABLE; Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.28 src/sys/arch/arm/cortex/gicv3_its.c:1.29 --- src/sys/arch/arm/cortex/gicv3_its.c:1.28 Thu Sep 24 08:50:09 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Fri Dec 11 21:40:50 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.29 2020/12/11 21:40:50 jmcneill Exp $"); #include #include @@ -429,6 +429,7 @@ gicv3_its_msix_enable(struct gicv3_its * pci_chipset_tag_t pc = pa->pa_pc; pcitag_t tag = pa->pa_tag; pcireg_t ctl; + uint32_t val; int off; if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, , NULL)) @@ -439,7 +440,9 @@ gicv3_its_msix_enable(struct gicv3_its * bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, (uint32_t)addr); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, (uint32_t)(addr >> 32)); bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_DATA, lpi - its->its_pic->pic_irqbase); - bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0); + val = bus_space_read_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL); + val &= ~PCI_MSIX_VECTCTL_MASK; + bus_space_write_4(bst, bsh, entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, val); ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL); ctl |= PCI_MSIX_CTL_ENABLE;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:40:50 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c gicv3_its.c Log Message: Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-X vector control register. To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gic_v2m.c cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:22:37 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Fix spelling in comment. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.36 src/sys/arch/arm/cortex/gicv3.c:1.37 --- src/sys/arch/arm/cortex/gicv3.c:1.36 Fri Dec 4 21:39:26 2020 +++ src/sys/arch/arm/cortex/gicv3.c Fri Dec 11 21:22:36 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.37 2020/12/11 21:22:36 jmcneill Exp $"); #include #include @@ -837,7 +837,7 @@ gicv3_init(struct gicv3_softc *sc) sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER); /* - * We don't alwayst have a consistent view of priorities between the + * We don't always have a consistent view of priorities between the * CPU interface (ICC_PMR_EL1) and the GICD/GICR registers. Detect * if we are making secure or non-secure accesses to each, and adjust * the values that we write to each accordingly.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 11 21:22:37 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Fix spelling in comment. To generate a diff of this commit: cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Fri Dec 4 21:39:26 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
gicv3: Only use 1 of N SPI distribution when the feature is available.
A GICv3+ implementation is not guaranteed to support 1 of N SPI
distribution. Support for this feature is indicated in GICD_TYPER.No1N.
When No1N=1, route all interrupts to the primary PE by default and only
allow a single CPU target when updating affinity.
To generate a diff of this commit:
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.35 src/sys/arch/arm/cortex/gicv3.c:1.36
--- src/sys/arch/arm/cortex/gicv3.c:1.35 Tue Nov 24 23:31:56 2020
+++ src/sys/arch/arm/cortex/gicv3.c Fri Dec 4 21:39:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.35 2020/11/24 23:31:56 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.35 2020/11/24 23:31:56 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.36 2020/12/04 21:39:26 jmcneill Exp $");
#include
#include
@@ -59,6 +59,8 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#define IPL_TO_PRIORITY(sc, ipl) (((0xff - (ipl)) << (sc)->sc_priority_shift) & 0xff)
#define IPL_TO_PMR(sc, ipl) (((0xff - (ipl)) << (sc)->sc_pmr_shift) & 0xff)
+#define GIC_SUPPORTS_1OFN(sc) (((sc)->sc_gicd_typer & GICD_TYPER_No1N) == 0)
+
#define GIC_PRIO_SHIFT_NS 4
#define GIC_PRIO_SHIFT_S 3
@@ -186,11 +188,13 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
} else {
- if (is->is_mpsafe) {
- /* Route MP-safe interrupts to all participating PEs */
+ /*
+ * If 1 of N SPI routing is supported, route MP-safe interrupts to all
+ * participating PEs. Otherwise, just route to the primary PE.
+ */
+ if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
irouter = GICD_IROUTER_Interrupt_Routing_mode;
} else {
- /* Route non-MP-safe interrupts to the primary PE only */
irouter = sc->sc_irouter[0];
}
gicd_write_8(sc, GICD_IROUTER(is->is_irq), irouter);
@@ -482,12 +486,13 @@ gicv3_set_affinity(struct pic_softc *pic
return EINVAL;
const int set = kcpuset_countset(affinity);
- if (set == ncpu)
- irouter = GICD_IROUTER_Interrupt_Routing_mode;
- else if (set == 1)
+ if (set == 1) {
irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
- else
+ } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
+ irouter = GICD_IROUTER_Interrupt_Routing_mode;
+ } else {
return EINVAL;
+ }
gicd_write_8(sc, GICD_IROUTER(irq), irouter);
@@ -820,7 +825,6 @@ gicv3_quirk_rockchip_rk3399(struct gicv3
int
gicv3_init(struct gicv3_softc *sc)
{
- const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
int n;
KASSERT(CPU_IS_PRIMARY(curcpu()));
@@ -830,6 +834,8 @@ gicv3_init(struct gicv3_softc *sc)
for (n = 0; n < MAXCPUS; n++)
sc->sc_irouter[n] = UINT64_MAX;
+ sc->sc_gicd_typer = gicd_read_4(sc, GICD_TYPER);
+
/*
* We don't alwayst have a consistent view of priorities between the
* CPU interface (ICC_PMR_EL1) and the GICD/GICR registers. Detect
@@ -855,14 +861,14 @@ gicv3_init(struct gicv3_softc *sc)
sc->sc_quirks);
sc->sc_pic.pic_ops = _picops;
- sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(gicd_typer);
+ sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(sc->sc_gicd_typer);
snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "gicv3");
#ifdef MULTIPROCESSOR
sc->sc_pic.pic_cpus = kcpuset_running;
#endif
pic_add(>sc_pic, 0);
- if ((gicd_typer & GICD_TYPER_LPIS) != 0) {
+ if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0) {
sc->sc_lpi.pic_ops = _lpiops;
sc->sc_lpi.pic_maxsources = 8192; /* Min. required by GICv3 spec */
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
@@ -893,7 +899,7 @@ gicv3_init(struct gicv3_softc *sc)
gicv3_dist_enable(sc);
gicv3_cpu_init(>sc_pic, curcpu());
- if ((gicd_typer & GICD_TYPER_LPIS) != 0)
+ if ((sc->sc_gicd_typer & GICD_TYPER_LPIS) != 0)
gicv3_lpi_cpu_init(>sc_lpi, curcpu());
#ifdef MULTIPROCESSOR
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.9 src/sys/arch/arm/cortex/gicv3.h:1.10
--- src/sys/arch/arm/cortex/gicv3.h:1.9 Tue Nov 24 23:31:56 2020
+++ src/sys/arch/arm/cortex/gicv3.h Fri Dec 4 21:39:26 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.9 2020/11/24 23:31:56 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.10 2020/12/04 21:39:26 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -64,6 +64,8 @@ struct gicv3_softc {
u_int sc_quirks;
#define
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Fri Dec 4 21:39:26 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h Log Message: gicv3: Only use 1 of N SPI distribution when the feature is available. A GICv3+ implementation is not guaranteed to support 1 of N SPI distribution. Support for this feature is indicated in GICD_TYPER.No1N. When No1N=1, route all interrupts to the primary PE by default and only allow a single CPU target when updating affinity. To generate a diff of this commit: cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/cortex/gicv3.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 28 14:29:02 UTC 2020 Modified Files: src/sys/arch/arm/cortex: armperiph.c Log Message: Fix build To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/armperiph.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/armperiph.c diff -u src/sys/arch/arm/cortex/armperiph.c:1.16 src/sys/arch/arm/cortex/armperiph.c:1.17 --- src/sys/arch/arm/cortex/armperiph.c:1.16 Tue Sep 29 19:58:50 2020 +++ src/sys/arch/arm/cortex/armperiph.c Sat Nov 28 14:29:02 2020 @@ -32,7 +32,7 @@ #include -__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $"); +__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.17 2020/11/28 14:29:02 skrll Exp $"); #include #include @@ -43,6 +43,7 @@ __KERNEL_RCSID(1, "$NetBSD: armperiph.c, #include #include #include +#include static int armperiph_match(device_t, cfdata_t, void *); static void armperiph_attach(device_t, device_t, void *);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sat Nov 28 14:29:02 UTC 2020 Modified Files: src/sys/arch/arm/cortex: armperiph.c Log Message: Fix build To generate a diff of this commit: cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/cortex/armperiph.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 22 20:17:39 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Fix interrupt priorities on N1 SDP.
The GICv3 architecture specification is not clear on the NS view of
priority registers, and there doesn't seem to be any consistency in how
these are implemented in both real and emulated environments.
The previous fix for this issue was meant to detect what we thought at the
time was a bug on the Rockchip RK3399. At that time the theory was somehow
EL1 has a secure view of the hardware, and this is causing us to have the
wrong view of IPRIORITYRn based on IHI0069F section 4.8.6 "Software
accesses of interrupt priority". But it turns out that this is not the
full picture. While I was able to confirm that yes, we do have secure
access to the GIC on RK3399 from EL1, the view of IPRIORITYRn differs
depending on whether you are using the Rockchip TF-A as included with
https://github.com/ayufan-rock64/linux-u-boot (shifted view), or mainline
TF-A from pkgsrc (unshifted view).
So to detect this quirk, we need three things: A method to detect if we
have S access to GIC registers, a method to see how many PMR bits are
implemented, and a method to see how many IPRIORITYRn bits are implemented.
To detect S access, we can try to toggle GICD_CTRL.EnableGrp1S. This bit
is either RES0 (security extensions not implemented), RAZ/WI (non-secure
access in two security state systems) or RW (secure access in two security
state systems).
To read the number of PMR and IPRIORITYRn bits supported, we can write all
1s to the register fields and read them back.
For the RK3399 (Rockchip TF-A) quirk, we assume a shifted view of
IPRIORITYRn if we have detected S accesses, and the PMR and IPRIORITYRn
values differ. The S access test is required because some real hardware
implementations (Ampere eMAG) were observed to report different PMR and
IPRIORITYRn masks, but present an unshifted view of IPRIORITYRn.
During testing, I also discovered that QEMU 5.1 requires this shifted view
workaround as well -- as far as I can tell, this is a QEMU bug. We can't
detect it the same way as RK3399 because security is disabled in the
emulated GIC, and the PMR and IPRIORITYRn tests both return 0xff! So now
if the GICv3 driver sees this configuration, it assumes that the shifted
view is required.
Honestly, this feature is so poorly documented that maybe it is better to
give up on HW priorities and preemption and use a single flat model like
Linux and FreeBSD does.
Tested on Arm N1 SDP, ROCKpro64 (RK3399) with Rockchip and pkgsrc TF-A,
Pinebook Pro (RK3399), Lenovo HR330A (Ampere eMAG), QEMU 5.1 (gic-version=3),
AWS EC2 a1.medium (Graviton).
To generate a diff of this commit:
cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.33 src/sys/arch/arm/cortex/gicv3.c:1.34
--- src/sys/arch/arm/cortex/gicv3.c:1.33 Sat Nov 21 11:44:00 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 22 20:17:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.33 2020/11/21 11:44:00 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.34 2020/11/22 20:17:39 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.33 2020/11/21 11:44:00 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.34 2020/11/22 20:17:39 jmcneill Exp $");
#include
#include
@@ -755,26 +755,37 @@ gicv3_irq_handler(void *frame)
pic_do_pending_ints(I32_bit, oldipl, frame);
}
-static int
-gicv3_detect_pmr_bits(struct gicv3_softc *sc)
+static bool
+gicv3_access_is_secure(struct gicv3_softc *sc)
+{
+ const uint32_t octlr = gicd_read_4(sc, GICD_CTRL);
+ gicd_write_4(sc, GICD_CTRL, octlr ^ GICD_CTRL_EnableGrp1S);
+ const uint32_t nctlr = gicd_read_4(sc, GICD_CTRL);
+ gicd_write_4(sc, GICD_CTRL, octlr);
+
+ return nctlr != octlr;
+}
+
+static uint8_t
+gicv3_get_pmr_bits(struct gicv3_softc *sc)
{
const uint32_t opmr = icc_pmr_read();
- icc_pmr_write(0xbf);
+ icc_pmr_write(0xff);
const uint32_t npmr = icc_pmr_read();
icc_pmr_write(opmr);
- return NBBY - (ffs(npmr) - 1);
+ return npmr;
}
-static int
-gicv3_detect_ipriority_bits(struct gicv3_softc *sc)
+static uint8_t
+gicv3_get_ipriority_bits(struct gicv3_softc *sc)
{
const uint32_t oipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr | 0xff);
const uint32_t nipriorityr = gicd_read_4(sc, GICD_IPRIORITYRn(8));
gicd_write_4(sc, GICD_IPRIORITYRn(8), oipriorityr);
- return NBBY - (ffs(nipriorityr & 0xff) - 1);
+ return nipriorityr & 0xff;
}
int
@@ -782,6 +793,7 @@ gicv3_init(struct gicv3_softc *sc)
{
const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
const uint32_t
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 22 20:17:39 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Fix interrupt priorities on N1 SDP. The GICv3 architecture specification is not clear on the NS view of priority registers, and there doesn't seem to be any consistency in how these are implemented in both real and emulated environments. The previous fix for this issue was meant to detect what we thought at the time was a bug on the Rockchip RK3399. At that time the theory was somehow EL1 has a secure view of the hardware, and this is causing us to have the wrong view of IPRIORITYRn based on IHI0069F section 4.8.6 "Software accesses of interrupt priority". But it turns out that this is not the full picture. While I was able to confirm that yes, we do have secure access to the GIC on RK3399 from EL1, the view of IPRIORITYRn differs depending on whether you are using the Rockchip TF-A as included with https://github.com/ayufan-rock64/linux-u-boot (shifted view), or mainline TF-A from pkgsrc (unshifted view). So to detect this quirk, we need three things: A method to detect if we have S access to GIC registers, a method to see how many PMR bits are implemented, and a method to see how many IPRIORITYRn bits are implemented. To detect S access, we can try to toggle GICD_CTRL.EnableGrp1S. This bit is either RES0 (security extensions not implemented), RAZ/WI (non-secure access in two security state systems) or RW (secure access in two security state systems). To read the number of PMR and IPRIORITYRn bits supported, we can write all 1s to the register fields and read them back. For the RK3399 (Rockchip TF-A) quirk, we assume a shifted view of IPRIORITYRn if we have detected S accesses, and the PMR and IPRIORITYRn values differ. The S access test is required because some real hardware implementations (Ampere eMAG) were observed to report different PMR and IPRIORITYRn masks, but present an unshifted view of IPRIORITYRn. During testing, I also discovered that QEMU 5.1 requires this shifted view workaround as well -- as far as I can tell, this is a QEMU bug. We can't detect it the same way as RK3399 because security is disabled in the emulated GIC, and the PMR and IPRIORITYRn tests both return 0xff! So now if the GICv3 driver sees this configuration, it assumes that the shifted view is required. Honestly, this feature is so poorly documented that maybe it is better to give up on HW priorities and preemption and use a single flat model like Linux and FreeBSD does. Tested on Arm N1 SDP, ROCKpro64 (RK3399) with Rockchip and pkgsrc TF-A, Pinebook Pro (RK3399), Lenovo HR330A (Ampere eMAG), QEMU 5.1 (gic-version=3), AWS EC2 a1.medium (Graviton). To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 22 19:53:48 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_reg.h Log Message: Add GICD_CTRL_EnableGrp1S definition. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gic_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic_reg.h diff -u src/sys/arch/arm/cortex/gic_reg.h:1.11 src/sys/arch/arm/cortex/gic_reg.h:1.12 --- src/sys/arch/arm/cortex/gic_reg.h:1.11 Thu May 2 23:07:40 2019 +++ src/sys/arch/arm/cortex/gic_reg.h Sun Nov 22 19:53:47 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_reg.h,v 1.11 2019/05/02 23:07:40 jmcneill Exp $ */ +/* $NetBSD: gic_reg.h,v 1.12 2020/11/22 19:53:47 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -144,6 +144,7 @@ #define GICD_CTRL_E1NWF __BIT(7) // GICv3 #define GICD_CTRL_DS __BIT(6) // GICv3 #define GICD_CTRL_ARE_NS __BIT(4) // GICv3 +#define GICD_CTRL_EnableGrp1S __BIT(2) // Secure only #define GICD_CTRL_EnableGrp1A __BIT(1) // GICv3 #define GICD_CTRL_Enable __BIT(0)
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 22 19:53:48 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_reg.h Log Message: Add GICD_CTRL_EnableGrp1S definition. To generate a diff of this commit: cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/cortex/gic_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 14:30:12 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_and To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 14:30:12 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_and
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.31 src/sys/arch/arm/cortex/gicv3.c:1.32
--- src/sys/arch/arm/cortex/gicv3.c:1.31 Sun Nov 1 14:19:42 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 14:30:12 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.32 2020/11/01 14:30:12 jmcneill Exp $");
#include
#include
@@ -41,6 +41,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
@@ -121,7 +122,7 @@ gicv3_unblock_irqs(struct pic_softc *pic
const u_int group = irqbase / 32;
if (group == 0) {
- sc->sc_enabled_sgippi |= mask;
+ atomic_or_32(>sc_enabled_sgippi, mask);
gicr_write_4(sc, ci->ci_gic_redist, GICR_ISENABLER0, mask);
while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP)
;
@@ -140,7 +141,7 @@ gicv3_block_irqs(struct pic_softc *pic,
const u_int group = irqbase / 32;
if (group == 0) {
- sc->sc_enabled_sgippi &= ~mask;
+ atomic_and_32(>sc_enabled_sgippi, ~mask);
gicr_write_4(sc, ci->ci_gic_redist, GICR_ICENABLER0, mask);
while (gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR) & GICR_CTLR_RWP)
;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 14:19:42 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have worked if enabled.. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.30 src/sys/arch/arm/cortex/gicv3.c:1.31 --- src/sys/arch/arm/cortex/gicv3.c:1.30 Sun Nov 1 12:13:21 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 14:19:42 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.31 2020/11/01 14:19:42 jmcneill Exp $"); #include #include @@ -843,13 +843,6 @@ gicv3_init(struct gicv3_softc *sc) if ((gicd_typer & GICD_TYPER_LPIS) != 0) gicv3_lpi_cpu_init(>sc_lpi, curcpu()); -#ifdef __HAVE_PIC_FAST_SOFTINTS - intr_establish_xname(SOFTINT_BIO, IPL_SOFTBIO, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_BIO, "softint bio"); - intr_establish_xname(SOFTINT_CLOCK, IPL_SOFTCLOCK, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_CLOCK, "softint clock"); - intr_establish_xname(SOFTINT_NET, IPL_SOFTNET, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_NET, "softint net"); - intr_establish_xname(SOFTINT_SERIAL, IPL_SOFTSERIAL, IST_MPSAFE | IST_EDGE, pic_handle_softint, (void *)SOFTINT_SERIAL, "softint serial"); -#endif - #ifdef MULTIPROCESSOR intr_establish_xname(IPI_AST, IPL_VM, IST_MPSAFE | IST_EDGE, pic_ipi_ast, (void *)-1, "IPI ast"); intr_establish_xname(IPI_XCALL, IPL_HIGH, IST_MPSAFE | IST_EDGE, pic_ipi_xcall, (void *)-1, "IPI xcall");
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 14:19:42 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have worked if enabled.. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 12:13:21 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with subsequent wfi/wfe instructions. Haven't seen this in practice but I would rather be safe here. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.29 src/sys/arch/arm/cortex/gicv3.c:1.30 --- src/sys/arch/arm/cortex/gicv3.c:1.29 Sun Nov 1 11:17:20 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 12:13:21 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.30 2020/11/01 12:13:21 jmcneill Exp $"); #include #include @@ -435,6 +435,7 @@ gicv3_ipi_send(struct pic_softc *pic, co sgir |= ci->ci_gic_sgir; } icc_sgi1r_write(sgir); + isb(); } static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 12:13:21 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering with subsequent wfi/wfe instructions. Haven't seen this in practice but I would rather be safe here. To generate a diff of this commit: cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 11:17:20 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb() here. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3.c diff -u src/sys/arch/arm/cortex/gicv3.c:1.28 src/sys/arch/arm/cortex/gicv3.c:1.29 --- src/sys/arch/arm/cortex/gicv3.c:1.28 Sun Nov 1 11:04:55 2020 +++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:17:20 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $ */ +/* $NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $ */ /*- * Copyright (c) 2018 Jared McNeill @@ -31,7 +31,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.29 2020/11/01 11:17:20 jmcneill Exp $"); #include #include @@ -214,7 +214,6 @@ gicv3_set_priority(struct pic_softc *pic struct gicv3_softc * const sc = PICTOSOFTC(pic); icc_pmr_write(IPL_TO_PMR(sc, ipl)); - isb(); } static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 11:17:20 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb() here. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 11:04:55 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3_irq_handler: No need to call gicv3_set_priority if we are already at the desired ipl. To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:04:55 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_irq_handler: No need to call gicv3_set_priority if we are already at
the desired ipl.
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.27 src/sys/arch/arm/cortex/gicv3.c:1.28
--- src/sys/arch/arm/cortex/gicv3.c:1.27 Sun Nov 1 11:03:44 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:04:55 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.28 2020/11/01 11:04:55 jmcneill Exp $");
#include
#include
@@ -723,7 +723,7 @@ gicv3_irq_handler(void *frame)
const int ipl = is->is_ipl;
if (__predict_false(ipl < ci->ci_cpl)) {
pic_do_pending_ints(I32_bit, ipl, frame);
- } else {
+ } else if (ci->ci_cpl != ipl) {
gicv3_set_priority(pic, ipl);
ci->ci_cpl = ipl;
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Sun Nov 1 11:03:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3_ipi_send: simplify logic in kcp != NULL case given that we know that
the kcpuset will only ever contain one cpu.
To generate a diff of this commit:
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.26 src/sys/arch/arm/cortex/gicv3.c:1.27
--- src/sys/arch/arm/cortex/gicv3.c:1.26 Fri Oct 30 18:54:36 2020
+++ src/sys/arch/arm/cortex/gicv3.c Sun Nov 1 11:03:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $ */
+/* $NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.26 2020/10/30 18:54:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.27 2020/11/01 11:03:44 jmcneill Exp $");
#include
#include
@@ -419,38 +419,23 @@ gicv3_cpu_init(struct pic_softc *pic, st
static void
gicv3_ipi_send(struct pic_softc *pic, const kcpuset_t *kcp, u_long ipi)
{
- CPU_INFO_ITERATOR cii;
struct cpu_info *ci;
- uint64_t intid, aff, targets;
+ uint64_t sgir;
- intid = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID);
+ sgir = __SHIFTIN(ipi, ICC_SGIR_EL1_INTID);
if (kcp == NULL) {
/* Interrupts routed to all PEs, excluding "self" */
if (ncpu == 1)
return;
- icc_sgi1r_write(intid | ICC_SGIR_EL1_IRM);
+ sgir |= ICC_SGIR_EL1_IRM;
} else {
- /* Interrupts routed to specific PEs */
- aff = 0;
- targets = 0;
- for (CPU_INFO_FOREACH(cii, ci)) {
- if (!kcpuset_isset(kcp, cpu_index(ci)))
-continue;
- if ((ci->ci_gic_sgir & ICC_SGIR_EL1_Aff) != aff) {
-if (targets != 0) {
- icc_sgi1r_write(intid | aff | targets);
- isb();
- targets = 0;
-}
-aff = (ci->ci_gic_sgir & ICC_SGIR_EL1_Aff);
- }
- targets |= (ci->ci_gic_sgir & ICC_SGIR_EL1_TargetList);
- }
- if (targets != 0) {
- icc_sgi1r_write(intid | aff | targets);
- isb();
- }
+ /* Interrupt to exactly one PE */
+ ci = cpu_lookup(kcpuset_ffs(kcp) - 1);
+ if (ci == curcpu())
+ return;
+ sgir |= ci->ci_gic_sgir;
}
+ icc_sgi1r_write(sgir);
}
static void
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Sun Nov 1 11:03:44 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: gicv3_ipi_send: simplify logic in kcp != NULL case given that we know that the kcpuset will only ever contain one cpu. To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: ryo Date: Thu Sep 24 08:50:09 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: need to swap on big endian machines. "The ITS command queue uses a little endian memory order model." (GIC Architecture Specification) To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: ryo Date: Thu Sep 24 08:50:09 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3_its.c Log Message: need to swap on big endian machines. "The ITS command queue uses a little endian memory order model." (GIC Architecture Specification) To generate a diff of this commit: cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gicv3_its.c diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.27 src/sys/arch/arm/cortex/gicv3_its.c:1.28 --- src/sys/arch/arm/cortex/gicv3_its.c:1.27 Thu Feb 13 02:12:06 2020 +++ src/sys/arch/arm/cortex/gicv3_its.c Thu Sep 24 08:50:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $ */ +/* $NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -32,7 +32,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.28 2020/09/24 08:50:09 ryo Exp $"); #include #include @@ -118,7 +118,13 @@ gits_command(struct gicv3_its *its, cons cwriter = gits_read_8(its, GITS_CWRITER); woff = cwriter & GITS_CWRITER_Offset; +#if _BYTE_ORDER == _BIG_ENDIAN + uint64_t *dw = (uint64_t *)(its->its_cmd.base + woff); + for (int i = 0; i < __arraycount(cmd->dw); i++) + dw[i] = htole64(cmd->dw[i]); +#else memcpy(its->its_cmd.base + woff, cmd->dw, sizeof(cmd->dw)); +#endif bus_dmamap_sync(its->its_dmat, its->its_cmd.map, woff, sizeof(cmd->dw), BUS_DMASYNC_PREWRITE); woff += sizeof(cmd->dw);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jul 27 18:36:23 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Remove CPU ID test in armgic_match. Perfectly normal to have GIC in non-Cortex cores. To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/cortex/gic.c diff -u src/sys/arch/arm/cortex/gic.c:1.40 src/sys/arch/arm/cortex/gic.c:1.41 --- src/sys/arch/arm/cortex/gic.c:1.40 Sun Jul 12 13:33:44 2020 +++ src/sys/arch/arm/cortex/gic.c Mon Jul 27 18:36:23 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $ */ +/* $NetBSD: gic.c,v 1.41 2020/07/27 18:36:23 jmcneill Exp $ */ /*- * Copyright (c) 2012 The NetBSD Foundation, Inc. * All rights reserved. @@ -34,7 +34,7 @@ #define _INTR_PRIVATE #include -__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.41 2020/07/27 18:36:23 jmcneill Exp $"); #include #include @@ -571,8 +571,6 @@ armgic_match(device_t parent, cfdata_t c if (strcmp(cf->cf_name, mpcaa->mpcaa_name) != 0) return 0; - if (!CPU_ID_CORTEX_P(cputype) || CPU_ID_CORTEX_A8_P(cputype)) - return 0; return 1; }
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Jul 27 18:36:23 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Remove CPU ID test in armgic_match. Perfectly normal to have GIC in non-Cortex cores. To generate a diff of this commit: cvs rdiff -u -r1.40 -r1.41 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: skrll
Date: Sun Jul 12 13:33:44 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Avoid undefined behaviour. Detected by KUBSAN.
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.39 src/sys/arch/arm/cortex/gic.c:1.40
--- src/sys/arch/arm/cortex/gic.c:1.39 Mon Apr 13 12:14:04 2020
+++ src/sys/arch/arm/cortex/gic.c Sun Jul 12 13:33:44 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.40 2020/07/12 13:33:44 skrll Exp $");
#include
#include
@@ -430,11 +430,11 @@ armgic_establish_irq(struct pic_softc *p
* There are 16 irqs per CFG register. 10=EDGE 00=LEVEL
*/
uint32_t new_cfg = cfg;
- uint32_t old_cfg = (cfg >> twopair_shift) & 3;
- if (is->is_type == IST_LEVEL && (old_cfg & 2) != 0) {
- new_cfg &= ~(3 << twopair_shift);
+ uint32_t old_cfg = (cfg >> twopair_shift) & __BITS(1, 0);
+ if (is->is_type == IST_LEVEL && (old_cfg & __BIT(1)) != 0) {
+ new_cfg &= ~(__BITS(1, 0) << twopair_shift);
} else if (is->is_type == IST_EDGE && (old_cfg & 2) == 0) {
- new_cfg |= 2 << twopair_shift;
+ new_cfg |= __BIT(1) << twopair_shift;
}
if (new_cfg != cfg) {
gicd_write(sc, cfg_reg, new_cfg);
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: skrll Date: Sun Jul 12 13:33:44 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Avoid undefined behaviour. Detected by KUBSAN. To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu May 7 16:20:40 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic_v2m.c gic_v2m.h Log Message: Do not store a pointer to the passed in struct pci_attach_args To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gic_v2m.c cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_v2m.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu May 7 16:20:40 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c gic_v2m.h
Log Message:
Do not store a pointer to the passed in struct pci_attach_args
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/gic_v2m.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/gic_v2m.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic_v2m.c
diff -u src/sys/arch/arm/cortex/gic_v2m.c:1.8 src/sys/arch/arm/cortex/gic_v2m.c:1.9
--- src/sys/arch/arm/cortex/gic_v2m.c:1.8 Mon Dec 2 03:06:51 2019
+++ src/sys/arch/arm/cortex/gic_v2m.c Thu May 7 16:20:40 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.c,v 1.8 2019/12/02 03:06:51 msaitoh Exp $ */
+/* $NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.8 2019/12/02 03:06:51 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.9 2020/05/07 16:20:40 jmcneill Exp $");
#include
#include
@@ -66,6 +66,7 @@ static int
gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count,
const struct pci_attach_args *pa)
{
+ struct pci_attach_args *new_pa;
int spi, n;
for (spi = frame->frame_base;
@@ -75,8 +76,11 @@ gic_v2m_msi_alloc_spi(struct gic_v2m_fra
if (frame->frame_pa[spi + n] != NULL)
goto next_spi;
- for (n = 0; n < count; n++)
-frame->frame_pa[spi + n] = pa;
+ for (n = 0; n < count; n++) {
+new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+memcpy(new_pa, pa, sizeof(*new_pa));
+frame->frame_pa[spi + n] = new_pa;
+ }
return spi;
}
@@ -90,7 +94,13 @@ next_spi:
static void
gic_v2m_msi_free_spi(struct gic_v2m_frame *frame, int spi)
{
+ struct pci_attach_args *pa;
+
+ pa = frame->frame_pa[spi];
frame->frame_pa[spi] = NULL;
+
+ if (pa != NULL)
+ kmem_free(pa, sizeof(*pa));
}
static int
Index: src/sys/arch/arm/cortex/gic_v2m.h
diff -u src/sys/arch/arm/cortex/gic_v2m.h:1.2 src/sys/arch/arm/cortex/gic_v2m.h:1.3
--- src/sys/arch/arm/cortex/gic_v2m.h:1.2 Mon Oct 14 11:00:13 2019
+++ src/sys/arch/arm/cortex/gic_v2m.h Thu May 7 16:20:40 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic_v2m.h,v 1.2 2019/10/14 11:00:13 jmcneill Exp $ */
+/* $NetBSD: gic_v2m.h,v 1.3 2020/05/07 16:20:40 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@ struct gic_v2m_frame {
uint32_t frame_flags;
#define GIC_V2M_FLAG_GRAVITON 0x01 /* Amazon Graviton quirk */
- const struct pci_attach_args *frame_pa[GICC_IAR_IRQ];
+ struct pci_attach_args *frame_pa[GICC_IAR_IRQ];
struct arm_pci_msi frame_msi;
};
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:56 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Apply similar fix from gic.c that fixed "left shift of 255 by 24 places
cannot be represented in type 'int'" warnings from UBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gicv3.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.24 src/sys/arch/arm/cortex/gicv3.c:1.25
--- src/sys/arch/arm/cortex/gicv3.c:1.24 Thu Feb 13 02:12:06 2020
+++ src/sys/arch/arm/cortex/gicv3.c Mon Apr 13 12:14:55 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.25 2020/04/13 12:14:55 jmcneill Exp $");
#include
#include
@@ -178,7 +178,7 @@ gicv3_establish_irq(struct pic_softc *pi
gicr_write_4(sc, n, GICR_ICFGRn(is->is_irq / 16), icfg);
ipriority = gicr_read_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4));
- ipriority &= ~(0xff << ipriority_shift);
+ ipriority &= ~(0xffU << ipriority_shift);
ipriority |= (ipriority_val << ipriority_shift);
gicr_write_4(sc, n, GICR_IPRIORITYRn(is->is_irq / 4), ipriority);
}
@@ -202,7 +202,7 @@ gicv3_establish_irq(struct pic_softc *pi
/* Update interrupt priority */
ipriority = gicd_read_4(sc, GICD_IPRIORITYRn(is->is_irq / 4));
- ipriority &= ~(0xff << ipriority_shift);
+ ipriority &= ~(0xffU << ipriority_shift);
ipriority |= (ipriority_val << ipriority_shift);
gicd_write_4(sc, GICD_IPRIORITYRn(is->is_irq / 4), ipriority);
}
@@ -277,7 +277,7 @@ gicv3_redist_enable(struct gicv3_softc *
for (o = 0; o < 4; o++, byte_shift += 8) {
struct intrsource * const is = sc->sc_pic.pic_sources[n + o];
if (is == NULL)
-priority |= 0xff << byte_shift;
+priority |= (0xffU << byte_shift);
else {
const u_int ipriority_val = IPL_TO_PRIORITY(sc, is->is_ipl);
priority |= ipriority_val << byte_shift;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Apr 13 12:14:56 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c Log Message: Apply similar fix from gic.c that fixed "left shift of 255 by 24 places cannot be represented in type 'int'" warnings from UBSan. To generate a diff of this commit: cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/cortex/gicv3.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Mon Apr 13 12:14:04 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix "left shift of 255 by 24 places cannot be represented in type 'int'"
warning from UBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gic.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.38 src/sys/arch/arm/cortex/gic.c:1.39
--- src/sys/arch/arm/cortex/gic.c:1.38 Fri Nov 16 23:25:09 2018
+++ src/sys/arch/arm/cortex/gic.c Mon Apr 13 12:14:04 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $ */
+/* $NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.38 2018/11/16 23:25:09 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gic.c,v 1.39 2020/04/13 12:14:04 jmcneill Exp $");
#include
#include
@@ -415,7 +415,7 @@ armgic_establish_irq(struct pic_softc *p
* There are 4 irqs per TARGETS register. For now bind
* to the primary cpu.
*/
- targets &= ~(0xff << byte_shift);
+ targets &= ~(0xffU << byte_shift);
#if 0
#ifdef MULTIPROCESSOR
if (is->is_mpsafe) {
@@ -455,7 +455,7 @@ armgic_establish_irq(struct pic_softc *p
*/
const bus_size_t priority_reg = GICD_IPRIORITYRn(is->is_irq / 4);
uint32_t priority = gicd_read(sc, priority_reg);
- priority &= ~(0xff << byte_shift);
+ priority &= ~(0xffU << byte_shift);
priority |= armgic_ipl_to_priority(is->is_ipl) << byte_shift;
gicd_write(sc, priority_reg, priority);
}
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Mon Apr 13 12:14:04 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gic.c Log Message: Fix "left shift of 255 by 24 places cannot be represented in type 'int'" warning from UBSan. To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/gic.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 02:12:07 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3_its.c
Log Message:
Make intr affinity work with MSIs again
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.23 src/sys/arch/arm/cortex/gicv3.c:1.24
--- src/sys/arch/arm/cortex/gicv3.c:1.23 Thu Feb 13 00:42:59 2020
+++ src/sys/arch/arm/cortex/gicv3.c Thu Feb 13 02:12:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.24 2020/02/13 02:12:06 jmcneill Exp $");
#include
#include
@@ -634,6 +634,7 @@ gicv3_lpi_get_affinity(struct pic_softc
struct gicv3_softc * const sc = LPITOSOFTC(pic);
struct gicv3_lpi_callback *cb;
+ kcpuset_zero(affinity);
LIST_FOREACH(cb, >sc_lpi_callbacks, list)
cb->get_affinity(cb->priv, irq, affinity);
}
@@ -647,11 +648,11 @@ gicv3_lpi_set_affinity(struct pic_softc
LIST_FOREACH(cb, >sc_lpi_callbacks, list) {
error = cb->set_affinity(cb->priv, irq, affinity);
- if (error)
+ if (error != EPASSTHROUGH)
return error;
}
- return error;
+ return EINVAL;
}
#endif
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.26 src/sys/arch/arm/cortex/gicv3_its.c:1.27
--- src/sys/arch/arm/cortex/gicv3_its.c:1.26 Thu Feb 13 00:42:59 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Thu Feb 13 02:12:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.27 2020/02/13 02:12:06 jmcneill Exp $");
#include
#include
@@ -806,7 +806,6 @@ gicv3_its_get_affinity(void *priv, size_
struct gicv3_its * const its = priv;
struct cpu_info *ci;
- kcpuset_zero(affinity);
ci = its->its_targets[irq];
if (ci)
kcpuset_set(affinity, cpu_index(ci));
@@ -825,7 +824,7 @@ gicv3_its_set_affinity(void *priv, size_
pa = its->its_pa[irq];
if (pa == NULL)
- return EINVAL;
+ return EPASSTHROUGH;
ci = cpu_lookup(kcpuset_ffs(affinity) - 1);
its->its_targets[irq] = ci;
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Feb 13 02:12:07 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3_its.c Log Message: Make intr affinity work with MSIs again To generate a diff of this commit: cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.26 -r1.27 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src Committed By: jmcneill Date: Thu Feb 13 00:42:59 UTC 2020 Modified Files: src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c Log Message: Since all ITS instances share a common LPI configuration table, used a shared vmem arena to allocate pic irqs. Idea from FreeBSD. To generate a diff of this commit: cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/cortex/gicv3.c cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3.h cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/cortex/gicv3_its.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/cortex
Module Name:src
Committed By: jmcneill
Date: Thu Feb 13 00:42:59 UTC 2020
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h gicv3_its.c
Log Message:
Since all ITS instances share a common LPI configuration table, used a
shared vmem arena to allocate pic irqs. Idea from FreeBSD.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/cortex/gicv3.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/gicv3.h
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/cortex/gicv3_its.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/gicv3.c
diff -u src/sys/arch/arm/cortex/gicv3.c:1.22 src/sys/arch/arm/cortex/gicv3.c:1.23
--- src/sys/arch/arm/cortex/gicv3.c:1.22 Tue Dec 24 09:12:56 2019
+++ src/sys/arch/arm/cortex/gicv3.c Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $ */
+/* $NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.22 2019/12/24 09:12:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.23 2020/02/13 00:42:59 jmcneill Exp $");
#include
#include
@@ -40,6 +40,7 @@ __KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.
#include
#include
#include
+#include
#include
@@ -828,6 +829,11 @@ gicv3_init(struct gicv3_softc *sc)
snprintf(sc->sc_lpi.pic_name, sizeof(sc->sc_lpi.pic_name), "gicv3-lpi");
pic_add(>sc_lpi, GIC_LPI_BASE);
+ sc->sc_lpi_pool = vmem_create("gicv3-lpi", 0, sc->sc_lpi.pic_maxsources,
+ 1, NULL, NULL, NULL, 0, VM_SLEEP, IPL_HIGH);
+ if (sc->sc_lpi_pool == NULL)
+ panic("failed to create gicv3 lpi pool\n");
+
gicv3_lpi_init(sc);
}
Index: src/sys/arch/arm/cortex/gicv3.h
diff -u src/sys/arch/arm/cortex/gicv3.h:1.7 src/sys/arch/arm/cortex/gicv3.h:1.8
--- src/sys/arch/arm/cortex/gicv3.h:1.7 Sun Jun 30 11:11:38 2019
+++ src/sys/arch/arm/cortex/gicv3.h Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.h,v 1.7 2019/06/30 11:11:38 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.8 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill
@@ -30,6 +30,7 @@
#define _ARM_CORTEX_GICV3_H
#include
+#include
struct gicv3_dma {
bus_dma_segment_t segs[1];
@@ -73,6 +74,9 @@ struct gicv3_softc {
/* LPI pending tables */
struct gicv3_dma sc_lpipend[MAXCPUS];
+ /* LPI IDs */
+ vmem_t *sc_lpi_pool;
+
/* Unique identifier for PEs */
u_int sc_processor_id[MAXCPUS];
Index: src/sys/arch/arm/cortex/gicv3_its.c
diff -u src/sys/arch/arm/cortex/gicv3_its.c:1.25 src/sys/arch/arm/cortex/gicv3_its.c:1.26
--- src/sys/arch/arm/cortex/gicv3_its.c:1.25 Sat Feb 1 15:33:48 2020
+++ src/sys/arch/arm/cortex/gicv3_its.c Thu Feb 13 00:42:59 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.25 2020/02/01 15:33:48 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.26 2020/02/13 00:42:59 jmcneill Exp $");
#include
#include
@@ -284,18 +284,19 @@ gicv3_its_msi_alloc_lpi(struct gicv3_its
const struct pci_attach_args *pa)
{
struct pci_attach_args *new_pa;
- int n;
+ vmem_addr_t n;
- for (n = 0; n < its->its_pic->pic_maxsources; n++) {
- if (its->its_pa[n] == NULL) {
- new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
- memcpy(new_pa, pa, sizeof(*new_pa));
- its->its_pa[n] = new_pa;
- return n + its->its_pic->pic_irqbase;
- }
- }
+ KASSERT(its->its_gic->sc_lpi_pool != NULL);
-return -1;
+ if (vmem_alloc(its->its_gic->sc_lpi_pool, 1, VM_INSTANTFIT|VM_SLEEP, ) != 0)
+ return -1;
+
+ KASSERT(its->its_pa[n] == NULL);
+
+ new_pa = kmem_alloc(sizeof(*new_pa), KM_SLEEP);
+ memcpy(new_pa, pa, sizeof(*new_pa));
+ its->its_pa[n] = new_pa;
+ return n + its->its_pic->pic_irqbase;
}
static void
@@ -303,11 +304,14 @@ gicv3_its_msi_free_lpi(struct gicv3_its
{
struct pci_attach_args *pa;
+ KASSERT(its->its_gic->sc_lpi_pool != NULL);
KASSERT(lpi >= its->its_pic->pic_irqbase);
pa = its->its_pa[lpi - its->its_pic->pic_irqbase];
its->its_pa[lpi - its->its_pic->pic_irqbase] = NULL;
kmem_free(pa, sizeof(*pa));
+
+ vmem_free(its->its_gic->sc_lpi_pool, lpi - its->its_pic->pic_irqbase, 1);
}
static uint32_t
