Re: [time-nuts] 5370 firmware hacking status report
In message 77e0fba5-aa78-4399-9562-d1274e109...@jks.com, John Seamons writes: I would worry a bit about the PLL locking too, but I have no idea how to actually measure it. I think the 1sec max gate-time is related to the eventcounter width, but it might be possible to simulate a wider counter in software. The obvious idea for advanced functionality is calculation of allan deviations -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] 5370 firmware hacking status report
Hi, the 5370 is capable of measuring up to 10s long time events or frequency/period with 10s gate time. (I.e. 2^39 * 19.53ps) Pressing 'external holdoff' activates external gating on 'EXT' input. Then you may apply a 10s long positive pulse from an external generator, with a few ms long pause, to the external input, getting 12 digits resolution. To have this longer gate time in firmware would be nice. Interesting would be to have even longer than 40 Bit arithmetic length by counting the overflow of the counter chain, and also, to get access to the full content of the arithmetic registers to calculate with higher precision externally. Or perhaps it is possible to realize a 'time stamp counter' on the 5370s hardware, to get zero dead time for T.I. measurements on 1pps comparisons. Frank ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
Poul-Henning Kamp wrote: In message77e0fba5-aa78-4399-9562-d1274e109...@jks.com, John Seamons writes: I would worry a bit about the PLL locking too, but I have no idea how to actually measure it. I think the 1sec max gate-time is related to the eventcounter width, but it might be possible to simulate a wider counter in software. The obvious idea for advanced functionality is calculation of allan deviations The PLL sample frequency is around 0.8MHz so that trigger rates approaching this will alter the PLL loop parameters. Trigger rates greater than the PLL sample frequency (200/256MHz) will likely cause lock to be lost. The 5359 (uses the same vernier oscillator assembly) overcomes this by using a digital sample and hold to set the VCO control voltage. However periodic auto calibration by closing the loop is required to avoid drift. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Discipline an oscillator with NTP?
Hi The standard NTP software does a best of the bunch selection when given a large number of servers. What it considers best and what you would pick likely are not the same thing. You stick at a few ms of error rather than getting say a 10X improvement with 100 servers. Custom code, custom hardware, stable routing - you can do *much* better. Of the three, routing is normally the biggest source of error. If it's not you have a very unusual ISP / connection / server. Bob On Jul 24, 2011, at 12:50 AM, David J Taylor david-tay...@blueyonder.co.uk wrote: Indeed thats why I was saying choose 3 servers. Now I see in the thread that you can pick pools of servers so thats good. Then average what they say the time is and drive oscillator. Wonder if you could look towards the stratum 1 servers. But that said I could easily believe that it might ot be any better then wwv. Good thread. Things to learn as we all seek a backup to GPS I assume. Regards Paul WB8TSL Paul, be aware that three servers is not the best choice, as if one fails you are left with two servers, and you don't know which is correct. IIRC four, five and seven servers allow for the failure of 1, 2 or 3 of them, but do choose more than three. 73, David GM8ARV ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
John, Fantastic job on reverse engineering the counter and then actually doing something to modernize it. I might guess implementing this on one of the counters out of 3 would be both educational and interesting. Ending up with a modern on the network counter. Took a look at your setup and bench. So the support for the 5370 is a HP vector network analyzer. Now thats some support. :-) I might tend to have the two flipped in the stack. So you are suggesting the potential to make this operational to a wider audience. Any thoughts on a timeline? I personally have no problems soldering in 40-60 wires from a daughter board as an example. Regards Paul WB8TSL On Sun, Jul 24, 2011 at 8:12 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Poul-Henning Kamp wrote: In message77E0FBA5-AA78-4399-**9562-d1274e109...@jks.com77e0fba5-aa78-4399-9562-d1274e109...@jks.com, John Seamons writes: I would worry a bit about the PLL locking too, but I have no idea how to actually measure it. I think the 1sec max gate-time is related to the eventcounter width, but it might be possible to simulate a wider counter in software. The obvious idea for advanced functionality is calculation of allan deviations The PLL sample frequency is around 0.8MHz so that trigger rates approaching this will alter the PLL loop parameters. Trigger rates greater than the PLL sample frequency (200/256MHz) will likely cause lock to be lost. The 5359 (uses the same vernier oscillator assembly) overcomes this by using a digital sample and hold to set the VCO control voltage. However periodic auto calibration by closing the loop is required to avoid drift. Bruce __**_ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/** mailman/listinfo/time-nutshttps://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] NERC TEC test postponed
At 04:50 PM 7/15/2011, Tom Van Baak (lab/iPad) wrote: I've been told the NERC has decided to postpone their July 14 TEC-elimination test. Sorry I don't have a URL with more information. Their website has been updated: http://www.nerc.com/page.php?cid=6|386 The TEC elimination field tests are now scheduled to start 9/15, but it's also marked tentative and start to be determined. -- newell N5TNL ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
On Jul 24, 2011, at 12:32 AM, Poul-Henning Kamp wrote: I would worry a bit about the PLL locking too, but I have no idea how to actually measure it. I think the 1sec max gate-time is related to the eventcounter width, but it might be possible to simulate a wider counter in software. The obvious idea for advanced functionality is calculation of allan deviations Interpolator PLL unlock: From the schematic, each VCO control voltage gets limit checked by a comparator located on the 200MHz multiplier card. If either one goes out of range a latch gets set on the count chain board which shows up as a status bit in N0ST. That latch is what drives the red led on the top edge of the count board. I currently check it at the top of the 500 sample/packet loop. This is often enough since it gets latched even if the VCO drops out only once. Whether the comparator is good enough if you're on the edge of failure sampling at 100 K/sec is another matter. Event counter width: It seems to be 16-bits wide with an overflow bit also in N0ST. So extending the bit length in software is not impossible. I notice now that the N0 counter has an overflow as well. This explains why binary mode readout is limited to TIs 320 ns (typo in manual, it says ps). An HPIB binary connection has no way of dealing with software overflow from a 16-bit N0. And 16-bits @ 200MHz is about +/- 328 ns. In non-binary mode the software must be maintaining a 28-bit N0 counter for the max +/- 10 sec TI spec. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
On Jul 24, 2011, at 11:18 AM, paul swed wrote: Took a look at your setup and bench. So the support for the 5370 in a HP vector network analyzer. Now thats some support. :-) I might tend to have the two flipped in the stack. So you are suggesting the potential to make this operational to a wider audience. Any thoughts on a timeline? I personally have no problems soldering in 40-60 wires from a daughter board as an example. 4396A NSA: I should have been more clear about that. I only use that box as a programmable HPIB master for testing. Nothing more. I really need to get a PCI or USB GPIB interface like everyone else. Anyone running John's GPIB Toolkit under Wine on Ubuntu? /insert Windows rant Rather than trying to replicate my painful development setup we really just need to get a proper board made. That Atmel eval kit alone is $200. The board needs a boot loader that lets you re-flash over the network (instead of spending money on a JTAG dongle or using the awful Atmel USB flasher). Has anyone used KiCAD for pcb layout? Also, I don't know anything about USB, so I could use some help. Atmel has an existing stack for the micro. Big advantages over using Ethernet if you don't already have a network setup. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
In message 2774adf8-762d-45c4-b3c6-edb188691...@jks.com, John Seamons writes: On Jul 24, 2011, at 11:18 AM, paul swed wrote: I really need to get a PCI or USB GPIB interface like everyone else. Anyone running John's GPIB Toolkit under Wine on Ubuntu? /insert Windows rant https://github.com/bsdphk/pylt Big advantages over using Ethernet if you don't already have a network setup. Ethernets big advantage is that it is galvanically isolated, USB is not. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
Hi I would check that things like Win 7 64 bit are happy with the USB stack on the micro. I'm not selling anybody MS stuff, but it limits your audiance if there's a compatibility issue. Some USB stacks are a lot better than others (both embedded and at the OS level). Ethernet is going to be functional on any modern OS. Lots of variables... Bob On Jul 24, 2011, at 4:30 PM, John Seamons wrote: On Jul 24, 2011, at 11:18 AM, paul swed wrote: Took a look at your setup and bench. So the support for the 5370 in a HP vector network analyzer. Now thats some support. :-) I might tend to have the two flipped in the stack. So you are suggesting the potential to make this operational to a wider audience. Any thoughts on a timeline? I personally have no problems soldering in 40-60 wires from a daughter board as an example. 4396A NSA: I should have been more clear about that. I only use that box as a programmable HPIB master for testing. Nothing more. I really need to get a PCI or USB GPIB interface like everyone else. Anyone running John's GPIB Toolkit under Wine on Ubuntu? /insert Windows rant Rather than trying to replicate my painful development setup we really just need to get a proper board made. That Atmel eval kit alone is $200. The board needs a boot loader that lets you re-flash over the network (instead of spending money on a JTAG dongle or using the awful Atmel USB flasher). Has anyone used KiCAD for pcb layout? Also, I don't know anything about USB, so I could use some help. Atmel has an existing stack for the micro. Big advantages over using Ethernet if you don't already have a network setup. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] 5370 firmware hacking status report
On Jul 24, 2011, at 2:40 PM, Poul-Henning Kamp wrote: Ethernets big advantage is that it is galvanically isolated, USB is not. You had mentioned this issue in February. And since I currently flash using USB I went ahead and bought the evaluation card for the Analog Devices ADuM4160 power/signal isolator chip (see last pic on jks.com). Even though I programmed the GPIO pins on the micro for open drain I didn't know if the +5 on the USB from the host computer would fight the signals from the 5370. Plus I didn't want the ground loop. So the isolator chip splits the power domains and the micro is powered by +5 from the 5370. Works great. But I haven't found anyone who sells the chip in small quantities yet. You also had mentioned PyRevEng back then. I will try it. It will be very useful at this point. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
