On Jul 24, 2011, at 12:32 AM, Poul-Henning Kamp wrote: > I would worry a bit about the PLL locking too, but I have no idea how > to actually measure it. > > I think the 1sec max gate-time is related to the eventcounter width, > but it might be possible to simulate a wider counter in software. > > The obvious idea for advanced functionality is calculation of > allan deviations
Interpolator PLL unlock: From the schematic, each VCO control voltage gets limit checked by a comparator located on the 200MHz multiplier card. If either one goes out of range a latch gets set on the count chain board which shows up as a status bit in N0ST. That latch is what drives the red led on the top edge of the count board. I currently check it at the top of the 500 sample/packet loop. This is often enough since it gets latched even if the VCO drops out only once. Whether the comparator is good enough if you're on the edge of failure sampling at 100 K/sec is another matter. Event counter width: It seems to be 16-bits wide with an overflow bit also in N0ST. So extending the bit length in software is not impossible. I notice now that the N0 counter has an overflow as well. This explains why binary mode readout is limited to TIs < 320 ns (typo in manual, it says ps). An HPIB binary connection has no way of dealing with software overflow from a 16-bit N0. And 16-bits @ 200MHz is about +/- 328 ns. In non-binary mode the software must be maintaining a 28-bit N0 counter for the max +/- 10 sec TI spec. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
