In message <[email protected]>, John Seamons writes:

I would worry a bit about the PLL locking too, but I have no idea how
to actually measure it.

I think the 1sec max gate-time is related to the eventcounter width,
but it might be possible to simulate a wider counter in software.

The obvious idea for advanced functionality is calculation of
allan deviations

-- 
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
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