[U-Boot] [PATCH] armv8: ls1046aqds: Fix NAND offset for Fman ucode and env

[Gong Qianyu]

Fix a bug of 'commit 8104deb2d6b7 ("armv8: layerscape: Adjust memory
mapping for Flash/SD card on LS1046A")' as NAND block size is
256KB on LS1046AQDS.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1046a_common.h | 2 +-
 include/configs/ls1046aqds.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index dfc8e9237d..6d501b9c54 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -183,7 +183,7 @@
 #define CONFIG_ENV_SPI_MODE0x03
 #elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR(72 * 
CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR(36 * 
CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR0x6090
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 9231cca9e9..39bd1c38a8 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -435,7 +435,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_SIZE0x2000
-#define CONFIG_ENV_OFFSET  (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET  (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
 #define CONFIG_ENV_OFFSET  (3 * 1024 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV 0
-- 
2.14.1

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[U-Boot] [Patch v2 2/2] arm64: ls1046ardb: Add distro boot support

[Gong Qianyu]

Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - No change.

 configs/ls1046ardb_qspi_defconfig   |  1 +
 configs/ls1046ardb_sdcard_defconfig |  1 +
 include/configs/ls1046a_common.h| 42 +++--
 include/configs/ls1046aqds.h|  1 +
 include/configs/ls1046ardb.h|  6 ++
 5 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index a8e8876..5be1846 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -35,3 +35,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046ardb_sdcard_defconfig 
b/configs/ls1046ardb_sdcard_defconfig
index 244c58a..6ee3b43 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -41,3 +41,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 1b91676..490744a 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -201,20 +201,54 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#include 
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(USB, usb, 0)
+#include 
+#endif
+
 #ifndef SPL_NO_MISC
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
-   "loadaddr=0x8010\0" \
"ramdisk_addr=0x80\0"   \
"ramdisk_size=0x200\0"  \
"fdt_high=0x\0" \
"initrd_high=0x\0"  \
+   "fdt_addr=0x64f0\0" \
+   "kernel_addr=0x6500\0"  \
+   "scriptaddr=0x8000\0"   \
+   "fdtheader_addr_r=0x8010\0" \
+   "kernelheader_addr_r=0x8020\0"  \
+   "load_addr=0xa000\0"\
+   "fdt_addr_r=0x9000\0"   \
+   "ramdisk_addr_r=0xa000\0"   \
"kernel_start=0x100\0"  \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
"console=ttyS0,115200\0"\
-   MTDPARTS_DEFAULT "\0"
+   MTDPARTS_DEFAULT "\0"   \
+   BOOTENV \
+   "boot_scripts=ls1046ardb_boot.scr\0"\
+   "scan_dev_for_boot_part="   \
+   "part list ${devtype} ${devnum} devplist; "   \
+   "env exists devplist || setenv devplist 1; "  \
+   "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} "  \
+   "${devnum}:${distro_bootpart} "  \
+   "bootfstype; then "  \
+   "run scan_dev_for_boot; "\
+ "fi; "   \
+   "done\0"   \
+   "installer=load mmc 0:2 $load_addr "  \
+   "/flex_installer_arm64.itb; "  \
+   "bootm $load_addr#ls1046ardb\0"  \
+   "qspi_bootcmd=echo Trying load from qspi..;"  \
+   "sf probe && sf read $load_addr " \
+   "$kernel_start $kernel_size && bootm $load_addr#$board\0"
+
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \
@@ -228,10 +262,6 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 
-#ifndef SPL_NO_MISC
-#define CONFIG_CMDLINE_EDITING 1
-#endif
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS 64  /* max command args */
 
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 645cd9c..1b66c94 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -466,6 +466,7 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_CMDLINE_TAG
 
+#undef CONFIG_BOOTCOMMAND
 #if

[U-Boot] [Patch v2 1/2] armv8: ls1046a: move CONFIG_CMD_USB to defconfig

[Gong Qianyu]

Move the macro to defconfig to take effect globally.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Reordered the macro.

 configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
 configs/ls1046aqds_defconfig| 1 +
 configs/ls1046aqds_lpuart_defconfig | 1 +
 configs/ls1046aqds_nand_defconfig   | 1 +
 configs/ls1046aqds_qspi_defconfig   | 1 +
 configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
 configs/ls1046aqds_sdcard_qspi_defconfig| 1 +
 configs/ls1046ardb_emmc_defconfig   | 1 +
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig   | 1 +
 configs/ls1046ardb_qspi_defconfig   | 1 +
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 +
 configs/ls1046ardb_sdcard_defconfig | 1 +
 include/configs/ls1046aqds.h| 1 -
 include/configs/ls1046ardb.h| 1 -
 14 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig 
b/configs/ls1046aqds_SECURE_BOOT_defconfig
index cead5af..cd69f79 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 87df2fe..1d013dc 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046aqds_lpuart_defconfig 
b/configs/ls1046aqds_lpuart_defconfig
index 47dba49..20bebb2 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046aqds_nand_defconfig 
b/configs/ls1046aqds_nand_defconfig
index a3c6065..51141e1 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index d145c5a..340210a 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig 
b/configs/ls1046aqds_sdcard_ifc_defconfig
index 19b8077..d2f672b 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index e49de18..fc2c1fa 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1046ardb_emmc_defconfig 
b/configs/ls1046ardb_emmc_defconfig
index c50931a..19e7bdc 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -23,6 +23,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index de14dc1..d0f1a06 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index 0a8f1a0..a8e8876 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 1cd19ed..81858be 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -26,6

[U-Boot] [PATCH] armv8: ls1046ardb: update core frequency to 1800MHZ

[Gong Qianyu]

Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 2 +-
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 
b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
index 6a5076e..ccedf87 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e00  
+0c150012 0e00  
 11335559 4012 6004 c100
    00238800
 20124000 3000 0096 0001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 
b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
index d5265b8..d3b1522 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e00  
+0c150012 0e00  
 11335559 40005012 6004 c100
    00238800
 20124000 3101 0096 0001
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] arm64: ls1046ardb: Add distro boot support

[Gong Qianyu]

Tested on ls1046ardb with automatically boot Ubuntu from SD card or
USB disk, if it fails to detect external storage disk, fall back to
qspi boot.

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 configs/ls1046ardb_qspi_defconfig   |  1 +
 configs/ls1046ardb_sdcard_defconfig |  1 +
 include/configs/ls1046a_common.h| 42 +++--
 include/configs/ls1046aqds.h|  1 +
 include/configs/ls1046ardb.h|  6 ++
 5 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index 0479c98..9ab17d4 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -35,3 +35,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ls1046ardb_sdcard_defconfig 
b/configs/ls1046ardb_sdcard_defconfig
index 12eb524..e9aa023 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -39,3 +39,4 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index b66b8ac..b859727 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -201,20 +201,54 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE   128
 
+#include 
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(USB, usb, 0)
+#include 
+#endif
+
 #ifndef SPL_NO_MISC
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"hwconfig=fsl_ddr:bank_intlv=auto\0"\
-   "loadaddr=0x8010\0" \
"ramdisk_addr=0x80\0"   \
"ramdisk_size=0x200\0"  \
"fdt_high=0x\0" \
"initrd_high=0x\0"  \
+   "fdt_addr=0x64f0\0" \
+   "kernel_addr=0x6500\0"  \
+   "scriptaddr=0x8000\0"   \
+   "fdtheader_addr_r=0x8010\0" \
+   "kernelheader_addr_r=0x8020\0"  \
+   "load_addr=0xa000\0"\
+   "fdt_addr_r=0x9000\0"   \
+   "ramdisk_addr_r=0xa000\0"   \
"kernel_start=0x100\0"  \
"kernel_load=0xa000\0"  \
"kernel_size=0x280\0"   \
"console=ttyS0,115200\0"\
-   MTDPARTS_DEFAULT "\0"
+   MTDPARTS_DEFAULT "\0"   \
+   BOOTENV \
+   "boot_scripts=ls1046ardb_boot.scr\0"\
+   "scan_dev_for_boot_part="   \
+   "part list ${devtype} ${devnum} devplist; "   \
+   "env exists devplist || setenv devplist 1; "  \
+   "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} "  \
+   "${devnum}:${distro_bootpart} "  \
+   "bootfstype; then "  \
+   "run scan_dev_for_boot; "\
+ "fi; "   \
+   "done\0"   \
+   "installer=load mmc 0:2 $load_addr "  \
+   "/flex_installer_arm64.itb; "  \
+   "bootm $load_addr#ls1046ardb\0"  \
+   "qspi_bootcmd=echo Trying load from qspi..;"  \
+   "sf probe && sf read $load_addr " \
+   "$kernel_start $kernel_size && bootm $load_addr#$board\0"
+
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500 " \
@@ -228,10 +262,6 @@
 #define CONFIG_SYS_BARGSIZECONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
 
-#ifndef SPL_NO_MISC
-#define CONFIG_CMDLINE_EDITING 1
-#endif
-
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS 64  /* max command args */
 
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 645cd9c..1b66c94 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -466,6 +466,7 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_CMDLINE_TAG
 
+#undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BO

[U-Boot] [PATCH 1/2] armv8: ls1046a: move CONFIG_CMD_USB to defconfig

[Gong Qianyu]

Move the macro to defconfig to take effect globally.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 configs/ls1046aqds_SECURE_BOOT_defconfig| 1 +
 configs/ls1046aqds_defconfig| 1 +
 configs/ls1046aqds_lpuart_defconfig | 1 +
 configs/ls1046aqds_nand_defconfig   | 1 +
 configs/ls1046aqds_qspi_defconfig   | 1 +
 configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
 configs/ls1046aqds_sdcard_qspi_defconfig| 1 +
 configs/ls1046ardb_emmc_defconfig   | 1 +
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig   | 1 +
 configs/ls1046ardb_qspi_defconfig   | 1 +
 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 +
 configs/ls1046ardb_sdcard_defconfig | 1 +
 include/configs/ls1046aqds.h| 1 -
 include/configs/ls1046ardb.h| 1 -
 14 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig 
b/configs/ls1046aqds_SECURE_BOOT_defconfig
index cead5af..e335c71 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 87df2fe..d58a8e9 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_lpuart_defconfig 
b/configs/ls1046aqds_lpuart_defconfig
index 47dba49..535505d 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -15,6 +15,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_nand_defconfig 
b/configs/ls1046aqds_nand_defconfig
index cdcc25d..0b30fd3 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_qspi_defconfig 
b/configs/ls1046aqds_qspi_defconfig
index d145c5a..35bd040 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -16,6 +16,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig 
b/configs/ls1046aqds_sdcard_ifc_defconfig
index a35e1be..56d90bd 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig 
b/configs/ls1046aqds_sdcard_qspi_defconfig
index 922f202..3b52a8d 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046ardb_emmc_defconfig 
b/configs/ls1046ardb_emmc_defconfig
index 94bd8a5..3f17c73 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -16,6 +16,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index de14dc1..6653016 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046ardb_qspi_defconfig 
b/configs/ls1046ardb_qspi_defconfig
index 0a8f1a0..0479c98 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -13,6 +13,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig 
b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 5162c2c..5b72ae1 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD

[U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
 - Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
 - Adjust the SPL BSS and MALLOC address.
v4:
 - Extend SPL max size and pad_to size for SD boot.
v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map.
 - Add emmc boot support.
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  13 ++
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 166 ++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  27 +++
 configs/ls1046ardb_qspi_defconfig  |  26 +++
 configs/ls1046ardb_sdcard_defconfig|  27 +++
 include/configs/ls1046a_common.h   | 175 +++
 include/configs/ls1046ardb.h   | 240 +
 22 files changed, 1470 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c871eaf..8c59c42 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,18 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   select DM_SPI_FLASH if DM_SPI
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -981,6 +993,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 756535b..b646aa0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express o

[U-Boot] [PATCH] armv8: ls1043a: Extend the size for SPL

[Gong Qianyu]

The SPL images are growing much bigger especially when DEBUG is ON.
So need to fix the values for them.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1043a_common.h | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e55fcb2..fa20e6d 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -69,16 +69,22 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0xf0
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR0x110
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
 
 #define CONFIG_SPL_TEXT_BASE   0x1000
-#define CONFIG_SPL_MAX_SIZE0x1d000
-#define CONFIG_SPL_STACK   0x1001e000
-#define CONFIG_SPL_PAD_TO  0x1d000
+/*
+ * CONFIG_SPL_MAX_SIZE is limited by OCRAM memory size(128 KiB) and
+ * a reserved stack size(4 KiB).
+ * So notice that even if DEBUG is ON, the SPL image(spl/u-boot-spl.bin)
+ * should not be > 124 KiB.
+ */
+#define CONFIG_SPL_MAX_SIZE0x1f000 /* 124 KiB */
+#define CONFIG_SPL_STACK   0x1002
+#define CONFIG_SPL_PAD_TO  0x21000 /* 132 KiB */
 
-#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SYS_TEXT_BASE + \
-   CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SPL_BSS_START_ADDR + \
+   CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
 #define CONFIG_SPL_BSS_START_ADDR  0x8010
 #define CONFIG_SPL_BSS_MAX_SIZE0x8
@@ -101,11 +107,12 @@
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_TEXT_BASE   0x1000
-#define CONFIG_SPL_MAX_SIZE0x1a000
-#define CONFIG_SPL_STACK   0x1001d000
+#define CONFIG_SPL_MAX_SIZE0x1d000 /* 116 KiB */
+#define CONFIG_SPL_STACK   0x1001f000
 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SPL_MALLOC_START0x8020
+#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SPL_BSS_START_ADDR + \
+   CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SPL_BSS_START_ADDR  0x8010
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10
 #define CONFIG_SPL_BSS_MAX_SIZE0x8
-- 
2.1.0.27.g96db324

___
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U-Boot@lists.denx.de
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[U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
 - Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
 - Adjust the SPL BSS and MALLOC address.
v4:
 - Extend SPL max size and pad_to size for SD boot.
v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map.
 - Add emmc boot support.
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  13 ++
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 166 ++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  26 +++
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 175 +++
 include/configs/ls1046ardb.h   | 240 +
 22 files changed, 1467 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c871eaf..8c59c42 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,18 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   select DM_SPI_FLASH if DM_SPI
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -981,6 +993,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 756535b..b646aa0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express o

[U-Boot] [Patch v6 9/9] armv8: ls1046aqds: Add LS1046AQDS board support

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

LS1046AQDS Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
 - Remove lpuart support.
 - Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
v5:
 - Fix SPL_PAD_TO size to block aligned value.
 - Adjust the SPL BSS and MALLOC address.
v4:
 - New Patch.

 arch/arm/Kconfig   |  13 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  77 
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  10 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 ++
 board/freescale/ls1046aqds/ls1046aqds.c| 298 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  31 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  32 ++
 include/configs/ls1046a_common.h   |  38 +-
 include/configs/ls1046aqds.h   | 487 +
 25 files changed, 1866 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8c59c42..5a5fb69 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,18 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046AQDS
+   bool "Support ls1046aqds"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   select DM_SPI_FLASH if DM_SPI
+   help
+ Support for Freescale LS1046AQDS platform.
+ The LS1046A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_LS1046ARDB
bool "Support ls1046ardb"
select ARM64
@@ -992,6 +1004,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b646aa0..b635dcf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-qds-duart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
new file mode 100644
index 000..10a95ea
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi 
b/arch/arm/dts/fsl-ls1046a-qds.dtsi
new file mode 100644
index 000..c512293
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Device Tree Include file for Freescale Laye

[U-Boot] [Patch v6 6/9] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
 - No change.
v2:
 - Add ERRATUM_A008511.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 430c85b..329f08f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -236,6 +236,12 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v6 7/9] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
 - No change.
v2:
 - Use values directly instead of macros. 
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..a60c928 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -222,6 +222,10 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   /* Disable SATA ECC */
+   out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
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[U-Boot] [Patch v6 5/9] armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r

[Gong Qianyu]

As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v6:
 - No change.
v5:
 - New Patch.

 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 19e34fa..b8e1d75 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -62,13 +62,8 @@ void board_init_f(ulong dummy)
i2c_init_all();
 #endif
dram_init();
-
-   /* Clear the BSS */
-   memset(__bss_start, 0, __bss_end - __bss_start);
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
 #endif
-   board_init_r(NULL, 0);
 }
 #endif
-- 
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[U-Boot] [Patch v6 3/9] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
 - No change.
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
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[U-Boot] [Patch v6 4/9] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v6:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5279981..430c85b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
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[U-Boot] [Patch v6 2/9] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v6:
 - No change.
v2:
 - Revise commmit message.

 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
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[U-Boot] [Patch v6 0/9] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This is version 6 patchset mainly to add support for both LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB or LS1046AQDS.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/

PCIe, USB and lpuart are not supported yet due to lack of some driver patches
and I'll send them to upstream once they're ready.
Please help to review. Thanks very much!

Changes in v6:
 - Remove lpuart support for QDS board.
 - Move CONFIG_FSL_QSPI to defconfig and select DM_SPI_FLASH in Kconfig.
Changes in v5:
 - Add a new patch to remove BSS clearing and board_init_r in spl.c. 
 - Fix SPL_PAD_TO size to block aligned value for NAND boot.
 - Adjust the SPL BSS and MALLOC address for future use.
Changes in v4:
 - Extend SPL max size and pad_to size for SD boot.
 - Add LS1046AQDS board support patch.
Changes in v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map in readme.
 - Add emmc boot support.
Changes in v2:
 - Add ERRATUM_A008511.
 - Use values directly instead of macros for SATA ECC. 
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.
 - Revise some commit messages.

Gong Qianyu (1):
  armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r

Mingkai Hu (2):
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (5):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR
  armv8: ls1046aqds: Add LS1046AQDS board support

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |  26 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|   5 -
 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  81 
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 ++
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   8 +
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  11 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 ++
 board/freescale/ls1046aqds/ls1046aqds.c| 298 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 board/freescale/ls1046ardb/Kconfig |  16 +
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 
 board/freescale/ls1046ardb/cpld.c  | 158 +++
 board/freescale/ls1046ardb/cpld.h  |  49 +++
 board/freescale/ls1046ardb/ddr.c   | 140 ++
 board/freescale/ls1046ardb/ddr.h   |  44 ++
 board/freescale/ls1046ardb/eth.c   |  77 
 board/freescale/ls1046ardb/ls1046ardb.c| 136 ++
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  31 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  32 ++
 configs/ls1046ardb_emmc_defconfig  |  26 ++
 configs/ls1046ardb_qspi_defconfig  |  25 ++
 configs/ls1046ardb_sdcard_defconfig|  26 ++
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 211 +
 include/configs/ls1046aqds.h   | 487 +
 include/conf

[U-Boot] [Patch v6 1/9] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v6:
 - No change.

 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index aaf7c02..042af09 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
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[U-Boot] [Patch v5 2/9] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
 - No change.
v2:
 - Revise commmit message.

 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
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[U-Boot] [Patch v5 6/9] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
 - No change.
v2:
 - Add ERRATUM_A008511.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 430c85b..329f08f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -236,6 +236,12 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
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[U-Boot] [Patch v5 1/9] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v5:
 - No change.

 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index aaf7c02..042af09 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
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[U-Boot] [Patch v5 9/9] armv8: ls1046aqds: Add LS1046AQDS board support

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

LS1046AQDS Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
 - Fix SPL_PAD_TO size to block aligned value.
 - Adjust the SPL BSS and MALLOC address.
v4:
 - New Patch.

 arch/arm/Kconfig   |  12 +
 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  81 
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  11 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 +
 board/freescale/ls1046aqds/ls1046aqds.c| 313 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_lpuart_defconfig|  29 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  30 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  31 ++
 include/configs/ls1046a_common.h   |  38 +-
 include/configs/ls1046aqds.h   | 494 +
 27 files changed, 1936 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2835a6d..810e922 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046AQDS
+   bool "Support ls1046aqds"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046AQDS platform.
+ The LS1046A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_LS1046ARDB
bool "Support ls1046ardb"
select ARM64
@@ -991,6 +1002,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b646aa0..4918213 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-qds-duart.dtb \
+   fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
new file mode 100644
index 000..10a95ea
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tr

[U-Boot] [Patch v5 8/9] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
 - Adjust the SPL BSS and MALLOC address.
v4:
 - Extend SPL max size and pad_to size for SD boot.
v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map.
 - Add emmc boot support.
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  12 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  26 +++
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 175 +++
 include/configs/ls1046ardb.h   | 242 +
 22 files changed, 1522 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c871eaf..2835a6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -981,6 +992,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 756535b..b646aa0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+   model = "LS1046A RDB Board";
+
+   alias

[U-Boot] [Patch v5 7/9] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
 - No change.
v2:
 - Use values directly instead of macros. 
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..a60c928 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -222,6 +222,10 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   /* Disable SATA ECC */
+   out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v5 4/9] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v5:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5279981..430c85b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v5 3/9] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v5:
 - No change.
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v5 5/9] armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r

[Gong Qianyu]

As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly.
Clearing BSS and calling board_init_r() will be done in crt0_64.S.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v5:
 - New Patch.

 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 19e34fa..b8e1d75 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -62,13 +62,8 @@ void board_init_f(ulong dummy)
i2c_init_all();
 #endif
dram_init();
-
-   /* Clear the BSS */
-   memset(__bss_start, 0, __bss_end - __bss_start);
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
 #endif
-   board_init_r(NULL, 0);
 }
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v5 0/9] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This is version 5 patchset mainly to add support for both LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB or LS1046AQDS.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/

PCIe and USB are not supported yet due to lack of some driver patches
and I'll send them to upstream once they're ready.
Please help to review. Thanks very much!

Changes in v5:
 - Add a new patch to remove BSS clearing and board_init_r in spl.c. 
 - Fix SPL_PAD_TO size to block aligned value for NAND boot.
 - Adjust the SPL BSS and MALLOC address for future use.
Changes in v4:
 - Extend SPL max size and pad_to size for SD boot.
 - Add LS1046AQDS board support patch.
Changes in v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map in readme.
 - Add emmc boot support.
Changes in v2:
 - Add ERRATUM_A008511.
 - Use values directly instead of macros for SATA ECC. 
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.
 - Revise some commit messages.

Gong Qianyu (1):
  armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r

Mingkai Hu (2):
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (5):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR
  armv8: ls1046aqds: Add LS1046AQDS board support

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 arch/arm/cpu/armv8/fsl-layerscape/spl.c|   5 -
 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  81 
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 ++
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   8 +
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  11 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 +
 board/freescale/ls1046aqds/ls1046aqds.c| 313 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 board/freescale/ls1046ardb/Kconfig |  16 +
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 
 board/freescale/ls1046ardb/cpld.c  | 158 +++
 board/freescale/ls1046ardb/cpld.h  |  49 ++
 board/freescale/ls1046ardb/ddr.c   | 140 ++
 board/freescale/ls1046ardb/ddr.h   |  44 ++
 board/freescale/ls1046ardb/eth.c   |  77 
 board/freescale/ls1046ardb/ls1046ardb.c| 136 ++
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_lpuart_defconfig|  29 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  30 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  31 ++
 configs/ls1046ardb_emmc_defconfig  |  26 ++
 configs/ls1046ardb_qspi_defconfig  |  25 ++
 configs/ls1046ardb_sdcard_defconfig|  26 ++
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 211 +
 include/configs/ls1046aqds.h   | 494 +
 include/configs/ls1046ardb.h   | 242 ++
 include/export

[U-Boot] [Patch v4 6/8] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
 - No change.
v2:
 - Use values directly instead of macros. 
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..a60c928 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -222,6 +222,10 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   /* Disable SATA ECC */
+   out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v4 3/8] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
 - No change.
v2:
 - Revise commmit message.

 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v4 7/8] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v4:
 - Extend SPL max size and pad_to size for SD boot.
v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map.
 - Add emmc boot support.
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  12 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  26 +++
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 176 +++
 include/configs/ls1046ardb.h   | 242 +
 22 files changed, 1523 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c871eaf..2835a6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -981,6 +992,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7d1944f..0215a55 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -142,6 +142,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+   model = "LS1046A RDB Board";
+
+   aliases {
+   spi0 = 
+   };

[U-Boot] [Patch v4 2/8] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
 - No change.
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v4 8/8] armv8: ls1046aqds: Add LS1046AQDS board support

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

LS1046AQDS Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v4:
 - New Patch.

 arch/arm/Kconfig   |  12 +
 arch/arm/dts/Makefile  |   2 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  81 
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  11 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 +
 board/freescale/ls1046aqds/ls1046aqds.c| 313 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_lpuart_defconfig|  29 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  30 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  31 ++
 include/configs/ls1046a_common.h   |  35 +-
 include/configs/ls1046aqds.h   | 498 +
 27 files changed, 1937 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2835a6d..810e922 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046AQDS
+   bool "Support ls1046aqds"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046AQDS platform.
+ The LS1046A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_LS1046ARDB
bool "Support ls1046ardb"
select ARM64
@@ -991,6 +1002,7 @@ source "board/freescale/ls2080ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1046aqds/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0215a55..e382f2d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -142,6 +142,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-qds-duart.dtb \
+   fsl-ls1046a-qds-lpuart.dtb \
fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
new file mode 100644
index 000..10a95ea
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1046a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
new file mode 100644
index 000..21243d0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright (C) 2016, Freesca

[U-Boot] [Patch v4 0/8] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This is version 4 patchset mainly to add support for both LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB or LS1046AQDS.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/

PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.
Please help to review. Thanks very much!

Changes in v4:
 - Extend SPL max size and pad_to size for SD boot.
 - Add LS1046AQDS board support patch.
Changes in v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map in readme.
 - Add emmc boot support.
Changes in v2:
 - Add ERRATUM_A008511.
 - Use values directly instead of macros for SATA ECC. 
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.
 - Revise some commit messages.


Mingkai Hu (2):
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (5):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR
  armv8: ls1046aqds: Add LS1046AQDS board support

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/fsl-ls1046a-qds-duart.dts |  16 +
 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts|  16 +
 arch/arm/dts/fsl-ls1046a-qds.dtsi  |  81 
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 ++
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   8 +
 board/freescale/common/vid.c   |   8 +-
 board/freescale/ls1046aqds/Kconfig |  15 +
 board/freescale/ls1046aqds/MAINTAINERS |  11 +
 board/freescale/ls1046aqds/Makefile|   9 +
 board/freescale/ls1046aqds/README  |  70 +++
 board/freescale/ls1046aqds/ddr.c   | 140 ++
 board/freescale/ls1046aqds/ddr.h   |  44 ++
 board/freescale/ls1046aqds/eth.c   | 415 +
 board/freescale/ls1046aqds/ls1046aqds.c| 313 +
 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg  |  17 +
 board/freescale/ls1046aqds/ls1046aqds_qixis.h  |  39 ++
 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg |   7 +
 .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg |   8 +
 .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg  |   8 +
 board/freescale/ls1046ardb/Kconfig |  16 +
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 
 board/freescale/ls1046ardb/cpld.c  | 158 +++
 board/freescale/ls1046ardb/cpld.h  |  49 ++
 board/freescale/ls1046ardb/ddr.c   | 140 ++
 board/freescale/ls1046ardb/ddr.h   |  44 ++
 board/freescale/ls1046ardb/eth.c   |  77 
 board/freescale/ls1046ardb/ls1046ardb.c| 136 ++
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046aqds_defconfig   |  28 ++
 configs/ls1046aqds_lpuart_defconfig|  29 ++
 configs/ls1046aqds_nand_defconfig  |  30 ++
 configs/ls1046aqds_qspi_defconfig  |  30 ++
 configs/ls1046aqds_sdcard_ifc_defconfig|  30 ++
 configs/ls1046aqds_sdcard_qspi_defconfig   |  31 ++
 configs/ls1046ardb_emmc_defconfig  |  26 ++
 configs/ls1046ardb_qspi_defconfig  |  25 ++
 configs/ls1046ardb_sdcard_defconfig|  26 ++
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 209 +
 include/configs/ls1046aqds.h   | 498 +
 include/configs/ls1046ardb.h   | 242 ++
 include/exports.h  |   2 +-
 52 files changed, 3494 insertions(+), 6 deletions(-)
-- 
2.1.0.27.g96db324

Regards,
Qianyu
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[U-Boot] [Patch v4 4/8] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v4:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5279981..430c85b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v4 1/8] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v4:
 - No change.

 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index aaf7c02..042af09 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v4 5/8] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3-v4:
 - No change.
v2:
 - Add ERRATUM_A008511.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 430c85b..329f08f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -236,6 +236,12 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
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[U-Boot] [RESEND Patch v2] net: fm: fix spi flash probe for using driver model

[Gong Qianyu]

The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Jagan Teki <jt...@openedev.com>
Reviewed-by: Joe Hershberger <joe.hershber...@ni.com>
---
v2:
 - Revised the comments as per Jagan's advice.

 drivers/net/fm/fm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 5eb773e..17a0886 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -368,8 +368,18 @@ int fm_init_common(int index, struct ccsr_fman *reg)
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
 
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   /* speed and mode will be read from DT */
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+0, 0, );
+
+   ucode_flash = dev_get_uclass_priv(new);
+#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
-- 
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[U-Boot] [Patch v3 5/7] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - No change.
v2:
 - Add ERRATUM_A008511.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 430c85b..329f08f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -236,6 +236,12 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 7/7] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map.
 - Add emmc boot support.
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  12 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  26 +++
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 176 +++
 include/configs/ls1046ardb.h   | 242 +
 22 files changed, 1523 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c871eaf..2835a6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -837,6 +837,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -981,6 +992,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7d1944f..0215a55 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -142,6 +142,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+   model = "LS1046A RDB Board";
+
+   aliases {
+   spi0 = 
+   };
+
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+

[U-Boot] [Patch v3 6/7] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - No change.
v2:
 - Use values directly instead of macros. 
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..a60c928 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -222,6 +222,10 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   /* Disable SATA ECC */
+   out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 2/7] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - No change.
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
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[U-Boot] [Patch v3 4/7] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v3:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5279981..430c85b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
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[U-Boot] [Patch v3 3/7] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - No change.
v2:
 - Revise commmit message.

 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
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[U-Boot] [Patch v3 0/7] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This is version 3 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/

PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.
Please help to review. Thanks very much!

Changes in v3:
 - Remove redundant sd rcw .cfg files.
 - Adjust the format of memory map in readme.
 - Add emmc boot support.
Changes in v2:
 - Add ERRATUM_A008511.
 - Use values directly instead of macros for SATA ECC. 
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.
 - Revise some commit messages.

Mingkai Hu (2):
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (4):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |  12 +
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   8 +
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   9 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  76 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 configs/ls1046ardb_emmc_defconfig  |  26 +++
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 176 +++
 include/configs/ls1046ardb.h   | 242 +
 include/exports.h  |   2 +-
 28 files changed, 1558 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1046a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1046a.dtsi
 create mode 100644 board/freescale/ls1046ardb/Kconfig
 create mode 100644 board/freescale/ls1046ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1046ardb/Makefile
 create mode 100644 board/freescale/ls1046ardb/README
 create mode 100644 board/freescale/ls1046ardb/cpld.c
 create mode 100644 board/freescale/ls1046ardb/cpld.h
 create mode 100644 board/freescale/ls1046ardb/ddr.c
 create mode 100644 board/freescale/ls1046ardb/ddr.h
 create mode 100644 board/freescale/ls1046ardb/eth.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
 create mode 100644 configs/ls1046ardb_emmc_defconfig
 create mode 100644 configs/ls1046ardb_qspi_defconfig
 create mode 100644 configs/ls1046ardb_sdcard_defconfig
 create mode 100644 include/configs/ls1046a_common.h
 create mode 100644 include/configs/ls1046ardb.h

-- 
2.1.0.27.g96db324

Regards,
Qianyu
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[U-Boot] [Patch v3 1/7] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2-v3:
 - No change.

 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d37e247..eacae62 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 6/7] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Use values directly instead of macros. 
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..a60c928 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -222,6 +222,10 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   /* Disable SATA ECC */
+   out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 5/7] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Add ERRATUM_A008511.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index c7e374c..c984988 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -238,6 +238,12 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
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[U-Boot] [Patch v2 2/7] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Revise commit message.

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 1/7] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - No change.

 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d37e247..eacae62 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 7/7] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
v2:
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.

 arch/arm/Kconfig   |  12 ++
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   8 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  77 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1200.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1400.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_5506.cfg  |   7 +
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 177 +++
 include/configs/ls1046ardb.h   | 237 +
 24 files changed, 1514 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c..01bfce2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -811,6 +811,17 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046ARDB platform.
+ The LS1046A Reference Design Board (RDB) is a high-performance
+ development platform that supports the QorIQ LS1046A
+ Layerscape Architecture processor.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -954,6 +965,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 223124e..95b40f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -142,6 +142,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..4902454
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+   model = "LS1046A RDB Board";
+
+   aliases {
+   spi0 = 
+   };
+
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s

[U-Boot] [Patch v2 3/7] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Revise commmit message.

 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
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[U-Boot] [Patch v2 4/7] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..c7e374c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
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[U-Boot] [Patch v2 0/7] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This is version 2 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/

PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.
Please help to review. Thanks very much!

Changes in v2:
 - Add ERRATUM_A008511.
 - Use values directly instead of macros for SATA ECC. 
 - Add >60 characters' paragraph for the board help.
 - Fix the memory map in readme.
 - Remove unused flash r/w functions.
 - Remove DDR3 defines.
 - Revise some commit messages.

Mingkai Hu (2):
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (4):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |  12 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   4 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   8 +
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   8 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  77 +++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 136 
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1200.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1400.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_5506.cfg  |   7 +
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 177 +++
 include/configs/ls1046ardb.h   | 237 +
 include/exports.h  |   2 +-
 30 files changed, 1549 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1046a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1046a.dtsi
 create mode 100644 board/freescale/ls1046ardb/Kconfig
 create mode 100644 board/freescale/ls1046ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1046ardb/Makefile
 create mode 100644 board/freescale/ls1046ardb/README
 create mode 100644 board/freescale/ls1046ardb/cpld.c
 create mode 100644 board/freescale/ls1046ardb/cpld.h
 create mode 100644 board/freescale/ls1046ardb/ddr.c
 create mode 100644 board/freescale/ls1046ardb/ddr.h
 create mode 100644 board/freescale/ls1046ardb/eth.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_1200.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_1400.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_5506.cfg
 create mode 100644 configs/ls1046ardb_qspi_defconfig
 create mode 100644 configs/ls1046ardb_sdcard_defconfig
 create mode 100644 include/configs/ls1046a_common.h
 create mode 100644 include/configs/ls1046ardb.h

-- 
2.1.0.27.g96db324

Regards,
Qianyu
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[U-Boot] [PATCH 0/8] Add LS1046ARDB board support

[Gong Qianyu]

Hi all,

This patchset mainly adds support for LS1046ARDB board. Tested on
LS1046ARDB board. 
PCIe and USB are not supported yet due to lack of some driver patches
and I'll add them once they're ready for upstream.

Please help to review. Thanks!


Mingkai Hu (3):
  drivers/ddr/fsl: add DEBUG_38
  armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM
latency
  armv8: ls1046ardb: Add LS1046ARDB board support

Shaohui Xie (4):
  ddr: fsl: fix a compile issue
  Export memset for standalone AQ FW load apps
  armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for
standalone app
  armv8: ls1046a: disable SATA ECC in DCSR

Shengzhou Liu (1):
  armv8: ls1046a: Enable DDR erratum for ls1046a

 arch/arm/Kconfig   |   9 +
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S   |  15 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|   6 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   7 +
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   8 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  67 ++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 173 +++
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1200.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1400.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_5506.cfg  |   7 +
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 drivers/ddr/fsl/ctrl_regs.c|   2 +
 drivers/ddr/fsl/fsl_ddr_gen4.c |   7 +-
 include/_exports.h |   1 +
 include/configs/ls1046a_common.h   | 181 
 include/configs/ls1046ardb.h   | 237 +
 include/exports.h  |   2 +-
 31 files changed, 1580 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1046a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1046a.dtsi
 create mode 100644 board/freescale/ls1046ardb/Kconfig
 create mode 100644 board/freescale/ls1046ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1046ardb/Makefile
 create mode 100644 board/freescale/ls1046ardb/README
 create mode 100644 board/freescale/ls1046ardb/cpld.c
 create mode 100644 board/freescale/ls1046ardb/cpld.h
 create mode 100644 board/freescale/ls1046ardb/ddr.c
 create mode 100644 board/freescale/ls1046ardb/ddr.h
 create mode 100644 board/freescale/ls1046ardb/eth.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb.c
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_1200.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_1400.cfg
 create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd_5506.cfg
 create mode 100644 configs/ls1046ardb_qspi_defconfig
 create mode 100644 configs/ls1046ardb_sdcard_defconfig
 create mode 100644 include/configs/ls1046a_common.h
 create mode 100644 include/configs/ls1046ardb.h

-- 
2.1.0.27.g96db324

Regards,
Qianyu
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[U-Boot] [PATCH 2/8] ddr: fsl: fix a compile issue

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 drivers/ddr/fsl/fsl_ddr_gen4.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index c2f8a8b..c0bf1a0 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 temp_sdram_cfg;
u32 total_gb_size_per_controller;
int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+   defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+   u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-   u32 temp32, mr6;
+   u32 mr6;
u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
u32 *vref_seq = vref_seq1;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

Use 3 cycles.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S 
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5af6b73..6451a36 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -179,6 +179,21 @@ ENTRY(lowlevel_init)
isb
dsb sy
 #endif
+
+#ifdef CONFIG_LS1046A
+   /* Initialize the L2 RAM latency */
+   mrs   x1, S3_1_c11_c0_2
+   mov   x0, #0x1C7
+   /* Clear L2 Tag RAM latency and L2 Data RAM latency */
+   bic   x1, x1, x0
+   /* Set L2 data ram latency bits [2:0] */
+   orr   x1, x1, #0x2
+   /* set L2 tag ram latency bits [8:6] */
+   orr   x1,  x1, #0x80
+   msr   S3_1_c11_c0_2, x1
+   isb
+#endif
+
mov lr, x29 /* Restore LR */
ret
 ENDPROC(lowlevel_init)
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 8/8] armv8: ls1046ardb: Add LS1046ARDB board support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

LS1046ARDB Specification:
-
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
 arch/arm/Kconfig   |   9 +
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  44 
 arch/arm/dts/fsl-ls1046a.dtsi  | 220 +++
 board/freescale/ls1046ardb/Kconfig |  16 ++
 board/freescale/ls1046ardb/MAINTAINERS |   8 +
 board/freescale/ls1046ardb/Makefile|  10 +
 board/freescale/ls1046ardb/README  |  67 ++
 board/freescale/ls1046ardb/cpld.c  | 158 ++
 board/freescale/ls1046ardb/cpld.h  |  49 +
 board/freescale/ls1046ardb/ddr.c   | 140 
 board/freescale/ls1046ardb/ddr.h   |  44 
 board/freescale/ls1046ardb/eth.c   |  77 +++
 board/freescale/ls1046ardb/ls1046ardb.c| 173 +++
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg  |  22 ++
 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg |   7 +
 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg   |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1200.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_1400.cfg  |   7 +
 .../ls1046ardb/ls1046ardb_rcw_sd_5506.cfg  |   7 +
 configs/ls1046ardb_qspi_defconfig  |  25 +++
 configs/ls1046ardb_sdcard_defconfig|  26 +++
 include/configs/ls1046a_common.h   | 181 
 include/configs/ls1046ardb.h   | 237 +
 24 files changed, 1542 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c..d343995 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -811,6 +811,14 @@ config TARGET_LS1043ARDB
help
  Support for Freescale LS1043ARDB platform.
 
+config TARGET_LS1046ARDB
+   bool "Support ls1046ardb"
+   select ARM64
+   select ARMV8_MULTIENTRY
+   select SUPPORT_SPL
+   help
+ Support for Freescale LS1046ARDB platform.
+
 config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -954,6 +962,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 223124e..95b40f6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -142,6 +142,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
+   fsl-ls1046a-rdb.dtb \
fsl-ls1012a-qds.dtb \
fsl-ls1012a-rdb.dtb \
fsl-ls1012a-frdm.dtb
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 000..91f6ced
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,44 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * Mingkai Hu <mingkai...@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1046a.dtsi"
+
+/ {
+   model = "LS1046A RDB Board";
+
+aliases {
+   spi0 = 
+};
+
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fs512s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <5000>;
+   reg = <0>;
+   };
+
+   qflash1: s25fs512s@1 {
+   #address-cells = <1>;
+  

[U-Boot] [PATCH 1/8] drivers/ddr/fsl: add DEBUG_38

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

DEBUG_38 is needed for rev2 DDR controller.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 drivers/ddr/fsl/ctrl_regs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 24fd366..4ae8b80 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2526,5 +2526,7 @@ compute_fsl_memctl_config_regs(const unsigned int 
ctrl_num,
ddr->debug[2] |= 0x0200;/* set bit 22 */
 #endif
 
+   ddr->debug[37] = 0x8000;
+
return check_fsl_memctl_config_regs(ddr);
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a

[Gong Qianyu]

From: Shengzhou Liu <shengzhou@nxp.com>

Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165

Signed-off-by: Shengzhou Liu <shengzhou@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index c7e374c..3250290 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -238,6 +238,11 @@
 #define GICC_BASE  0x0142
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+
+#define CONFIG_SYS_FSL_ERRATUM_A009801
+#define CONFIG_SYS_FSL_ERRATUM_A009803
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 #else
 #error SoC not defined
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 4/8] Export memset for standalone AQ FW load apps

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

commit 952793150 'board/ls2085rdb: Export functions for standalone
AQ FW load apps' mentioned memset was exported but it was not,
this patch exports the memset.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/_exports.h | 1 +
 include/exports.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/_exports.h b/include/_exports.h
index 11beeb2..1584705 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -75,6 +75,7 @@
const char *, char **, unsigned int)
EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+   EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
 #ifdef CONFIG_PHY_AQUANTIA
EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
mdio_get_current_dev, void)
diff --git a/include/exports.h b/include/exports.h
index deef8fb..1d81bc4 100644
--- a/include/exports.h
+++ b/include/exports.h
@@ -57,7 +57,7 @@ struct jt_funcs {
 };
 
 
-#define XF_VERSION 8
+#define XF_VERSION 9
 
 #if defined(CONFIG_X86)
 extern gd_t *global_data;
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

So to fix SATA CRC error.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d..f1c6964 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -22,6 +22,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SATA_ECC_REG_ADDR  0x20140520
+#define SATA_ECC_DISABLE   0x8000
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -222,6 +225,9 @@ int sata_init(void)
 {
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
 
+#ifdef CONFIG_LS1046A
+   out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 5/8] armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone app

[Gong Qianyu]

From: Shaohui Xie <shaohui@nxp.com>

The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..c7e374c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -9,6 +9,8 @@
 
 #include 
 
+#define CONFIG_STANDALONE_LOAD_ADDR0x8030
+
 #ifdef CONFIG_SYS_FSL_DDR4
 #define CONFIG_SYS_FSL_DDRC_GEN4
 #else
-- 
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[U-Boot] [Patch v2] net: fm: fix spi flash probe for using driver model

[Gong Qianyu]

The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Jagan Teki <jt...@openedev.com>
---
v2:
 - Revised the comments as per Jagan's advice.

 drivers/net/fm/fm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 00cdfd4..4a3e463 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -371,8 +371,18 @@ int fm_init_common(int index, struct ccsr_fman *reg)
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
 
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   /* speed and mode will be read from DT */
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+0, 0, );
+
+   ucode_flash = dev_get_uclass_priv(new);
+#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3] armv8: ls1043aqds: add IFC fixup in case QSPI is enabled

[Gong Qianyu]

QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - Moved the fixup to board file.
 - Detected the muxing through QIXIS at runtime.
 - Tested on LS1043AQDS board.

 board/freescale/ls1043aqds/ls1043aqds.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index b7e9c21..941dfbc 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -327,6 +327,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
+   u8 reg;
 
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
@@ -341,6 +342,15 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
 #endif
+
+   reg = QIXIS_READ(brdcfg[0]);
+   reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+   /* Disable IFC if QSPI is enabled */
+   if (reg == 0xF)
+   do_fixup_by_compat(blob, "fsl,ifc",
+  "status", "disabled", 8 + 1, 1);
+
return 0;
 }
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] config.h: clean unused CONFIG_ENV_SPI_* if using driver model

[Gong Qianyu]

When using SPI driver model, it will get the values from DT. So
there is no need to set CONFIG_ENV_SPI_MAX_HZ and
CONFIG_ENV_SPI_MODE any more.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1012a_common.h | 2 --
 include/configs/ls1043a_common.h | 2 --
 2 files changed, 4 deletions(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index fba2fac..1602f09 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -52,8 +52,6 @@
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
 #define CONFIG_ENV_SPI_BUS 0
 #define CONFIG_ENV_SPI_CS  0
-#define CONFIG_ENV_SPI_MAX_HZ  100
-#define CONFIG_ENV_SPI_MODE0x03
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_FSL_SPI_INTERFACE
 #define CONFIG_SF_DATAFLASH
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index b0d4a8d..028f7d9 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -222,8 +222,6 @@
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
 #define CONFIG_ENV_SPI_BUS 0
 #define CONFIG_ENV_SPI_CS  0
-#define CONFIG_ENV_SPI_MAX_HZ  100
-#define CONFIG_ENV_SPI_MODE0x03
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* FMan fireware Pre-load address */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] net: fm: fix spi flash probe for using driver model

[Gong Qianyu]

The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 drivers/net/fm/fm.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 00cdfd4..6308d22 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -371,8 +371,18 @@ int fm_init_common(int index, struct ccsr_fman *reg)
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
 
+#ifdef CONFIG_DM_SPI_FLASH
+   struct udevice *new;
+
+   /* Will get the speed and mode from Device Tree */
+   ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+0, 0, );
+
+   ucode_flash = dev_get_uclass_priv(new);
+#else
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2] armv8: Enable CPUECTLR.SMPEN for coherency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
v2:
 - Revise commit message, add for A57/A72 part.
 - Add comments above the code.

 arch/arm/cpu/armv8/start.S | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..dfce469 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,14 @@ reset:
msr cpacr_el1, x0   /* Enable FP/SIMD */
 0:
 
+   /* Enalbe SMPEN bit for coherency.
+* This register is not architectural but at the moment
+* this bit should be set for A53/A57/A72.
+*/
+   mrs x0, S3_1_c15_c2_1   /* cpuactlr_el1 */
+   orr x0, x0, #0x40
+   msr S3_1_c15_c2_1, x0
+
/* Apply ARM core specific erratas */
bl  apply_core_errata
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 0/5] armv8: fsl-layerscape: Add LS1046A SoC support

[Gong Qianyu]

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Change History:

[Patch v3 1/5] armv8: fsl-layerscape: Add A72 core detection
v3:
 - Revise commit message.
v2:
 - Add commit message.

[Patch v3 2/5] armv8: fsl-layerscape: Consolidate the LSCH2 common
v3:
 - New patch.

[Patch v3 3/5] armv8: fsl_lsch2: Add SerDes 2 support
v3:
 - Revise commit message.
v2:
 - New patch.

[Patch v3 4/5] armv8: fsl_lsch2: Add LS1046A SoC support
v3:
 - Fix the part in config.h as per the consolidation patch.
v2:
 - Move serdes 2 support to a new patch.
 - Fix SVR and add LS1026A SVR.
 - Add SoC descriptions in README.soc.
 - Remove ls1046a errata.

[Patch v3 5/5] drivers: net/fm: Add Fman support for LS1046A
v3:
 - Revise commit message.
v2:
 - Add commit message.


Alison Wang (1):
  armv8: fsl-layerscape: Add A72 core detection

Gong Qianyu (2):
  armv8: fsl-layerscape: Consolidate the LSCH2 common defines
  armv8: fsl_lsch2: Add SerDes 2 support

Mingkai Hu (2):
  armv8: fsl_lsch2: Add LS1046A SoC support
  drivers: net/fm: Add Fman support for LS1046A

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|   3 +-
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  42 +++
 .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c|  19 
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  25 -
 arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c |  99 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  82 +++---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |   2 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   3 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   1 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |   2 +
 drivers/net/fm/Makefile|   1 +
 drivers/net/fm/ls1046.c| 123 +
 14 files changed, 368 insertions(+), 41 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
 create mode 100644 drivers/net/fm/ls1046.c

-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 4/5] armv8: fsl_lsch2: Add LS1046A SoC support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang <zhiqiang@nxp.com>
Signed-off-by: Mihai Bantea <mihai.ban...@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - No change.
v2:
 - Move serdes 2 support to a new patch.
 - Fix SVR and add LS1026A SVR.
 - Add SoC descriptions in README.soc.
 - Remove ls1046a errata.

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |  4 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 42 +
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 27 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  2 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  2 +
 8 files changed, 200 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..4df467d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -32,3 +32,7 @@ endif
 ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index 8eee016..f7b949a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -3,6 +3,7 @@ SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
+   4. LS1046A
 
 LS1043A
 -
@@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and 
features:
 - Two WatchDog timers
 - ARM generic timer
  - QorIQ platform's trust architecture 2.1
+
+LS1046A
+
+The LS1046A integrated multicore processor combines four ARM Cortex-A72
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1046A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A72 CPUs
+ - 2 MB unified L2 Cache
+ - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Two Configurable x4 SerDes
+   - Two PLLs per four-lane SerDes
+   - Support for 10G operation
+ - Ethernet interfaces by FMan
+   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
+   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
+   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
+   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
+ - High-speed peripheral interfaces
+   - Three PCIe 3.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC) supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index d0dc58d..8922197 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+   case 4:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+   break;
+   case 5:
+   sys_info->freq_fman[0] = sys_info->freq_systembus;
+   break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(>rcwsr[15]);
-   rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
-   sys_info->freq_sdhc = freq_c_pl

[U-Boot] [Patch v3 3/5] armv8: fsl_lsch2: Add SerDes 2 support

[Gong Qianyu]

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - Revise commit message.
v2:
 - New Patch.

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c  | 19 +++
 arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h |  1 +
 .../arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  2 ++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a..f73092a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
 #ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   ret |= serdes2_prtcl_map[device];
+#endif
 
return !!ret;
 }
@@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   case FSL_SRDS_2:
+   cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+   cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+   break;
+#endif
default:
printf("invalid SerDes%d\n", sd);
break;
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   serdes_init(FSL_SRDS_2,
+   CONFIG_SYS_FSL_SERDES_ADDR,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+   serdes2_prtcl_map);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 487cba8..1f33404 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
 
 enum srds {
FSL_SRDS_1  = 0,
+   FSL_SRDS_2  = 1,
 };
 
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index cbb252c..05f497c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -228,6 +228,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0x
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK   0x
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT  0
 #define RCW_SB_EN_REG_INDEX7
 #define RCW_SB_EN_MASK 0x0020
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 1/5] armv8: fsl-layerscape: Add A72 core detection

[Gong Qianyu]

From: Alison Wang <b18...@freescale.com>

Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - Revise commit message.
v2:
 - Added commit messages.

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 ++-
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..b810d01 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -558,7 +558,8 @@ int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz  ", core,
   type == TY_ITYP_VER_A7 ? "A7 " :
   (type == TY_ITYP_VER_A53 ? "A53" :
-   (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+  (type == TY_ITYP_VER_A57 ? "A57" :
+  (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
   strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n   Bus:  %-4s MHz  ",
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c1..cbb252c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
 #define TY_ITYP_VER_A7  0x1
 #define TY_ITYP_VER_A53 0x2
 #define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0xc000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK0x003f  /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb..4d54ab2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -156,6 +156,7 @@
 #define TY_ITYP_VER_A7 0x1
 #define TY_ITYP_VER_A530x2
 #define TY_ITYP_VER_A570x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0x8000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x003f  /* initiator mask */
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 2/5] armv8: fsl-layerscape: Consolidate the LSCH2 common defines

[Gong Qianyu]

Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - New Patch.

 arch/arm/include/asm/arch-fsl-layerscape/config.h | 59 ---
 1 file changed, 20 insertions(+), 39 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 44fe0c0..7116f9d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -149,43 +149,43 @@
 #define CONFIG_ARM_ERRATA_833471
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
-#elif defined(CONFIG_LS1043A)
-#define CONFIG_MAX_CPUS4
+#elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_SYS_FMAN_V3
-#define CONFIG_SYS_NUM_FMAN1
-#define CONFIG_SYS_NUM_FM1_DTSEC   7
-#define CONFIG_SYS_NUM_FM1_10GEC   1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
 #define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x0100
 #define CONFIG_SYS_FSL_SEC_COMPAT  5
 #define CONFIG_SYS_FSL_OCRAM_BASE  0x1000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE  0x20 /* 2 MiB */
-#define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED  CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_OCRAM_SIZE  0x0020 /* 2M */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x0100
 
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_PEX_LUT_BE
+#define CONFIG_SYS_FSL_SEC_BE
+
+#define CONFIG_SYS_FSL_SRDS_1
+/* SoC related */
+#ifdef CONFIG_LS1043A
+#define CONFIG_MAX_CPUS4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN1
+#define CONFIG_SYS_NUM_FM1_DTSEC   7
+#define CONFIG_SYS_NUM_FM1_10GEC   1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED  CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE  0x6000UL
 #define MAX_QE_RISC1
 #define QE_NUM_OF_SNUM 28
 
-#define SRDS_MAX_LANES 4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-
+#define CONFIG_SYS_FSL_IFC_BE
 #define CONFIG_SYS_FSL_SFP_VER_3_2
 #define CONFIG_SYS_FSL_SEC_MON_BE
-#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
@@ -205,32 +205,13 @@
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #elif defined(CONFIG_LS1012A)
 #define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_CACHELINE_SIZE  64
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0x0100
-#define CONFIG_SYS_FSL_SEC_COMPAT  5
 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
-#define CONFIG_SYS_FSL_OCRAM_BASE  0x1000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE  0x20 /* 2 MiB */
-
 #define GICD_BASE  0x01401000
 #define GICC_BASE  0x01402000
-
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
-
-#define SRDS_MAX_LANES 4
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
+#endif
 
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v3 5/5] drivers: net/fm: Add Fman support for LS1046A

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v3:
 - Revise commit message.
v2:
 - Add commit messages.

 drivers/net/fm/Makefile |   1 +
 drivers/net/fm/ls1046.c | 123 
 2 files changed, 124 insertions(+)

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
 obj-$(CONFIG_LS1043A)  += ls1043.o
+obj-$(CONFIG_LS1046A)  += ls1046.o
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
new file mode 100644
index 000..bf4
--- /dev/null
+++ b/drivers/net/fm/ls1046.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define FSL_CHASSIS2_RCWSR13_EC1   0xe000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO  0x2000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM   0xa000
+#define FSL_CHASSIS2_RCWSR13_EC2   0x1c00 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO  0x0400
+#define FSL_CHASSIS2_RCWSR13_EC2_1588  0x0800
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM   0x1400
+
+u32 port_to_devdisr[] = {
+   [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+   [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+   [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+   [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+   [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+   [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+   [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+   [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+   [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+   [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+   [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+   [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 devdisr2 = in_be32(>devdisr2);
+
+   return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+   setbits_be32(>devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 rcwsr13 = in_be32(>rcwsr[13]);
+
+   if (is_device_disabled(port))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if (port == FM1_DTSEC3)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+   FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   if (port == FM1_DTSEC4)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+   FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   /* handle SGMII, only MAC 2/5/6/9/10 available */
+   switch (port) {
+   case FM1_DTSEC2:
+   case FM1_DTSEC5:
+   case FM1_DTSEC6:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
+   return PHY_INTERFACE_MODE_SGMII;
+   break;
+   default:
+   break;
+   }
+
+   /* handle 2.5G SGMII, only MAC 5/9/10 available */
+   switch (port) {
+   case FM1_DTSEC5:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
+port - FM1_DTSEC5))
+   return PHY_INTERFACE_MODE_SGMII_2500;
+   break;
+   default:
+   break;
+   }
+
+   /* handle QSGMII, o

[U-Boot] [Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support

[Gong Qianyu]

This patch adds serdes 2 support for FSL_LSCH2.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - New patch.

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c  | 19 +++
 arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h |  1 +
 .../arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  2 ++
 3 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a..f73092a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
 #ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   ret |= serdes2_prtcl_map[device];
+#endif
 
return !!ret;
 }
@@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   case FSL_SRDS_2:
+   cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+   cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+   break;
+#endif
default:
printf("invalid SerDes%d\n", sd);
break;
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   serdes_init(FSL_SRDS_2,
+   CONFIG_SYS_FSL_SERDES_ADDR,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+   serdes2_prtcl_map);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h 
b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 606b667..e1b3f44 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -140,6 +140,7 @@ enum srds_prtcl {
 
 enum srds {
FSL_SRDS_1  = 0,
+   FSL_SRDS_2  = 1,
 };
 
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index cbb252c..05f497c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -228,6 +228,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0x
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK   0x
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT  0
 #define RCW_SB_EN_REG_INDEX7
 #define RCW_SB_EN_MASK 0x0020
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection

[Gong Qianyu]

From: Alison Wang <b18...@freescale.com>

Add support to detect Cortex-A72 core for printing it out.

Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Added commit messages.

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 ++-
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..b810d01 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -558,7 +558,8 @@ int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz  ", core,
   type == TY_ITYP_VER_A7 ? "A7 " :
   (type == TY_ITYP_VER_A53 ? "A53" :
-   (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+  (type == TY_ITYP_VER_A57 ? "A57" :
+  (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
   strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n   Bus:  %-4s MHz  ",
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c1..cbb252c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
 #define TY_ITYP_VER_A7  0x1
 #define TY_ITYP_VER_A53 0x2
 #define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0xc000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK0x003f  /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb..4d54ab2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -156,6 +156,7 @@
 #define TY_ITYP_VER_A7 0x1
 #define TY_ITYP_VER_A530x2
 #define TY_ITYP_VER_A570x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0x8000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x003f  /* initiator mask */
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2] driver: net: phylib: add support for aquantia AQR106/107 PHY

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

This patch adds support for aquantia AQR106/107 PHY.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 drivers/net/phy/aquantia.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver = {
.shutdown = _shutdown,
 };
 
+struct phy_driver aqr106_driver = {
+   .name = "Aquantia AQR106",
+   .uid = 0x3a1b4d0,
+   .mask = 0xfff0,
+   .features = PHY_10G_FEATURES,
+   .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+   MDIO_MMD_PHYXS | MDIO_MMD_AN |
+   MDIO_MMD_VEND1),
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
+struct phy_driver aqr107_driver = {
+   .name = "Aquantia AQR107",
+   .uid = 0x3a1b4e0,
+   .mask = 0xfff0,
+   .features = PHY_10G_FEATURES,
+   .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+   MDIO_MMD_PHYXS | MDIO_MMD_AN |
+   MDIO_MMD_VEND1),
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
 struct phy_driver aqr405_driver = {
.name = "Aquantia AQR405",
.uid = 0x3a1b4b2,
@@ -165,6 +191,8 @@ int phy_aquantia_init(void)
phy_register(_driver);
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
+   phy_register(_driver);
phy_register(_driver);
 
return 0;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang <zhiqiang@nxp.com>
Signed-off-by: Mihai Bantea <mihai.ban...@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Move serdes 2 support to a new patch.
 - Fix SVR and add LS1026A SVR.
 - Add SoC descriptions in README.soc.
 - Remove ls1046a errata.

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |  4 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 42 +
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 +-
 arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99 ++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  | 45 ++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  2 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/soc.h |  2 +
 8 files changed, 218 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..4df467d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -32,3 +32,7 @@ endif
 ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc 
b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index 8eee016..f7b949a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -3,6 +3,7 @@ SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
+   4. LS1046A
 
 LS1043A
 -
@@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and 
features:
 - Two WatchDog timers
 - ARM generic timer
  - QorIQ platform's trust architecture 2.1
+
+LS1046A
+
+The LS1046A integrated multicore processor combines four ARM Cortex-A72
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1046A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A72 CPUs
+ - 2 MB unified L2 Cache
+ - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Two Configurable x4 SerDes
+   - Two PLLs per four-lane SerDes
+   - Support for 10G operation
+ - Ethernet interfaces by FMan
+   - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+   - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
+   - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
+   - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
+   - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
+ - High-speed peripheral interfaces
+   - Three PCIe 3.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC) supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index d0dc58d..8922197 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+   case 4:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+   break;
+   case 5:
+   sys_info->freq_fman[0] = sys_info->freq_systembus;
+   break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(>rcwsr[15]);
-   rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
-   sys_info->freq_sdhc = freq_c_pl

[U-Boot] [Patch v2 0/4] armv8: fsl-layerscape: Add LS1046A SoC support

[Gong Qianyu]

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Change history:

[Patch v2 1/4] armv8: fsl-layerscape: Add A72 core detection
v2:
 - Add commit messages.

[Patch v2 2/4] armv8/fsl_lsch2: Add LS1046A SoC support
v2:
 - Move serdes 2 support to a new patch.
 - Fix SVR and add LS1026A SVR.
 - Add SoC descriptions in README.soc.
 - Remove ls1046a errata.

[Patch v2 3/4] armv8: fsl_lsch2: Add serdes 2 support
v2:
 - New patch.

[Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A
v2:
 - Add commit messages.


Regards,
Qianyu
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[U-Boot] [Patch v2 4/4] drivers: net/fm: Add Fman support for LS1046A

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

This patch adds Fman support for LS1046A SoC.

Signed-off-by: Shaohui Xie <shaohui@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
v2:
 - Add commit messages.

 drivers/net/fm/Makefile |   1 +
 drivers/net/fm/ls1046.c | 123 
 2 files changed, 124 insertions(+)

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
 obj-$(CONFIG_LS1043A)  += ls1043.o
+obj-$(CONFIG_LS1046A)  += ls1046.o
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
new file mode 100644
index 000..bf4
--- /dev/null
+++ b/drivers/net/fm/ls1046.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define FSL_CHASSIS2_RCWSR13_EC1   0xe000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO  0x2000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM   0xa000
+#define FSL_CHASSIS2_RCWSR13_EC2   0x1c00 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO  0x0400
+#define FSL_CHASSIS2_RCWSR13_EC2_1588  0x0800
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM   0x1400
+
+u32 port_to_devdisr[] = {
+   [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+   [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+   [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+   [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+   [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+   [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+   [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+   [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+   [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+   [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+   [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+   [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 devdisr2 = in_be32(>devdisr2);
+
+   return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+   setbits_be32(>devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 rcwsr13 = in_be32(>rcwsr[13]);
+
+   if (is_device_disabled(port))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if (port == FM1_DTSEC3)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+   FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   if (port == FM1_DTSEC4)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+   FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   /* handle SGMII, only MAC 2/5/6/9/10 available */
+   switch (port) {
+   case FM1_DTSEC2:
+   case FM1_DTSEC5:
+   case FM1_DTSEC6:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
+   return PHY_INTERFACE_MODE_SGMII;
+   break;
+   default:
+   break;
+   }
+
+   /* handle 2.5G SGMII, only MAC 5/9/10 available */
+   switch (port) {
+   case FM1_DTSEC5:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
+port - FM1_DTSEC5))
+   return PHY_INTERFACE_MODE_SGMII_2500;
+   break;
+   default:
+   break;
+   }
+
+   /* handle QSGMII, only MAC 1/5/6/10 available */
+   switch (port) {
+   case FM1_DTSEC

[U-Boot] [PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang <zhiqiang@nxp.com>
Signed-off-by: Mihai Bantea <mihai.ban...@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index eb2cbc3..4df467d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -32,3 +32,7 @@ endif
 ifneq ($(CONFIG_LS1012A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index fe3444a..f73092a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 int is_serdes_configured(enum srds_prtcl device)
 {
@@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
 #ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   ret |= serdes2_prtcl_map[device];
+#endif
 
return !!ret;
 }
@@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   case FSL_SRDS_2:
+   cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
+   cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
+   break;
+#endif
default:
printf("invalid SerDes%d\n", sd);
break;
@@ -114,4 +126,11 @@ void fsl_serdes_init(void)
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+   serdes_init(FSL_SRDS_2,
+   CONFIG_SYS_FSL_SERDES_ADDR,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
+   FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
+   serdes2_prtcl_map);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index d0dc58d..8922197 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+   case 4:
+   sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+   break;
+   case 5:
+   sys_info->freq_fman[0] = sys_info->freq_systembus;
+   break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(>rcwsr[15]);
-   rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
-   sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+   switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+   case 1:
+   sys_info->freq_sdhc = freq_c_pll[1];
+   break;
+   case 2:
+   sys_info->freq_sdhc = freq_c_pll[1] / 2;
+   break;
+   case 3:
+   sys_info->freq_sdhc = freq_c_pll[1] / 3;
+   break;
+   case 6:
+   sys_info->freq_sdhc = freq_c_pll[0] / 2;
+   break;
+   default:
+   printf("Error: Unknown ESDHC clock select!\n");
+   break;
+   }
 #else
sys_info->freq_sdhc = sys_info->freq_systembus;
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
new file mode 100644
index 000..1da6b71
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+struct serdes_config {
+   u32 protocol;
+   u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+   /* SerDes 1 */
+   {0x, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+   {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10,

[U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Add A72 core detection

[Gong Qianyu]

From: Alison Wang <b18...@freescale.com>

Signed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8062106..b810d01 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -558,7 +558,8 @@ int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz  ", core,
   type == TY_ITYP_VER_A7 ? "A7 " :
   (type == TY_ITYP_VER_A53 ? "A53" :
-   (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+  (type == TY_ITYP_VER_A57 ? "A57" :
+  (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
   strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n   Bus:  %-4s MHz  ",
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8b8a7c1..cbb252c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
 #define TY_ITYP_VER_A7  0x1
 #define TY_ITYP_VER_A53 0x2
 #define TY_ITYP_VER_A57 0x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0xc000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK0x003f  /* initiator mask */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3ad46eb..4d54ab2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -156,6 +156,7 @@
 #define TY_ITYP_VER_A7 0x1
 #define TY_ITYP_VER_A530x2
 #define TY_ITYP_VER_A570x3
+#define TY_ITYP_VER_A720x4
 
 #define TP_CLUSTER_EOC 0x8000  /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x003f  /* initiator mask */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/3] armv8/ls1046a: Add Fman support

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

Signed-off-by: Shaohui Xie <shaohui@freescale.com>
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 493cdc6..344fbe2 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
 obj-$(CONFIG_LS1043A)  += ls1043.o
+obj-$(CONFIG_LS1046A)  += ls1046.o
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
new file mode 100644
index 000..bf4
--- /dev/null
+++ b/drivers/net/fm/ls1046.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define FSL_CHASSIS2_RCWSR13_EC1   0xe000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO  0x2000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM   0xa000
+#define FSL_CHASSIS2_RCWSR13_EC2   0x1c00 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII  0x
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO  0x0400
+#define FSL_CHASSIS2_RCWSR13_EC2_1588  0x0800
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM   0x1400
+
+u32 port_to_devdisr[] = {
+   [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+   [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+   [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+   [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+   [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+   [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+   [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+   [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+   [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+   [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+   [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+   [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 devdisr2 = in_be32(>devdisr2);
+
+   return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+   setbits_be32(>devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+   struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+   u32 rcwsr13 = in_be32(>rcwsr[13]);
+
+   if (is_device_disabled(port))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_XGMII;
+
+   if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
+   return PHY_INTERFACE_MODE_NONE;
+
+   if (port == FM1_DTSEC3)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+   FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   if (port == FM1_DTSEC4)
+   if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+   FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
+   return PHY_INTERFACE_MODE_RGMII;
+
+   /* handle SGMII, only MAC 2/5/6/9/10 available */
+   switch (port) {
+   case FM1_DTSEC2:
+   case FM1_DTSEC5:
+   case FM1_DTSEC6:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
+   return PHY_INTERFACE_MODE_SGMII;
+   break;
+   default:
+   break;
+   }
+
+   /* handle 2.5G SGMII, only MAC 5/9/10 available */
+   switch (port) {
+   case FM1_DTSEC5:
+   case FM1_DTSEC9:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
+port - FM1_DTSEC5))
+   return PHY_INTERFACE_MODE_SGMII_2500;
+   break;
+   default:
+   break;
+   }
+
+   /* handle QSGMII, only MAC 1/5/6/10 available */
+   switch (port) {
+   case FM1_DTSEC1:
+   case FM1_DTSEC5:
+   case FM1_DTSEC6:
+   case FM1_DTSEC10:
+   if (is_serdes_configured(QSGMII_FM1_A))
+   return PHY_INTERFACE_MODE_QSGMII;
+   break;
+   defau

[U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Add LS1046A SoC support

[Gong Qianyu]

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.


[PATCH 1/3] armv8: fsl-layerscape: Add A72 core detection
[PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support
[PATCH 3/3] armv8/ls1046a: Add Fman support


Regards,
Qianyu
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[U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

Data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..735dd67 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,11 @@ reset:
msr cpacr_el1, x0   /* Enable FP/SIMD */
 0:
 
+   /* Enalbe SMPEN bit */
+   mrs x0, S3_1_c15_c2_1   /* cpuactlr_el1 */
+   orr x0, x0, #0x40
+   msr S3_1_c15_c2_1, x0
+
/* Apply ARM core specific erratas */
bl  apply_core_errata
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

Set the flash to Uniform Sector Architecture in the non-volatile
register. After the power cycle, it's also Uniform Sector Architecture.

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 64d4e0f..366c362 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash 
*flash)
 static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
 {
u8 cmd[4];
-   u32 offset = 0x84; /* CR3V register offset */
+   u32 offset = 0x4; /* CR3NV register offset */
u8 cr3v;
int ret;
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] phylib: add support for aquantia AQR106/107 PHY

[Gong Qianyu]

From: Mingkai Hu <mingkai...@nxp.com>

Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>

diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index f90c2ae..ad12f6d 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -147,6 +147,32 @@ struct phy_driver aqr105_driver = {
.shutdown = _shutdown,
 };
 
+struct phy_driver aqr106_driver = {
+   .name = "Aquantia AQR106",
+   .uid = 0x3a1b4d0,
+   .mask = 0xfff0,
+   .features = PHY_10G_FEATURES,
+   .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+   MDIO_MMD_PHYXS | MDIO_MMD_AN |
+   MDIO_MMD_VEND1),
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
+struct phy_driver aqr107_driver = {
+   .name = "Aquantia AQR107",
+   .uid = 0x3a1b4e0,
+   .mask = 0xfff0,
+   .features = PHY_10G_FEATURES,
+   .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+   MDIO_MMD_PHYXS | MDIO_MMD_AN |
+   MDIO_MMD_VEND1),
+   .config = _config,
+   .startup = _startup,
+   .shutdown = _shutdown,
+};
+
 struct phy_driver aqr405_driver = {
.name = "Aquantia AQR405",
.uid = 0x3a1b4b2,
@@ -165,6 +191,8 @@ int phy_aquantia_init(void)
phy_register(_driver);
phy_register(_driver);
phy_register(_driver);
+   phy_register(_driver);
+   phy_register(_driver);
phy_register(_driver);
 
return 0;
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V2 3/3] armv8: ls1043aqds: print FPGA info early for QSPI boot

[Gong Qianyu]

Now I2C is initialized early enough to access FPGA so it supports to
show board info as early as other boot methods.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1043aqds.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 520b28c..ee8cb23 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -10,11 +10,7 @@
 #include "ls1043a_common.h"
 
 #define CONFIG_DISPLAY_CPUINFO
-#ifdef CONFIG_QSPI_BOOT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#else
 #define CONFIG_DISPLAY_BOARDINFO
-#endif
 
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE   0x8200
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V2 2/3] armv8: ls1043aqds: use configuarable clock

[Gong Qianyu]

Get the clocks from FPGA through IFC or I2C. So it needs I2C early init
if booting with IFC disabled.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 4 
 include/configs/ls1043aqds.h| 5 +++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index 9447c93..b7e9c21 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -230,6 +230,10 @@ int board_early_init_f(void)
 #ifdef CONFIG_LPUART
u8 uart;
 #endif
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+   i2c_early_init_f();
+#endif
fsl_lsch2_early_init_f();
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index a19eaee..520b28c 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -29,8 +29,8 @@ unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
 #endif
 
-#define CONFIG_SYS_CLK_FREQ1
-#define CONFIG_DDR_CLK_FREQ1
+#define CONFIG_SYS_CLK_FREQget_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
@@ -225,6 +225,7 @@ unsigned long get_board_ddr_clk(void);
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_SYS_NO_FLASH
 #endif
 
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch V2 1/3] armv8: ls1043aqds: fix to get boot device info from FPGA

[Gong Qianyu]

The LBMAP switches on the board will tell which boot device is used.
Only QSPI boot is supported if the boot device is IFCCard.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index 7e47ef0..9447c93 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -47,7 +47,7 @@ enum {
 int checkboard(void)
 {
char buf[64];
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
+#ifndef CONFIG_SD_BOOT
u8 sw;
 #endif
 
@@ -55,8 +55,6 @@ int checkboard(void)
 
 #ifdef CONFIG_SD_BOOT
puts("SD\n");
-#elif defined(CONFIG_QSPI_BOOT)
-   puts("QSPI\n");
 #else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -67,8 +65,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
-   else if (sw == 0x15)
-   printf("IFCCard\n");
+   else if (sw == 0xF)
+   printf("QSPI\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is avaliable in U-Boot

[Gong Qianyu]

IFC is considered as a required component in Layerscape platforms' Linux.
But if IFC is not enabled in U-Boot on some boards, accessing IFC memory
space would cause kernel call trace. So disable IFC node in such cases.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
V2:
 - Revised the title and message.
 - Used #ifndef CONFIG_FSL_IFC rather than #ifdef CONFIG_FSL_QSPI.

 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1e875c4..96dab56 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -98,4 +98,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_firmware(blob);
 #endif
+
+#ifndef CONFIG_FSL_IFC
+   do_fixup_by_compat(blob, "fsl,ifc",
+  "status", "disabled", 8 + 1, 1);
+#endif
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 3/3] ls102xa: spl: fix the macro name of MMC mode

[Gong Qianyu]

There is no MODE_FAT but MODE_FS. Fix it.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54..0289058 100644
--- a/arch/arm/cpu/armv7/ls102xa/spl.c
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -20,7 +20,7 @@ u32 spl_boot_mode(void)
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-   return MMCSD_MODE_FAT;
+   return MMCSD_MODE_FS;
 #else
return MMCSD_MODE_RAW;
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/3] fsl-layerscape: spl: fix the macro name of MMC mode

[Gong Qianyu]

There is no MODE_FAT but MODE_FS. Fix it.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 4c8a9a0..5883c00 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -29,7 +29,7 @@ u32 spl_boot_mode(void)
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-   return MMCSD_MODE_FAT;
+   return MMCSD_MODE_FS;
 #else
return MMCSD_MODE_RAW;
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/3] fsl-layerscape: spl: remove duplicate init_early_memctl_regs()

[Gong Qianyu]

init_early_memctl_regs() will also be called in board_early_init_f().
So remove the duplicate call in spl code.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index c1229c8..4c8a9a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -49,9 +49,6 @@ void board_init_f(ulong dummy)
 #ifdef CONFIG_LS2080A
arch_cpu_init();
 #endif
-#ifdef CONFIG_FSL_IFC
-   init_early_memctl_regs();
-#endif
board_early_init_f();
timer_init();
 #ifdef CONFIG_LS2080A
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1043a: remove redundant code in board files

[Gong Qianyu]

gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1043aqds/ls1043aqds.c | 4 
 board/freescale/ls1043ardb/ls1043ardb.c | 5 -
 2 files changed, 9 deletions(-)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index fba6b88..a59b8f4 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -325,10 +325,6 @@ int board_init(void)
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
 #endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
-   gd->env_addr = (ulong)_environment[0];
-#endif
return 0;
 }
 
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbf..f1d4c39 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -19,7 +19,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include "cpld.h"
 #ifdef CONFIG_U_QE
@@ -95,10 +94,6 @@ int board_init(void)
init_final_memctl_regs();
 #endif
 
-#ifdef CONFIG_ENV_IS_NOWHERE
-   gd->env_addr = (ulong)_environment[0];
-#endif
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1043ardb: fix types of variables

[Gong Qianyu]

Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1043ardb/ls1043ardb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index f1d4c39..2685dac 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -30,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
-   static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+   static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
 #ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
-   u32 cfg_rcw_src;
+   u16 cfg_rcw_src;
 #endif
-   u32 sd1refclk_sel;
+   u8 sd1refclk_sel;
 
printf("Board: LS1043ARDB, boot from ");
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'

[Gong Qianyu]

The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 board/freescale/ls1043ardb/cpld.c | 26 --
 board/freescale/ls1043ardb/cpld.h |  1 +
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls1043ardb/cpld.c 
b/board/freescale/ls1043ardb/cpld.c
index 78c2824..c645283 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
 /* Set the boot bank to the alternate bank */
 void cpld_set_altbank(void)
 {
+   u16 reg = CPLD_CFG_RCW_SRC_NOR;
u8 reg4 = CPLD_READ(soft_mux_on);
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
u8 reg7 = CPLD_READ(vbank);
 
-   CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
 
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
 /* Set the boot bank to the default bank */
 void cpld_set_defbank(void)
 {
-   CPLD_WRITE(global_rst, 1);
+   u16 reg = CPLD_CFG_RCW_SRC_NOR;
+   u8 reg4 = CPLD_READ(soft_mux_on);
+   u8 reg5 = (u8)(reg >> 1);
+   u8 reg6 = (u8)(reg & 1);
+
+   cpld_rev_bit();
+
+   CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+   CPLD_WRITE(cfg_rcw_src1, reg5);
+   CPLD_WRITE(cfg_rcw_src2, reg6);
+
+   CPLD_WRITE(vbank, 0);
+
+   CPLD_WRITE(system_rst, 1);
 }
 
 void cpld_set_nand(void)
diff --git a/board/freescale/ls1043ardb/cpld.h 
b/board/freescale/ls1043ardb/cpld.h
index bd59c0e..cb175b5 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL   0x40
 #define CPLD_BANK_SEL_MASK 0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
+#define CPLD_CFG_RCW_SRC_NOR   0x025
 #define CPLD_CFG_RCW_SRC_NAND  0x106
 #define CPLD_CFG_RCW_SRC_SD0x040
 #endif
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled

[Gong Qianyu]

IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS.
So this patch could fix 'sync abort' caused by autoboot that tries to
access IFC address.

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1043a_common.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e900c50..d4a181e 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -264,8 +264,13 @@
 
 #define CONFIG_BOOTARGS"console=ttyS0,115200 
root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load "\
+   "e f0 && bootm $kernel_load"
+#else
 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
"$kernel_size && bootm $kernel_load"
+#endif
 #define CONFIG_BOOTDELAY   10
 
 /* Monitor Command Prompt */
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2] armv8: ls1043a: load Fman ucode from SD/MMC under SD boot

[Gong Qianyu]

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1043a_common.h | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 2432531..e900c50 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -216,7 +216,15 @@
 /* Store Fman ucode at offeset 0x16(11 blocks). */
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR(11 * 
CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#elif defined(CONFIG_SD_BOOT)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image 
is
+ * about 1MB (2040 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR(512 * 0x820)
+#elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
 #define CONFIG_ENV_SPI_BUS 0
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH 1/2] armv8: ls1043a: load Fman ucode from NAND flash under NAND boot

[Gong Qianyu]

Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
---
 include/configs/ls1043a_common.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index fd243b1..2432531 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -212,7 +212,11 @@
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE   0x6
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifdef CONFIG_NAND_BOOT
+/* Store Fman ucode at offeset 0x16(11 blocks). */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR(11 * 
CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
 #define CONFIG_ENV_SPI_BUS 0
-- 
2.1.0.27.g96db324

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