[PATCH v2] armv8: layerscape: fix the function mismatch issue
From: Yuantian Tang Signed-off-by: Yuantian Tang --- v2: update copyright year arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d8803738f1..a40175cb3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2022 NXP * * Extracted from armv8/start.S */ @@ -353,7 +353,7 @@ ENTRY(fsl_ocram_clear_ecc_err) ldr x0, =DCSR_DCFG_MBEESR2 str w1, [x0] ret -ENDPROC(fsl_ocram_init) +ENDPROC(fsl_ocram_clear_ecc_err) #endif #ifdef CONFIG_FSL_LSCH3 -- 2.25.1
[PATCH] armv8: layerscape: fix the function mismatch issue
From: Yuantian Tang Signed-off-by: Yuantian Tang --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d8803738f1..4b5e2e1632 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -353,7 +353,7 @@ ENTRY(fsl_ocram_clear_ecc_err) ldr x0, =DCSR_DCFG_MBEESR2 str w1, [x0] ret -ENDPROC(fsl_ocram_init) +ENDPROC(fsl_ocram_clear_ecc_err) #endif #ifdef CONFIG_FSL_LSCH3 -- 2.25.1
RE: [EXT] [PATCH v2] ls1028a: use default scan_dev_for_boot
> -Original Message-
> From: Mian Yousaf Kaukab
> Sent: 2020年7月23日 21:41
> To: u-boot@lists.denx.de; Andy Tang
> Cc: Priyanka Jain ; Rajesh Bhagat
> ; harninder@nxp.com;
> sudhanshu.gu...@nxp.com; Poonam Aggrwal ;
> Mian Yousaf Kaukab
> Subject: [EXT] [PATCH v2] ls1028a: use default scan_dev_for_boot
>
> Caution: EXT Email
>
> scan_dev_for_efi is supposed to be called from scan_dev_for_boot.
> However this call is missing for ls1028ardb and ls1028aqds boards. As a result
> EFI boot doesn’t work. Fix this issue by removing custom definition of
> scan_dev_for_boot and use the default definition instead.
>
> Signed-off-by: Mian Yousaf Kaukab
> ---
> Change-log:
> v2: -Rename. was: ls1028a: fix EFI boot
>
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20200721143354.14382-1
> -ykaukab%40suse.de%2Fdata=02%7C01%7Candy.tang%40nxp.com%7
> C729286cd9264486fe7e208d82f0e3e21%7C686ea1d3bc2b4c6fa92cd99c5c3
> 01635%7C0%7C1%7C637311085499253728sdata=iS6R4NdV3LhAXttKf
> lgl29Su8TJqfFoBzTCnUl4mAQM%3Dreserved=0
> -Remove custom definition of scan_dev_for_boot
>
> include/configs/ls1028aqds.h | 7 --- include/configs/ls1028ardb.h | 7
> ---
> 2 files changed, 14 deletions(-)
>
> diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index
> 7bb740f48e36..8ab943cc640a 100644
> --- a/include/configs/ls1028aqds.h
> +++ b/include/configs/ls1028aqds.h
> @@ -129,13 +129,6 @@
> "run scan_dev_for_boot; " \
> "fi; " \
> "done\0" \
> - "scan_dev_for_boot=" \
> - "echo Scanning ${devtype} " \
> - "${devnum}:${distro_bootpart}...; " \
> - "for prefix in ${boot_prefixes}; do " \
> - "run scan_dev_for_scripts; " \
> - "done;" \
> - "\0" \
> "boot_a_script=" \
> "load ${devtype} ${devnum}:${distro_bootpart} " \
> "${scriptaddr} ${prefix}${script}; " \ diff --git
> a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index
> 07450113269c..3c9358ca4b7a 100644
> --- a/include/configs/ls1028ardb.h
> +++ b/include/configs/ls1028ardb.h
> @@ -112,13 +112,6 @@
> "run scan_dev_for_boot; "\
> "fi; " \
> "done\0" \
> - "scan_dev_for_boot=" \
> - "echo Scanning ${devtype} " \
> - "${devnum}:${distro_bootpart}...; "
> \
> - "for prefix in ${boot_prefixes}; do " \
> - "run scan_dev_for_scripts; " \
> - "done;" \
> - "\0" \
> "boot_a_script=" \
> "load ${devtype} ${devnum}:${distro_bootpart} " \
> "${scriptaddr} ${prefix}${script}; "\
> --
> 2.26.2
Reviewed-by: andy.t...@nxp.com
RE: [EXT] Re: [PATCH] ls1028a: fix EFI boot
> -Original Message- > From: Mian Yousaf Kaukab > Sent: 2020年7月23日 17:31 > To: Andy Tang > Cc: Poonam Aggrwal ; u-boot@lists.denx.de; > Rajesh Bhagat ; harninder@nxp.com; > sudhanshu.gu...@nxp.com; prabhakar.kushw...@nxp.com; Priyanka Jain > > Subject: [EXT] Re: [PATCH] ls1028a: fix EFI boot > > Caution: EXT Email > > On Thu, Jul 23, 2020 at 06:26:38AM +, Andy Tang wrote: > > Hi Yousaf, > Hi Andy, > > > > Could you please try removing entire environment variable > "scan_dev_for_boot" in the ls1028aqds/rdb header file? > > In this way, the default value for scan_dev_for_boot could be used and meet > your requirement. > Its actually better to remove the custom definition of scan_dev_for_boot. > However, the default definition will additionally call “run > scan_dev_for_extlinux”. > I can send a new patch if that's not an issue. Go ahead, that should not be an issue. BR, Andy > > > > BR, > > Andy > BR, > Yousaf
RE: [PATCH] ls1028a: fix EFI boot
Hi Yousaf,
Could you please try removing entire environment variable "scan_dev_for_boot"
in the ls1028aqds/rdb header file?
In this way, the default value for scan_dev_for_boot could be used and meet
your requirement.
BR,
Andy
> -Original Message-
> From: Poonam Aggrwal
> Sent: 2020年7月22日 18:01
> To: Mian Yousaf Kaukab ; u-boot@lists.denx.de; Rajesh
> Bhagat ; harninder@nxp.com;
> sudhanshu.gu...@nxp.com
> Cc: prabhakar.kushw...@nxp.com; Andy Tang ;
> Priyanka Jain
> Subject: RE: [PATCH] ls1028a: fix EFI boot
>
> Hello Yousaf
>
>
> > -Original Message-
> > From: U-Boot On Behalf Of Mian Yousaf
> > Kaukab
> > Sent: Tuesday, July 21, 2020 8:04 PM
> > To: u-boot@lists.denx.de; Rajesh Bhagat ;
> > harninder@nxp.com; sudhanshu.gu...@nxp.com
> > Cc: prabhakar.kushw...@nxp.com; Andy Tang ;
> > Priyanka Jain ; Mian Yousaf Kaukab
> >
> > Subject: [PATCH] ls1028a: fix EFI boot
> >
> > scan_dev_for_efi is supposed to be called from scan_dev_for_boot.
> > However this call is missing for ls1028ardb and ls1028aqds boards. As
> > a result EFI boot doesn’t work. Fix this issue by adding scan_dev_for_efi
> call.
> >
> Acked.
>
> Andy, can you please also take a look.
>
> Thanks .
>
> Regards
> Poonam
>
> > Signed-off-by: Mian Yousaf Kaukab
> > ---
> > include/configs/ls1028aqds.h | 1 +
> > include/configs/ls1028ardb.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/configs/ls1028aqds.h
> > b/include/configs/ls1028aqds.h index 7bb740f48e36..3d622002ebca
> 100644
> > --- a/include/configs/ls1028aqds.h
> > +++ b/include/configs/ls1028aqds.h
> > @@ -135,6 +135,7 @@
> > "for prefix in ${boot_prefixes}; do " \
> > "run scan_dev_for_scripts; " \
> > "done;" \
> > + SCAN_DEV_FOR_EFI \
> > "\0" \
> > "boot_a_script=" \
> > "load ${devtype} ${devnum}:${distro_bootpart} " \ diff --git
> > a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index
> > 07450113269c..0064c1dcc01a 100644
> > --- a/include/configs/ls1028ardb.h
> > +++ b/include/configs/ls1028ardb.h
> > @@ -118,6 +118,7 @@
> > "for prefix in ${boot_prefixes}; do " \
> > "run scan_dev_for_scripts; " \
> > "done;" \
> > + SCAN_DEV_FOR_EFI \
> > "\0" \
> > "boot_a_script=" \
> > "load ${devtype} ${devnum}:${distro_bootpart} " \
> > --
> > 2.26.2
[PATCH] armv8: ls1028ardb: add xspi parameter to qixis command
From: Yuantian Tang
Add xspi boot source to qixis command to let the soc boot from
flex-nor flash chip.
Signed-off-by: Yuantian Tang
---
board/freescale/common/qixis.c | 13 +
include/configs/ls1028ardb.h | 4 ++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index dd1ee90b3c..f4a8ad78c0 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -322,6 +322,19 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
+#endif
+ } else if (strcmp(argv[1], "xspi") == 0) {
+#ifdef QIXIS_LBMAP_XSPI
+ QIXIS_WRITE(rst_ctl, 0x30);
+ QIXIS_WRITE(rcfg_ctl, 0);
+ set_lbmap(QIXIS_LBMAP_XSPI);
+ set_rcw_src(QIXIS_RCW_SRC_XSPI);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+ QIXIS_RCFG_CTL_RECONFIG_START);
+#else
+ printf("Not implemented\n");
#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index 0f289cb078..4d65d5d38b 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -38,10 +38,10 @@
#define QIXIS_LBMAP_ALTBANK0x00
#define QIXIS_LBMAP_SD 0x00
#define QIXIS_LBMAP_EMMC 0x00
-#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_LBMAP_XSPI 0x00
#define QIXIS_RCW_SRC_SD 0xf8
#define QIXIS_RCW_SRC_EMMC 0xf9
-#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RCW_SRC_XSPI 0xff
#define QIXIS_RST_CTL_RESET0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10
#define QIXIS_RCFG_CTL_RECONFIG_START 0x11
--
2.17.1
RE: [PATCH] armv8: ls1046ardb: add new 16GB udimm memory support
+Mazyar,
Hi Mazyar,
Could you please address Priyanka's concern?
BR,
Andy
> -Original Message-
> From: Priyanka Jain (OSS)
> Sent: 2020年4月15日 18:07
> To: Andy Tang
> Cc: Mingkai Hu ; Rajesh Bhagat
> ; u-boot@lists.denx.de; Andy Tang
>
> Subject: RE: [PATCH] armv8: ls1046ardb: add new 16GB udimm memory
> support
>
> >-Original Message-
> >From: U-Boot On Behalf Of
> >andy.t...@nxp.com
> >Sent: Friday, April 3, 2020 12:30 PM
> >To: Priyanka Jain
> >Cc: Mingkai Hu ; Rajesh Bhagat
> >; u-boot@lists.denx.de; Andy Tang
> >
> >Subject: [PATCH] armv8: ls1046ardb: add new 16GB udimm memory support
> >
> >From: Yuantian Tang
> >
> >Add this udimm memory support on ls1046ardb board.
> What is this?
> I see in code, you are adding DIMM specific parameter to support new
> frequency.
> Is this code changes because you are adding a different DIMM or adding
> support for new frequency?
> If new DIMM, What if someone tried to use the frequency "2133" with the
> original dim on board.
>
> Please provide more details in description.
>
> Thanks
> Priyanka
> >
> >Signed-off-by: Yuantian Tang
> >---
> > board/freescale/ls1046ardb/ddr.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> >diff --git a/board/freescale/ls1046ardb/ddr.h
> >b/board/freescale/ls1046ardb/ddr.h
> >index 3b4d44d465..d401daa776 100644
> >--- a/board/freescale/ls1046ardb/ddr.h
> >+++ b/board/freescale/ls1046ardb/ddr.h
> >@@ -32,6 +32,7 @@ static const struct board_specific_parameters
> >udimm0[] = {
> > {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
> > {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
> > {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
> >+{2, 2133, 0, 4, 7, 0x08090A0E, 0x1011120C,},
> > {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
> > {}
> > };
> >--
> >2.17.1
[PATCH] armv8: ls1046ardb: add new 16GB udimm memory support
From: Yuantian Tang
Add this udimm memory support on ls1046ardb board.
Signed-off-by: Yuantian Tang
---
board/freescale/ls1046ardb/ddr.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
index 3b4d44d465..d401daa776 100644
--- a/board/freescale/ls1046ardb/ddr.h
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -32,6 +32,7 @@ static const struct board_specific_parameters udimm0[] = {
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2133, 0, 4, 7, 0x08090A0E, 0x1011120C,},
{2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
{}
};
--
2.17.1
[PATCH 2/2] armv8: ls1028a: clean up the environment variables
From: Yuantian Tang
Move the environment variables from command head file to
ls1028ardb specific head file so that they will mess up
with ls1028aqds board.
Also updated some variable slightly.
There is no function change by this patch.
Signed-off-by: Yuantian Tang
---
include/configs/ls1028a_common.h | 87 ---
include/configs/ls1028ardb.h | 89
2 files changed, 89 insertions(+), 87 deletions(-)
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 05b8cf0..fda98e6 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -73,93 +73,6 @@
func(USB, usb, 0)
#include
-/* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "board=ls1028ardb\0"\
- "hwconfig=fsl_ddr:bank_intlv=auto\0"\
- "ramdisk_addr=0x80\0" \
- "ramdisk_size=0x200\0" \
- "fdt_high=0x\0" \
- "initrd_high=0x\0" \
- "fdt_addr=0x00f0\0" \
- "kernel_addr=0x0100\0" \
- "scriptaddr=0x8000\0" \
- "scripthdraddr=0x8008\0"\
- "fdtheader_addr_r=0x8010\0" \
- "kernelheader_addr_r=0x8020\0" \
- "load_addr=0xa000\0"\
- "kernel_addr_r=0x8100\0"\
- "fdt_addr_r=0x9000\0" \
- "ramdisk_addr_r=0xa000\0" \
- "kernel_start=0x100\0" \
- "kernelheader_start=0x80\0" \
- "kernel_load=0xa000\0" \
- "kernel_size=0x280\0" \
- "kernelheader_size=0x4\0" \
- "kernel_addr_sd=0x8000\0" \
- "kernel_size_sd=0x14000\0" \
- "kernelhdr_addr_sd=0x4000\0"\
- "kernelhdr_size_sd=0x10\0" \
- "console=ttyS0,115200\0"\
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"\
- BOOTENV \
- "boot_scripts=ls1028ardb_boot.scr\0"\
- "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \
- "scan_dev_for_boot_part=" \
- "part list ${devtype} ${devnum} devplist; " \
- "env exists devplist || setenv devplist 1; " \
- "for distro_bootpart in ${devplist}; do " \
- "if fstype ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "bootfstype; then " \
- "run scan_dev_for_boot; "\
- "fi; " \
- "done\0" \
- "scan_dev_for_boot=" \
- "echo Scanning ${devtype} " \
- "${devnum}:${distro_bootpart}...; " \
- "for prefix in ${boot_prefixes}; do " \
- "run scan_dev_for_scripts; " \
- "done;" \
- "\0" \
- "boot_a_script=" \
- "load ${devtype} ${devnum}:${distro_bootpart} " \
- "${scriptaddr} ${prefix}${script}; "\
- "env exists secureboot && load ${devtype} " \
- "${devnum}:${distro_bootpart} " \
- "${scripthdraddr} ${prefix}${boot_script_hdr} " \
- "&& esbc_validate ${scripthdraddr};"\
- "source ${scriptaddr}\0" \
- "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
- "sf probe 0:0 && sf read $load_addr " \
- "$kernel_start $kernel_size ; env exists secureboot &&" \
- "sf read $kernelheader_addr_r $kernelheader_start " \
- "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
- " bootm $load_addr#$board\0" \
- "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
- "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
- "&& hdp load $load_addr 0x2000\0" \
- "sd_bootcmd=echo Trying load from SD ...;" \
- "mmcinfo; mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
- "env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd "\
- " && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0" \
- "sd_hdploadcmd=echo Trying load HDP
[PATCH 1/2 v2] armv8: ls1028aqds: add some environments
From: Yuantian Tang
Add sd and emmc bootcmd environments to facilitate
the boot process.
Signed-off-by: Yuantian Tang
---
v2:
- updated some variable slightly.
include/configs/ls1028aqds.h | 39 ---
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index b3c1242..5843274 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -108,6 +108,7 @@
"load_addr=0xa000\0" \
"kernel_addr_r=0x8100\0" \
"fdt_addr_r=0x9000\0" \
+ "fdt2_addr_r=0x9001\0" \
"ramdisk_addr_r=0xa000\0" \
"kernel_start=0x100\0" \
"kernelheader_start=0x80\0" \
@@ -148,19 +149,35 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
- "sd_bootcmd=echo Trying load from SD ..;" \
- "mmcinfo; mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
+ "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$board\0" \
+ "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
+ "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+ "&& hdp load $load_addr 0x2000\0" \
+ "sd_bootcmd=echo Trying load from SD ...;" \
+ "mmc dev 0; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd " \
- " && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0" \
- "emmc_bootcmd=echo Trying load from EMMC ..;" \
- "mmcinfo; mmc dev 1; mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0" \
+ "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+ "mmc dev 0;mmcinfo; mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0" \
+ "emmc_bootcmd=echo Trying load from EMMC ..;" \
+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
+ "bootm $load_addr#$board\0" \
+ "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
+ "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0"
+
#endif
#endif /* __LS1028A_QDS_H */
--
2.9.5
[PATCH] armv8: ls1028aqds: add some environments
From: Yuantian Tang
Add sd and emmc bootcmd environments to facilitate
the boot process.
Signed-off-by: Yuantian Tang
---
include/configs/ls1028aqds.h | 38 +---
1 file changed, 27 insertions(+), 11 deletions(-)
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index b0e9441a48..4cffd69446 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -142,19 +142,35 @@
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
- "sd_bootcmd=echo Trying load from SD ..;" \
- "mmcinfo; mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
+ "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$board\0" \
+ "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \
+ "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
+ "&& hdp load $load_addr 0x2000\0" \
+ "sd_bootcmd=echo Trying load from SD ...;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd " \
- " && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0" \
- "emmc_bootcmd=echo Trying load from EMMC ..;" \
- "mmcinfo; mmc dev 1; mmc read $load_addr " \
- "$kernel_addr_sd $kernel_size_sd && " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$board\0" \
+ "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
+ "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0" \
+ "emmc_bootcmd=echo Trying load from EMMC ..;" \
+ "mmcinfo; mmc dev 1; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
- "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
+ "bootm $load_addr#$board\0" \
+ "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \
+ "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
+ "&& hdp load $load_addr 0x2000\0"
+
#endif
#endif /* __LS1028A_QDS_H */
--
2.17.1
[PATCH 3/4] armv8: ls1028aqds: add lpuart dts support
From: Yuantian Tang
Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that
it can be used as common device tree for lpuart and duart.
Add lpuart device tree and duart device tree respectively
for qds which are used with duart and lpuart console.
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang
---
arch/arm/dts/Makefile | 3 ++-
arch/arm/dts/fsl-ls1028a-qds-duart.dts| 15 +++
arch/arm/dts/fsl-ls1028a-qds-lpuart.dts | 15 +++
.../{fsl-ls1028a-qds.dts => fsl-ls1028a-qds.dtsi} | 4
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +-
configs/ls1028aqds_tfa_defconfig | 2 +-
6 files changed, 38 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-duart.dts
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
rename arch/arm/dts/{fsl-ls1028a-qds.dts => fsl-ls1028a-qds.dtsi} (98%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9303beb2f5..f9c8c30303 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -370,7 +370,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
fsl-ls1028a-rdb.dtb \
- fsl-ls1028a-qds.dtb \
+ fsl-ls1028a-qds-duart.dtb \
+ fsl-ls1028a-qds-lpuart.dtb \
fsl-lx2160a-rdb.dtb \
fsl-lx2160a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts
b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
new file mode 100644
index 00..83264e0f54
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
new file mode 100644
index 00..063857b2f2
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for Freescale Layerscape-1028AQDS family SoC.
+ *
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+#include "fsl-ls1028a-qds.dtsi"
+
+/ {
+ chosen {
+ stdout-path =
+ };
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts
b/arch/arm/dts/fsl-ls1028a-qds.dtsi
similarity index 98%
rename from arch/arm/dts/fsl-ls1028a-qds.dts
rename to arch/arm/dts/fsl-ls1028a-qds.dtsi
index 3fd37beedf..649c5ee8e3 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dts
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -149,6 +149,10 @@
status = "okay";
};
+ {
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index d0051bb682..6bc732f3e5 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -28,7 +28,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 7085be77fe..e8f1f57920 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -30,7 +30,7 @@ CONFIG_CMD_WDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_ADDR=0x2050
--
2.17.1
[PATCH 2/4] arm: dts: ls1028a: add lpuart nodes
From: Yuantian Tang
Add lpuart nodes to enable lpuart feature
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang
---
arch/arm/dts/fsl-ls1028a.dtsi | 60 +++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 5365bfb1a8..9911690e5c 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -240,6 +240,66 @@
status = "disabled";
};
+ lpuart0: serial@226 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x226 0x0 0x1000>;
+ interrupts = <0 232 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart1: serial@227 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x227 0x0 0x1000>;
+ interrupts = <0 233 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart2: serial@228 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x228 0x0 0x1000>;
+ interrupts = <0 234 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart3: serial@229 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x229 0x0 0x1000>;
+ interrupts = <0 235 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart4: serial@22a {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x22a 0x0 0x1000>;
+ interrupts = <0 236 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart5: serial@22b {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x22b 0x0 0x1000>;
+ interrupts = <0 237 0x4>;
+ clocks = <>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
usb1: usb3@310 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x310 0x0 0x1>;
--
2.17.1
[PATCH 1/4] board: freescale: ls1028a: mux changes for lpuart
From: Yuantian Tang
mux changes in board file to enable lpuart1 and macro
define for lpuart1 used for mux changes in board configuation
register 13
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang
---
board/freescale/ls1028a/ls1028a.c | 32 +++
include/configs/ls1028aqds.h | 7 +++
2 files changed, 39 insertions(+)
diff --git a/board/freescale/ls1028a/ls1028a.c
b/board/freescale/ls1028a/ls1028a.c
index aa93534ac6..3659e7daf3 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
int config_board_mux(void)
{
+#ifndef CONFIG_LPUART
#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
u8 reg;
@@ -55,9 +56,18 @@ int config_board_mux(void)
reg &= ~(0xc0);
QIXIS_WRITE(brdcfg[15], reg);
#endif
+#endif
+
return 0;
}
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+ return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
+#endif
+
int board_init(void)
{
#ifdef CONFIG_ENV_IS_NOWHERE
@@ -120,11 +130,33 @@ int misc_init_r(void)
int board_early_init_f(void)
{
+#ifdef CONFIG_LPUART
+ u8 uart;
+#endif
+
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
fsl_lsch3_early_init_f();
+
+#ifdef CONFIG_LPUART
+ /*
+* Field| Function
+* --
+* 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
+* I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
+* --
+* 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
+* I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
+*/
+ /* use lpuart0 as system console */
+ uart = QIXIS_READ(brdcfg[13]);
+ uart &= ~CFG_LPUART_MUX_MASK;
+ uart |= CFG_LPUART_EN;
+ QIXIS_WRITE(brdcfg[13], uart);
+#endif
+
return 0;
}
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 982df07bb0..b3c12420eb 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -66,6 +66,13 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#define CFG_LPUART_MUX_MASK0xf0
+#define CFG_LPUART_EN 0xf0
+#endif
+
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
--
2.17.1
[PATCH 4/4] configs: ls1028aqds: add lpuart config
From: Yuantian Tang Add lpuart config to enable lpuart feature. Signed-off-by: Vabhav Sharma Signed-off-by: Yuantian Tang . --- configs/ls1028aqds_tfa_lpuart_defconfig | 88 + 1 file changed, 88 insertions(+) create mode 100644 configs/ls1028aqds_tfa_lpuart_defconfig diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig new file mode 100644 index 00..417f29217a --- /dev/null +++ b/configs/ls1028aqds_tfa_lpuart_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028AQDS=y +CONFIG_TFABOOT=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x4 +CONFIG_ENV_OFFSET=0x50 +CONFIG_DM_GPIO=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x200 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_SYS_EXTRA_OPTIONS="LPUART" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-lpuart" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x2050 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_FSL_ENETC=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF2127=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- 2.17.1
[PATCH] armv8: ls1028a: add dhcp boot target device
From: Yuantian Tang Add DHCP boot target device to enable command bootcmd_dhcp. Signed-off-by: Yuantian Tang --- include/configs/ls1028a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 98320e22e9..94ba08acb4 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -70,7 +70,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ - func(USB, usb, 0) + func(USB, usb, 0) \ + func(DHCP, dhcp, na) #include /* Initial environment variables */ -- 2.17.1
[PATCH] board: ls1028ardb: add BOARD_LATE_INIT config
From: Yuantian Tang Select BOARD_LATE_INIT config so that many board works can be done in late init stage. Signed-off-by: Yuantian Tang --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d9f7fcce7..d871c13aab 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1376,6 +1376,7 @@ config TARGET_LS1028ARDB select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance -- 2.17.1
Re: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities support
Hi Priyanka,
Please see my reply inline.
> -Original Message-
> From: Priyanka Jain
> Sent: 2019年9月25日 13:43
> To: Andy Tang
> Cc: u-boot@lists.denx.de
> Subject: RE: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities
> support
>
>
>
> >-Original Message-
> >From: Andy Tang
> >Sent: Wednesday, September 25, 2019 11:06 AM
> >To: Priyanka Jain
> >Cc: u-boot@lists.denx.de
> >Subject: RE: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities
> >support
> >
> >Hi Priyanka,
> >
> >Please see my reply inline.
> >
> >> -Original Message-----
> >> From: Priyanka Jain
> >> Sent: 2019年9月25日 13:05
> >> To: Andy Tang ; Priyanka Jain
> >>
> >> Cc: Andy Tang ; u-boot@lists.denx.de
> >> Subject: RE: [U-Boot] [PATCH v2] armv8: ls1028a: add more
> >> personalities support
> >>
> >>
> >>
> >> >-Original Message-
> >> >From: U-Boot On Behalf Of Yuantian
> >> >Tang
> >> >Sent: Wednesday, September 18, 2019 2:21 PM
> >> >To: Prabhakar Kushwaha
> >> >Cc: Andy Tang ; u-boot@lists.denx.de
> >> >Subject: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities
> >> >support
> >> >
> >> Please update subject to be more specific about Soc personalities.
> >> Something like
> >> armv8: ls1028a: add LS1027A, LS1018A, LS1017A support you can skip
> >> this line in description
> >Any reason it must be put in patch subject?
> It’s a suggestion as subject are supposed to specific summary about the
> content of patch "Add more personalities" is a bit vague --priyankajain
We can put the "more personalities" in subject or in description.
Either way is ok. I prefer to put it in description. Subject should be as
concise as possible.
Thanks for your suggestion.
BR,
Andy
> >
> >BR,
> >Andy
> >>
> >> --priyankajain
> >> >Add LS1027A, LS1018A and LS1017A personalities support to LS1028A
> >> >processor soc family.
> >> >
> >> >LS1028A processor is the prime personality of LS1028A soc family.
> >> >LS1027A processor is a lower funtionality version of QorIQ LS1028A
> >> >which does not support the multimedia subsystems, such as LCD
> >> >controller, GPU, and eDP PHY.
> >> >The QorIQ LS1018A and LS1017A are low power versions of the QorIQ
> >> >LS1028A and LS1027A processors, respectively which integrate single
> >> >64-bit Arm A72 core.
> >> >
> >> >Signed-off-by: Tang Yuantian
> >> >---
> >> >v2:
> >> > - refine description
> >> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 +++
> >> > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
> >> > 2 files changed, 6 insertions(+)
> >> >
> >> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> >index 3e2a24fe80..dee96afe2d 100644
> >> >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >> >@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = {
> >> > CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
> >> > CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
> >> > CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
> >> >+ CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
> >> >+ CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
> >> >+ CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
> >> > CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
> >> > CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
> >> > CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), diff --git
> >> >a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >> >b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >> >
> >> >--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >> >+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >> >@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
> >> > /* LS1043A/LS1023A 23x23 package silicon has different value of
> >> >VAR_PER
> >> */
> >> > #define SVR_LS1043A_P23 0x879202
> >> > #define SVR_LS1023A_P23 0x87920A
> >> >+#define SVR_LS1017A 0x870B24
> >> >+#define SVR_LS1018A 0x870B20
> >> >+#define SVR_LS1027A 0x870B04
> >> > #define SVR_LS1028A 0x870B00
> >> > #define SVR_LS1046A 0x870700
> >> > #define SVR_LS1026A 0x870708
> >> >--
> >> >2.17.1
> >> >
> >> >___
> >> >U-Boot mailing list
> >> >U-Boot@lists.denx.de
> >> >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> >> >s
> >> >ts
> >> >.de
> >> >nx.de%2Flistinfo%2Fu-
> >> >bootdata=02%7C01%7Cpriyanka.jain%40nxp.com%7Cad5af7711f
> a64
> >> 03
> >>
> >>9450208d73c16cc16%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %
> >> 7C
> >> >637043940922465590sdata=dtSR0EQhGhJYBzhKAOWWGCMRbxY
> ax
> >> %2F
> >> >uuJmKY%2FKAhQBY%3Dreserved=0
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Re: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities support
Hi Priyanka,
Please see my reply inline.
> -Original Message-
> From: Priyanka Jain
> Sent: 2019年9月25日 13:05
> To: Andy Tang ; Priyanka Jain
> Cc: Andy Tang ; u-boot@lists.denx.de
> Subject: RE: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities
> support
>
>
>
> >-Original Message-
> >From: U-Boot On Behalf Of Yuantian Tang
> >Sent: Wednesday, September 18, 2019 2:21 PM
> >To: Prabhakar Kushwaha
> >Cc: Andy Tang ; u-boot@lists.denx.de
> >Subject: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities
> >support
> >
> Please update subject to be more specific about Soc personalities.
> Something like
> armv8: ls1028a: add LS1027A, LS1018A, LS1017A support you can skip this
> line in description
Any reason it must be put in patch subject?
BR,
Andy
>
> --priyankajain
> >Add LS1027A, LS1018A and LS1017A personalities support to LS1028A
> >processor soc family.
> >
> >LS1028A processor is the prime personality of LS1028A soc family.
> >LS1027A processor is a lower funtionality version of QorIQ LS1028A
> >which does not support the multimedia subsystems, such as LCD
> >controller, GPU, and eDP PHY.
> >The QorIQ LS1018A and LS1017A are low power versions of the QorIQ
> >LS1028A and LS1027A processors, respectively which integrate single
> >64-bit Arm A72 core.
> >
> >Signed-off-by: Tang Yuantian
> >---
> >v2:
> > - refine description
> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 +++
> > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
> > 2 files changed, 6 insertions(+)
> >
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >index 3e2a24fe80..dee96afe2d 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = {
> > CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
> > CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
> > CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
> >+CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
> >+CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
> >+CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
> > CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
> > CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
> > CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
> >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >
> >--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void);
> > /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER
> */
> > #define SVR_LS1043A_P23 0x879202
> > #define SVR_LS1023A_P23 0x87920A
> >+#define SVR_LS1017A 0x870B24
> >+#define SVR_LS1018A 0x870B20
> >+#define SVR_LS1027A 0x870B04
> > #define SVR_LS1028A 0x870B00
> > #define SVR_LS1046A 0x870700
> > #define SVR_LS1026A 0x870708
> >--
> >2.17.1
> >
> >___
> >U-Boot mailing list
> >U-Boot@lists.denx.de
> >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists
> >.de
> >nx.de%2Flistinfo%2Fu-
> >bootdata=02%7C01%7Cpriyanka.jain%40nxp.com%7Cad5af7711fa64
> 03
> >9450208d73c16cc16%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%
> 7C
> >637043940922465590sdata=dtSR0EQhGhJYBzhKAOWWGCMRbxYax
> %2F
> >uuJmKY%2FKAhQBY%3Dreserved=0
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Re: [U-Boot] [PATCH] armv8: ls1028a: add more personalities support
Hi Priyanka, Adding same information in both subject and description is not a good idea. I will add your suggested information in description. Thanks, Andy > -Original Message- > From: Priyanka Jain > Sent: 2019年9月17日 18:05 > To: Andy Tang ; Prabhakar Kushwaha > ; Priyanka Jain > Cc: Andy Tang ; u-boot@lists.denx.de > Subject: RE: [U-Boot] [PATCH] armv8: ls1028a: add more personalities > support > > > > >-Original Message- > >From: U-Boot On Behalf Of Yuantian Tang > >Sent: Tuesday, September 17, 2019 8:21 AM > >To: Prabhakar Kushwaha > >Cc: Andy Tang ; u-boot@lists.denx.de > >Subject: [U-Boot] [PATCH] armv8: ls1028a: add more personalities > >support > Be more specific about which personalities in subject. May be something like > armv8: ls1028a: add ls1018a, ls1027a, ls1017a support > > > > >Add three more personalities support to LS1028A processor soc family. > Same as above > > > >LS1028A processor is the prime personality of LS1028A soc family. > >LS1027A processor is a lower funtionality version of QorIQ LS1028A > >which does not support the multimedia subsystems, such as LCD > >controller, GPU, and eDP PHY. > >The QorIQ LS1018A and LS1017A are low power versions of the QorIQ > >LS1028A and LS1027A processors, respectively which integrate single > >64-bit Arm A72 core. > > > >Signed-off-by: Tang Yuantian > >--- > > priyankajain ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] armv8: ls1028ardb: Add sd and emmc related environments
Hi Prabhakar,
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2019年5月23日 11:39
> To: Andy Tang
> Cc: u-boot@lists.denx.de; Andy Tang
> Subject: RE: [PATCH v2] armv8: ls1028ardb: Add sd and emmc related
> environments
>
>
> > -Original Message-
> > From: Yuantian Tang
> > Sent: Thursday, May 23, 2019 7:46 AM
> > To: Prabhakar Kushwaha
> > Cc: u-boot@lists.denx.de; Andy Tang
> > Subject: [PATCH v2] armv8: ls1028ardb: Add sd and emmc related
> environments
> >
> > Add SD, EMMC and xspi environments to faciliate the boot.
> >
> > Signed-off-by: Yuantian Tang
> > ---
> > v2:
> > - rebase to latest code
> > include/configs/ls1028a_common.h | 24 +---
> > 1 file changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/include/configs/ls1028a_common.h
> > b/include/configs/ls1028a_common.h
> > index 0db86396e9..9531548184 100644
> > --- a/include/configs/ls1028a_common.h
> > +++ b/include/configs/ls1028a_common.h
> > @@ -127,25 +127,43 @@
> > "${scripthdraddr} ${prefix}${boot_script_hdr} " \
> > "&& esbc_validate ${scripthdraddr};"\
> > "source ${scriptaddr}\0" \
> > - "sd_bootcmd=echo Trying load from SD ..;" \
> > + "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \
> > + "sf probe 0:0 && sf read $load_addr " \
> > + "$kernel_start $kernel_size ; env exists secureboot &&" \
> > + "sf read $kernelheader_addr_r $kernelheader_start " \
> > + "$kernelheader_size && esbc_validate ${kernelheader_addr_r};
> > "\
> > + " bootm $load_addr#$board\0" \
> > + "sd_bootcmd=echo Trying load from SD ...;" \
> > "mmcinfo; mmc read $load_addr " \
> > "$kernel_addr_sd $kernel_size_sd && " \
> > "env exists secureboot && mmc read $kernelheader_addr_r " \
> > "$kernelhdr_addr_sd $kernelhdr_size_sd "\
> > " && esbc_validate ${kernelheader_addr_r};" \
> > "bootm $load_addr#$board\0" \
> > + "xspi_hdploadcmd=echo Trying load HDP firmware from
> > FlexSPI...;" \
> > + "sf probe 0:0 && sf read $load_addr 0x94 0x3 " \
> > + "&& hdp load $load_addr 0x2000\0" \
> > + "sd_hdploadcmd=echo Trying load HDP firmware from SD..;"\
> > + "mmcinfo;mmc read $load_addr 0x4a00 0x200 " \
> > + "&& hdp load $load_addr 0x2000\0" \
>
> Hdp support is not part of upstream code -base
>
> So can we remove hdp reference from this patch
Yeah, sure. I have not noticed that.
Thanks,
Andy
>
> --pk
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Re: [U-Boot] [PATCH] armv8: ls1028ardb: Add sd and emmc related environments
No problem. Thanks Prabhakar, BR, Andy > -Original Message- > From: Prabhakar Kushwaha > Sent: 2019年5月23日 9:11 > To: Andy Tang ; Sudhanshu Gupta > ; Harninder Rai ; > Rajesh Bhagat > Cc: u-boot@lists.denx.de; Andy Tang > Subject: RE: [PATCH] armv8: ls1028ardb: Add sd and emmc related > environments > > > > -Original Message- > > From: Prabhakar Kushwaha > > Sent: Wednesday, May 22, 2019 6:07 PM > > To: Yuantian Tang ; Sudhanshu Gupta > > ; Harninder Rai ; > > Rajesh Bhagat > > Cc: u-boot@lists.denx.de; Andy Tang > > Subject: RE: [PATCH] armv8: ls1028ardb: Add sd and emmc related > > environments > > > > > > > -Original Message- > > > From: Yuantian Tang > > > Sent: Tuesday, May 14, 2019 2:24 PM > > > To: Prabhakar Kushwaha ; Sudhanshu > Gupta > > > ; Harninder Rai ; > > > Rajesh Bhagat > > > Cc: u-boot@lists.denx.de; Andy Tang > > > Subject: [PATCH] armv8: ls1028ardb: Add sd and emmc related > > > environments > > > > > > Add SD and EMMC environments to faciliate the boot. > > > > > > Signed-off-by: Yuantian Tang > > > --- > > > > Please rebase after my pull request getting accepted > > > > My pull request accepted. Please rebase it on top of the tree. > > I am marking this patch as "change requested" > > --pk ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXT] Re: [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A SoC support
Hi Prabhakar, Please see my reply inline. > -Original Message- > From: Prabhakar Kushwaha > Sent: 2019年5月21日 16:23 > To: Bin Meng ; Andy Tang > Cc: Simon Glass ; Tom Rini ; > Sudhanshu Gupta ; U-Boot Mailing List > ; Ran Wang ; Bhaskar > Upadhaya > Subject: RE: [EXT] Re: [U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP > LS1028A SoC support > > > > > For example, the "config ARCH_LS1028A" selects the following I2C > > > > components: > > > > > > > > + select SYS_I2C_MXC > > > > + select SYS_I2C_MXC_I2C1 > > > > + select SYS_I2C_MXC_I2C2 > > > > + select SYS_I2C_MXC_I2C3 > > > > + select SYS_I2C_MXC_I2C4 > > > > + select SYS_I2C_MXC_I2C5 > > > > + select SYS_I2C_MXC_I2C6 > > > > + select SYS_I2C_MXC_I2C7 > > > > + select SYS_I2C_MXC_I2C8 > > > > > > > > These I2C# macros look to me this is not DM based. For DM such > > > > stuff is determined from the DT automatically. > > > Agree. Our I2C IP owner is working on it and will change all I2C > > > driver to DM > > based. > > > > Great. > > Andy: Please make sure our I2C IP owner do change all NXP supported SoCs > including LS1028A. Patch for DM-based i2c driver is ready. Will send out this week. Then there are follow up patches to convert all the platforms. Thanks, Andy > > > > > > > > > > > > > > For ls1028a_serdes.c, we probably need create serdes uclass driver for > it. > > > We don't have serdes dts node in both uboot and kernel. So I think > > > we can > > leave it as it is. > > > > I see. Then let's keep it as it is. > > > > > > > > > > > > > For arch/arm/cpu/armv8/fsl-layerscape/cpu.c, can we create a CPU > > > > driver for it? I see lots of CONFIG_XXX_BASE and CONFIG_XXX_SIZE > > > > in this file that come from > > > > arch/arm/include/asm/arch-fsl-layerscape/cpu.h? Can't we get such > > > > in > > DT? > > > Agree. But this affects all our platforms and need big efforts. Many > > components are involved in it. > > > We will convert it step by step. > > > > > > > Sounds you already have a plan, which is good! > > > > I will prefer to merge this patch-set for now. > > I will keep CPU DM model in my todo. It will require change in many NXP > supported devices. > > --pk > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXT] Re: [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A SoC support
Hi Bin, Thanks for your review. Please see my comments below. > -Original Message- > From: Bin Meng > Sent: 2019年5月17日 14:32 > To: Andy Tang > Cc: Simon Glass ; Tom Rini ; > Prabhakar Kushwaha ; Sudhanshu Gupta > ; U-Boot Mailing List ; > Ran Wang ; Bhaskar Upadhaya > > Subject: Re: [EXT] Re: [U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP > LS1028A SoC support > > Caution: EXT Email > > Hi Andy, > > On Fri, May 17, 2019 at 11:23 AM Andy Tang wrote: > > > > Hi Bin, > > > > > -Original Message- > > > From: Bin Meng > > > Sent: 2019年5月16日 20:10 > > > To: Andy Tang ; Simon Glass > ; > > > Tom Rini > > > Cc: Prabhakar Kushwaha ; Sudhanshu > Gupta > > > ; U-Boot Mailing List > > > ; Ran Wang ; Bhaskar > > > Upadhaya > > > Subject: [EXT] Re: [U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP > > > LS1028A SoC support > > > > > > > > > Hi, > > > > > > On Wed, Apr 10, 2019 at 4:50 PM Yuantian Tang > > > wrote: > > > > > > > > Ls1028a Soc is based on Layerscape Chassis Generation 3.2 > > > > architecture with features: > > > > 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN > > > > ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C > > > > controllers, > > > > 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. > > > > > > > > Signed-off-by: Sudhanshu Gupta > > > > Signed-off-by: Rai Harninder > > > > Signed-off-by: Rajesh Bhagat > > > > Signed-off-by: Bhaskar Upadhaya > > > > Signed-off-by: Tang Yuantian > > > > --- > > > > v3: > > > > -- fix some issues > > > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- > > > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > > > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 + > > > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 > > > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 73 ++ > > > > arch/arm/dts/fsl-ls1028a.dtsi | 280 > > > + > > > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 + > > > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + > > > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + > > > > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- > > > > 10 files changed, 521 insertions(+), 2 deletions(-) create mode > > > > 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > > > create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi > > > > > > > > > > I really would like to see complete DM driver support on this new > platform. > > > Please consider converting appropriate codes to driver model. If > > > there is no proper uclass model, please propose one and discuss it > > > on the list. I see the existing NXP PowerPC support is stuck in such > > > a situation that lots of codes are still non-DM and we are getting > > > close to the DM deadline. I don't want to see such happens again in the > NXP ARM support. > > Could you please be more specific which part of code is non-DM based? > > I checked it and didn't find where is non-DM. > > Thanks for your review. > > For example, the "config ARCH_LS1028A" selects the following I2C > components: > > + select SYS_I2C_MXC > + select SYS_I2C_MXC_I2C1 > + select SYS_I2C_MXC_I2C2 > + select SYS_I2C_MXC_I2C3 > + select SYS_I2C_MXC_I2C4 > + select SYS_I2C_MXC_I2C5 > + select SYS_I2C_MXC_I2C6 > + select SYS_I2C_MXC_I2C7 > + select SYS_I2C_MXC_I2C8 > > These I2C# macros look to me this is not DM based. For DM such stuff is > determined from the DT automatically. Agree. Our I2C IP owner is working on it and will change all I2C driver to DM based. > > For ls1028a_serdes.c, we probably need create serdes uclass driver for it. We don't have serdes dts node in both uboot and kernel. So I think we can leave it as it is. > > For arch/arm/cpu/armv8/fsl-layerscape/cpu.c, can we create a CPU driver for > it? I see lots of CONFIG_XXX_BASE and CONFIG_XXX_SIZE in this file that > come from arch/arm/include/asm/arch-fsl-layerscape/cpu.h? Can't we get > such in DT? Agree. But this affects all our platforms and need big efforts. Many components are involved in it. We will convert it step by step. BR, Andy > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [EXT] Re: [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A SoC support
Hi Bin, > -Original Message- > From: Bin Meng > Sent: 2019年5月16日 20:10 > To: Andy Tang ; Simon Glass ; > Tom Rini > Cc: Prabhakar Kushwaha ; Sudhanshu > Gupta ; U-Boot Mailing List > ; Ran Wang ; Bhaskar > Upadhaya > Subject: [EXT] Re: [U-Boot] [PATCH 1/3 v3] armv8: ls1028a: Add NXP LS1028A > SoC support > > > Hi, > > On Wed, Apr 10, 2019 at 4:50 PM Yuantian Tang > wrote: > > > > Ls1028a Soc is based on Layerscape Chassis Generation 3.2 architecture > > with features: > > 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN > > ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, > > 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. > > > > Signed-off-by: Sudhanshu Gupta > > Signed-off-by: Rai Harninder > > Signed-off-by: Rajesh Bhagat > > Signed-off-by: Bhaskar Upadhaya > > Signed-off-by: Tang Yuantian > > --- > > v3: > > -- fix some issues > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 + > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 73 ++ > > arch/arm/dts/fsl-ls1028a.dtsi | 280 > + > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 + > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + > > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- > > 10 files changed, 521 insertions(+), 2 deletions(-) create mode > > 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi > > > > I really would like to see complete DM driver support on this new platform. > Please consider converting appropriate codes to driver model. If there is no > proper uclass model, please propose one and discuss it on the list. I see the > existing NXP PowerPC support is stuck in such a situation that lots of codes > are still non-DM and we are getting close to the DM deadline. I don't want to > see such happens again in the NXP ARM support. Could you please be more specific which part of code is non-DM based? I checked it and didn't find where is non-DM. Thanks for your review. BR, Andy > > Thanks! > > Regards, > Bin ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support
Hi Prabhakar, > -Original Message- > From: Prabhakar Kushwaha > Sent: 2019年4月7日 17:58 > To: Andy Tang > Cc: albert.u.b...@aribaud.net; Sudhanshu Gupta ; > Harninder Rai ; Rajesh Bhagat > ; Bhaskar Upadhaya ; > u-boot@lists.denx.de; Andy Tang > Subject: RE: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support > > > > -Original Message- > > From: Yuantian Tang > > Sent: Wednesday, April 3, 2019 12:48 PM > > To: Prabhakar Kushwaha > > Cc: albert.u.b...@aribaud.net; Sudhanshu Gupta > > ; Harninder Rai ; > > Rajesh Bhagat ; Bhaskar Upadhaya > > ; u-boot@lists.denx.de; Andy Tang > > > > Subject: [PATCH 1/3 v2] armv8: ls1028a: Add NXP LS1028A SoC support > > > > LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with a > > GPU and LCD controller, as well as TSN-enabled Ethernet ports and a > > TSN-enabled switch with four external ports. > > The high performance Cortex-A72 cores, performing above 16,000 > > CoreMarks, combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA > > 3.0, USB 3.0 and Octal/Quad SPI interfaces provide capabilities for a > > number of industrial and embedded applications. The device provides > > excellent integration with the new Time-Sensitive Networking standards > > and enables a number of TSN applications > > > > Features Summary > > * Two 32/64-bit Arm v8 Cortex-A72 CPUs > > * Cache coherent interconnect fabric (CCI-400) > > * 32-bit DDR3L/DDR4 SDRAM memory controller with ECC support > > * LCD controller and DisplayPort/eDP interface > > * Graphics processing unit > > * TSN-capable Ethernet Switch with four external ports > > * Ethernet Controller (ENETC) with TSN functionality > > * Four SerDes lanes with two PLLs for high-speed peripheral interfaces > > * Additional peripheral interfaces > > * Two high-speed USB 3.0 controllers > > * Two eSDHC controllers > > * Two controller area network (FlexCAN) modules > > * supporting flexible datarate (FD) > > * Three serial peripheral interface (SPI) controllers > > * Flexible SPI interface (FlexSPI) controller > > * Eight I2C controllers > > * Six LPUARTs > > * 16550-compliant DUART > > * General Purpose IO (GPIO) > > * Eight FlexTimers/PWM controllers > > * Six asynchronous audio interface (SAI) > > * Support for hardware virtualization and partitioning enforcement > > * QorIQ platform's trust architecture 3.0 > > * Queue direct memory access controller (qDMA) > > * Enhanced direct memory access controller (eDMA) > > * Global programmable interrupt controller (GIC) > > * Arm generic timer > > * Thermal Monitor Unit (TMU) > > > > It looks to be marketing description > This patch is not supporting all above features. So update description with > whatever supported by this patch. It listed all the features SOC supports, not the features this PATCH supports. We should give a full feature list when a new soc was added. > > > > Signed-off-by: Sudhanshu Gupta > > Signed-off-by: Rai Harninder > > Signed-off-by: Rajesh Bhagat > > Signed-off-by: Bhaskar Upadhaya > > Signed-off-by: Tang Yuantian > > --- > > v2: > > - fix many issues > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 ++- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 3 + > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 51 > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 88 +++ > > arch/arm/dts/fsl-ls1028a.dtsi | 280 > + > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 61 + > > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 16 ++ > > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 + > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + > > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +- > > 11 files changed, 552 insertions(+), 2 deletions(-) create mode 100644 > > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c > > create mode 100644 arch/arm/dts/fsl-ls1028a.dtsi > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > index f48481f..8ecd095 100644 > > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig > > @@ -20,6 +20,40 @@ config ARCH_LS1012A > > select SYS_I2C_MXC_I2C2 > > imply PANIC_HANG > > > >
Re: [U-Boot] [PATCH 4/4 v2] arm64: ls1012a: enable DM support for sata
Hi York, Sorry it is my fault. I resent this patch set with this issue fixed. I also found 1/4 patch can't be applied probably because the code base has changed. The new patch set I sent is based on the latest code. Please reapply them, thanks. Regards, Andy -Original Message- From: York Sun Sent: 2018年7月13日 6:02 To: Andy Tang Cc: michal.si...@xilinx.com; albert.u.b...@aribaud.net; Prabhakar Kushwaha ; Sumit Garg ; s...@chromium.org; Y.b. Lu ; Peng Ma ; u-boot@lists.denx.de Subject: Re: [PATCH 4/4 v2] arm64: ls1012a: enable DM support for sata On 06/04/2018 02:13 AM, andy.t...@nxp.com wrote: > From: Yuantian Tang > > Enable related configs to support sata DM feature. > > Signed-off-by: Tang Yuantian > --- > v2: > - add 2g5rdb and qds board support > > configs/ls1012a2g5rdb_qspi_defconfig |6 +- > configs/ls1012aqds_qspi_defconfig |7 ++- > configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |7 ++- > configs/ls1012ardb_qspi_defconfig |7 ++- > 4 files changed, 23 insertions(+), 4 deletions(-) Andy, Does this set depend on something else? I got compiling error for all these four boards ../drivers/ata/sata_ceva.c:10:31: fatal error: asm/arch/hardware.h: No such file or directory York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4 v3] arm64: ls1012a: enable DM support for sata
From: Yuantian Tang Enable related configs to support sata DM feature. Signed-off-by: Tang Yuantian --- v3: - no changes v2: - add 2g5rdb and qds board support configs/ls1012a2g5rdb_qspi_defconfig |6 +- configs/ls1012aqds_qspi_defconfig |7 ++- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |7 ++- configs/ls1012ardb_qspi_defconfig |7 ++- 4 files changed, 23 insertions(+), 4 deletions(-) diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 37b63ff..223256e 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -29,7 +29,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -44,3 +44,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1f9b76a..7ade3da 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -34,7 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -56,3 +56,8 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 7dcfaae..4e3d58a 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -53,3 +53,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 6a8485c..7589431 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -30,7 +30,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -51,3 +51,8 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4 v3] armv8: dts: fsl-ls1012a: add sata node support
From: Yuantian Tang
One ls1012a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Tang Yuantian
---
v3:
- no changes
v2:
- add qds and 2g5rdb board support
arch/arm/dts/fsl-ls1012a-2g5rdb.dts |4
arch/arm/dts/fsl-ls1012a-qds.dtsi |4
arch/arm/dts/fsl-ls1012a-rdb.dtsi |4
arch/arm/dts/fsl-ls1012a.dtsi |8
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index db23cf8..cdd4ce4 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -40,3 +40,7 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi
b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index d069b60..661af0e 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -125,3 +125,7 @@
status = "okay";
phy_type = "ulpi";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 201e5fa..757e2eb 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -34,3 +34,7 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index be99076..f22cbf4 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -134,6 +134,14 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+ sata: sata@320 {
+ compatible = "fsl,ls1012a-ahci";
+ reg = <0x0 0x320 0x0 0x1>;
+ interrupts = <0 69 4>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
+
usb0: usb2@860 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x860 0x0 0x1000>;
--
1.7.1
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[U-Boot] [PATCH 3/4 v3] scsi: ceva: add ls1012a soc support
From: Yuantian Tang
Make the code structure more general so that more socs can be
added easily and also remove speed limitation restriction.
Add the ls1012a sata support as well.
Signed-off-by: Tang Yuantian
Reviewed-by: Michal Simek
Tested-by: Michal Simek
(with and without CONFIG_OF_LIVE on zynqmp zcu102)
---
v3:
- remove #include to fix compling warning
v2:
- refine the commit message
- use live tree functions
drivers/ata/sata_ceva.c | 87 ---
1 files changed, 52 insertions(+), 35 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index a7d45e8..047cff7 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -7,8 +7,6 @@
#include
#include
#include
-#include
-
#include
/* Vendor Specific Register Offsets */
@@ -18,6 +16,7 @@
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
@@ -72,45 +71,57 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
+/* flag bit definition */
+#define FLAG_COHERENT 1
+
+/* register config value */
+#define CEVA_PHY1_CFG 0xa003fffe
+#define CEVA_PHY2_CFG 0x28184d1f
+#define CEVA_PHY3_CFG 0x0e081509
+#define CEVA_TRANS_CFG 0x0829
+#define CEVA_AXICC_CFG 0x3fff
+
+/* ecc addr-val pair */
+#define ECC_DIS_ADDR_CH2 0x8000
+#define ECC_DIS_VAL_CH20x20140520
+
+enum ceva_soc {
+ CEVA_1V84,
+ CEVA_LS1012A,
+};
+
struct ceva_sata_priv {
ulong base;
+ enum ceva_soc soc;
+ ulong flag;
};
-static int ceva_init_sata(ulong mmio)
+static int ceva_init_sata(struct ceva_sata_priv *priv)
{
+ ulong base = priv->base;
ulong tmp;
- int i;
-
- /*
-* AXI Data bus width to 64
-* Set Mem Addr Read, Write ID for data transfers
-* Transfer limit to 72 DWord
-*/
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
- writel(tmp, mmio + AHCI_VEND_PAXIC);
-
- /* Set AHCI Enable */
- tmp = readl(mmio + HOST_CTL);
- tmp |= HOST_AHCI_EN;
- writel(tmp, mmio + HOST_CTL);
-
- for (i = 0; i < NR_PORTS; i++) {
- /* TPSS TPRS scalars, CISE and Port Addr */
- tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
- writel(tmp, mmio + AHCI_VEND_PCFG);
-
- /* Port Phy Cfg register enables */
- tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
- writel(tmp, mmio + AHCI_VEND_PPCFG);
- /* Rx Watermark setting */
+ switch (priv->soc) {
+ case CEVA_1V84:
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, base + AHCI_VEND_PAXIC);
+ tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
+ writel(tmp, base + AHCI_VEND_PCFG);
+ tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+ writel(tmp, base + AHCI_VEND_PPCFG);
tmp = PTC_RX_WM_VAL | PTC_RSVD;
- writel(tmp, mmio + AHCI_VEND_PTC);
-
- /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
- tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
- writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+ writel(tmp, base + AHCI_VEND_PTC);
+ break;
+
+ case CEVA_LS1012A:
+ writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+ break;
}
+
return 0;
}
@@ -125,13 +136,14 @@ static int sata_ceva_probe(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- ceva_init_sata(priv->base);
+ ceva_init_sata(priv);
return ahci_probe_scsi(dev, priv->base);
}
static const struct udevice_id sata_ceva_ids[] = {
- { .compatible = "ceva,ahci-1v84" },
+ { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
+ { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ }
};
@@ -139,10 +151,15 @@ static int sata_ceva_ofdata_to_platdata(struct udevice
*dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ if (dev_read_bool(dev, "dma-coherent"))
+ priv->flag |= FLAG_COHERENT;
+
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ priv->soc = dev_get_driver_data(dev);
+
return 0;
}
--
1.7.1
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[U-Boot] [PATCH 1/4 v3] armv8: fsl: remove sata support
From: Yuantian Tang
Remove the old implementation in order to enable DM for sata
Signed-off-by: Tang Yuantian
---
v3:
- rebase to latest code
v2:
- no changes
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 54
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 32 --
2 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index bfd6639..8028d52 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,8 +6,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
#endif
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
- ccsr_ahci = (void *)CONFIG_SYS_SATA2;
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
- ccsr_ahci = (void *)CONFIG_SYS_SATA1;
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA1);
- scsi_scan(false);
-#endif
-
- return 0;
-}
-#endif
-
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
@@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
}
#elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
- /* Disable SATA ECC */
- out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA);
- scsi_scan(false);
-
- return 0;
-}
-#endif
static void erratum_a009929(void)
{
@@ -719,9 +668,6 @@ int qspi_ahb_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a219a6..6e3a420 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -85,39 +85,7 @@ struct cpu_type {
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
-#define AHCI_PORT_TRANS_CFG0x0829
-#define AHCI_PORT_AXICC_CFG0x3fff
-
#ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 axicc; /* AXI cache control */
- u32 paxic; /* port AXI config */
- u32 axipc; /* AXI PROT control */
- u32 ptc;/* port Trans Config */
- u32 pts;/* port Trans Status */
- u32 plc;/* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls;/* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
int get_core_volt_from_fuse(void);
--
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[U-Boot] [PATCH 3/4 v2] scsi: ceva: add ls1012a soc support
From: Yuantian Tang
Make the code structure more general so that more socs can be
added easily and also remove speed limitation restriction.
Add the ls1012a sata support as well.
Signed-off-by: Tang Yuantian
Reviewed-by: Michal Simek
Tested-by: Michal Simek
(with and without CONFIG_OF_LIVE on zynqmp zcu102)
---
v2:
- refine the commit message
- use live tree functions
drivers/ata/sata_ceva.c | 85 --
1 files changed, 52 insertions(+), 33 deletions(-)
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index a7d45e8..2e8296c 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -18,6 +18,7 @@
#define AHCI_VEND_PP3C 0xB0
#define AHCI_VEND_PP4C 0xB4
#define AHCI_VEND_PP5C 0xB8
+#define AHCI_VEND_AXICC 0xBc
#define AHCI_VEND_PAXIC 0xC0
#define AHCI_VEND_PTC 0xC8
@@ -72,45 +73,57 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
+/* flag bit definition */
+#define FLAG_COHERENT 1
+
+/* register config value */
+#define CEVA_PHY1_CFG 0xa003fffe
+#define CEVA_PHY2_CFG 0x28184d1f
+#define CEVA_PHY3_CFG 0x0e081509
+#define CEVA_TRANS_CFG 0x0829
+#define CEVA_AXICC_CFG 0x3fff
+
+/* ecc addr-val pair */
+#define ECC_DIS_ADDR_CH2 0x8000
+#define ECC_DIS_VAL_CH20x20140520
+
+enum ceva_soc {
+ CEVA_1V84,
+ CEVA_LS1012A,
+};
+
struct ceva_sata_priv {
ulong base;
+ enum ceva_soc soc;
+ ulong flag;
};
-static int ceva_init_sata(ulong mmio)
+static int ceva_init_sata(struct ceva_sata_priv *priv)
{
+ ulong base = priv->base;
ulong tmp;
- int i;
-
- /*
-* AXI Data bus width to 64
-* Set Mem Addr Read, Write ID for data transfers
-* Transfer limit to 72 DWord
-*/
- tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
- writel(tmp, mmio + AHCI_VEND_PAXIC);
-
- /* Set AHCI Enable */
- tmp = readl(mmio + HOST_CTL);
- tmp |= HOST_AHCI_EN;
- writel(tmp, mmio + HOST_CTL);
-
- for (i = 0; i < NR_PORTS; i++) {
- /* TPSS TPRS scalars, CISE and Port Addr */
- tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
- writel(tmp, mmio + AHCI_VEND_PCFG);
-
- /* Port Phy Cfg register enables */
- tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
- writel(tmp, mmio + AHCI_VEND_PPCFG);
- /* Rx Watermark setting */
+ switch (priv->soc) {
+ case CEVA_1V84:
+ tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+ writel(tmp, base + AHCI_VEND_PAXIC);
+ tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
+ writel(tmp, base + AHCI_VEND_PCFG);
+ tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
+ writel(tmp, base + AHCI_VEND_PPCFG);
tmp = PTC_RX_WM_VAL | PTC_RSVD;
- writel(tmp, mmio + AHCI_VEND_PTC);
-
- /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
- tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
- writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
+ writel(tmp, base + AHCI_VEND_PTC);
+ break;
+
+ case CEVA_LS1012A:
+ writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
+ if (priv->flag & FLAG_COHERENT)
+ writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
+ break;
}
+
return 0;
}
@@ -125,13 +138,14 @@ static int sata_ceva_probe(struct udevice *dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- ceva_init_sata(priv->base);
+ ceva_init_sata(priv);
return ahci_probe_scsi(dev, priv->base);
}
static const struct udevice_id sata_ceva_ids[] = {
- { .compatible = "ceva,ahci-1v84" },
+ { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
+ { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
{ }
};
@@ -139,10 +153,15 @@ static int sata_ceva_ofdata_to_platdata(struct udevice
*dev)
{
struct ceva_sata_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ if (dev_read_bool(dev, "dma-coherent"))
+ priv->flag |= FLAG_COHERENT;
+
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
+ priv->soc = dev_get_driver_data(dev);
+
return 0;
}
--
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[U-Boot] [PATCH 4/4 v2] arm64: ls1012a: enable DM support for sata
From: Yuantian Tang Enable related configs to support sata DM feature. Signed-off-by: Tang Yuantian --- v2: - add 2g5rdb and qds board support configs/ls1012a2g5rdb_qspi_defconfig |6 +- configs/ls1012aqds_qspi_defconfig |7 ++- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig |7 ++- configs/ls1012ardb_qspi_defconfig |7 ++- 4 files changed, 23 insertions(+), 4 deletions(-) diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 37b63ff..223256e 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -29,7 +29,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -44,3 +44,7 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1f9b76a..7ade3da 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -34,7 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -56,3 +56,8 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 7dcfaae..4e3d58a 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -53,3 +53,8 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 6a8485c..7589431 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -30,7 +30,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -# CONFIG_BLK is not set +CONFIG_BLK=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -51,3 +51,8 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +CONFIG_AHCI=y -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4 v2] armv8: dts: fsl-ls1012a: add sata node support
From: Yuantian Tang
One ls1012a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Tang Yuantian
---
v2:
- add qds and 2g5rdb board support
arch/arm/dts/fsl-ls1012a-2g5rdb.dts |4
arch/arm/dts/fsl-ls1012a-qds.dtsi |4
arch/arm/dts/fsl-ls1012a-rdb.dtsi |4
arch/arm/dts/fsl-ls1012a.dtsi |8
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
index db23cf8..cdd4ce4 100644
--- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -40,3 +40,7 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi
b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index d069b60..661af0e 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -125,3 +125,7 @@
status = "okay";
phy_type = "ulpi";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
index 201e5fa..757e2eb 100644
--- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -34,3 +34,7 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index be99076..f22cbf4 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -134,6 +134,14 @@
0x8200 0x0 0x4000 0x40 0x4000 0x0
0x4000>; /* non-prefetchable memory */
};
+ sata: sata@320 {
+ compatible = "fsl,ls1012a-ahci";
+ reg = <0x0 0x320 0x0 0x1>;
+ interrupts = <0 69 4>;
+ clocks = < 4 0>;
+ status = "disabled";
+ };
+
usb0: usb2@860 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x860 0x0 0x1000>;
--
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[U-Boot] [PATCH 1/4 v2] armv8: fsl: remove sata support
From: Yuantian Tang
Remove the old implementation in order to enable DM for sata
Signed-off-by: Tang Yuantian
---
v2:
- no change
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 54
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 32 --
2 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index bfd6639..8028d52 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,8 +6,6 @@
#include
#include
#include
-#include
-#include
#include
#include
#include
@@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
#endif
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci;
-
-#ifdef CONFIG_SYS_SATA2
- ccsr_ahci = (void *)CONFIG_SYS_SATA2;
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-#endif
-
-#ifdef CONFIG_SYS_SATA1
- ccsr_ahci = (void *)CONFIG_SYS_SATA1;
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA1);
- scsi_scan(false);
-#endif
-
- return 0;
-}
-#endif
-
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
@@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
}
#elif defined(CONFIG_FSL_LSCH2)
-#ifdef CONFIG_SCSI_AHCI_PLAT
-int sata_init(void)
-{
- struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
-
- /* Disable SATA ECC */
- out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x8000);
- out_le32(_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
- out_le32(_ahci->pp2c, AHCI_PORT_PHY2_CFG);
- out_le32(_ahci->pp3c, AHCI_PORT_PHY3_CFG);
- out_le32(_ahci->ptc, AHCI_PORT_TRANS_CFG);
- out_le32(_ahci->axicc, AHCI_PORT_AXICC_CFG);
-
- ahci_init((void __iomem *)CONFIG_SYS_SATA);
- scsi_scan(false);
-
- return 0;
-}
-#endif
static void erratum_a009929(void)
{
@@ -719,9 +668,6 @@ int qspi_ahb_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
-#ifdef CONFIG_SCSI_AHCI_PLAT
- sata_init();
-#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 9a219a6..6e3a420 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -85,39 +85,7 @@ struct cpu_type {
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG0xa003fffe
-#define AHCI_PORT_PHY2_CFG 0x28184d1f
-#define AHCI_PORT_PHY3_CFG 0x0e081509
-#define AHCI_PORT_TRANS_CFG0x0829
-#define AHCI_PORT_AXICC_CFG0x3fff
-
#ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
- u32 pcfg; /* port config */
- u32 ppcfg; /* port phy1 config */
- u32 pp2c; /* port phy2 config */
- u32 pp3c; /* port phy3 config */
- u32 pp4c; /* port phy4 config */
- u32 pp5c; /* port phy5 config */
- u32 axicc; /* AXI cache control */
- u32 paxic; /* port AXI config */
- u32 axipc; /* AXI PROT control */
- u32 ptc;/* port Trans Config */
- u32 pts;/* port Trans Status */
- u32 plc;/* port link config */
- u32 plc1; /* port link config1 */
- u32 plc2; /* port link config2 */
- u32 pls;/* port link status */
- u32 pls1; /* port link status1 */
- u32 pcmdc; /* port CMD config */
- u32 ppcs; /* port phy control status */
- u32 pberr; /* port 0/1 BIST error */
- u32 cmds; /* port 0/1 CMD status error */
-};
-
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
int get_core_volt_from_fuse(void);
--
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Re: [U-Boot] [PATCH 3/4] scsi: ceva: add ls1012a soc support
Got it, thanks.
Regards,
Andy
-Original Message-
From: Michal Simek [mailto:michal.si...@xilinx.com]
Sent: 2018年5月28日 16:29
To: Andy Tang <andy.t...@nxp.com>; York Sun <york@nxp.com>
Cc: michal.si...@xilinx.com; albert.u.b...@aribaud.net; Prabhakar Kushwaha
<prabhakar.kushw...@nxp.com>; Sumit Garg <sumit.g...@nxp.com>;
s...@chromium.org; Y.b. Lu <yangbo...@nxp.com>; u-boot@lists.denx.de
Subject: Re: [PATCH 3/4] scsi: ceva: add ls1012a soc support
On 25.5.2018 11:06, andy.t...@nxp.com wrote:
> From: Yuantian Tang <andy.t...@nxp.com>
>
> Adjust the code structure more general so that more socs can be added
> easily.
> Add the ls1012a sata support as well.
>
Please also mentioned that speed limitation restriction here.
> Signed-off-by: Tang Yuantian <andy.t...@nxp.com>
> ---
> drivers/ata/sata_ceva.c | 87 +-
> 1 files changed, 55 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index
> a7d45e8..4c9ebe4 100644
> --- a/drivers/ata/sata_ceva.c
> +++ b/drivers/ata/sata_ceva.c
> @@ -18,6 +18,7 @@
> #define AHCI_VEND_PP3C 0xB0
> #define AHCI_VEND_PP4C 0xB4
> #define AHCI_VEND_PP5C 0xB8
> +#define AHCI_VEND_AXICC 0xBc
> #define AHCI_VEND_PAXIC 0xC0
> #define AHCI_VEND_PTC 0xC8
>
> @@ -72,45 +73,57 @@
> #define DRV_NAME "ahci-ceva"
> #define CEVA_FLAG_BROKEN_GEN21
>
> +/* flag bit definition */
> +#define FLAG_COHERENT1
> +
> +/* register config value */
> +#define CEVA_PHY1_CFG0xa003fffe
> +#define CEVA_PHY2_CFG0x28184d1f
> +#define CEVA_PHY3_CFG0x0e081509
> +#define CEVA_TRANS_CFG 0x0829
> +#define CEVA_AXICC_CFG 0x3fff
> +
> +/* ecc addr-val pair */
> +#define ECC_DIS_ADDR_CH2 0x8000
> +#define ECC_DIS_VAL_CH2 0x20140520
> +
> +enum ceva_soc {
> + CEVA_1V84,
> + CEVA_LS1012A,
> +};
> +
> struct ceva_sata_priv {
> ulong base;
> + enum ceva_soc soc;
> + ulong flag;
> };
>
> -static int ceva_init_sata(ulong mmio)
> +static int ceva_init_sata(struct ceva_sata_priv *priv)
> {
> + ulong base = priv->base;
> ulong tmp;
> - int i;
> -
> - /*
> - * AXI Data bus width to 64
> - * Set Mem Addr Read, Write ID for data transfers
> - * Transfer limit to 72 DWord
> - */
> - tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
> - writel(tmp, mmio + AHCI_VEND_PAXIC);
> -
> - /* Set AHCI Enable */
> - tmp = readl(mmio + HOST_CTL);
> - tmp |= HOST_AHCI_EN;
> - writel(tmp, mmio + HOST_CTL);
> -
> - for (i = 0; i < NR_PORTS; i++) {
> - /* TPSS TPRS scalars, CISE and Port Addr */
> - tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
> - writel(tmp, mmio + AHCI_VEND_PCFG);
> -
> - /* Port Phy Cfg register enables */
> - tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
> - writel(tmp, mmio + AHCI_VEND_PPCFG);
>
> - /* Rx Watermark setting */
> + switch (priv->soc) {
> + case CEVA_1V84:
> + tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
> + writel(tmp, base + AHCI_VEND_PAXIC);
> + tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
> + writel(tmp, base + AHCI_VEND_PCFG);
> + tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
> + writel(tmp, base + AHCI_VEND_PPCFG);
> tmp = PTC_RX_WM_VAL | PTC_RSVD;
> - writel(tmp, mmio + AHCI_VEND_PTC);
> -
> - /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
> - tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
> - writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
> + writel(tmp, base + AHCI_VEND_PTC);
> + break;
> +
> + case CEVA_LS1012A:
> + writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
> + writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
> + writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
> + if (priv->flag & FLAG_COHERENT)
> + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
> + break;
> }
> +
> return 0;
> }
>
> @@ -125,24 +138,34 @@ static int sata_ceva_probe(struct udevice *dev)
> {
> struct ceva_sata_priv *priv = dev_get_priv(dev);
>
> - ceva_init_sata(priv->base);
> + ceva_init_sata(priv);
>
> return ahci_probe_scsi(dev, priv->base); }
>
> static c
Re: [U-Boot] help on DM
Thanks Simon. We convert the driver to ahci uclass. Problem solved. Regards, Andy -Original Message- From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass Sent: 2018年5月16日 23:40 To: Andy Tang <andy.t...@nxp.com> Cc: u-boot@lists.denx.de Subject: Re: help on DM Hi Andy, On 8 May 2018 at 19:48, Andy Tang <andy.t...@nxp.com> wrote: > Hi Simon, > > > > I am working on enabling DM for sata driver. Previously sata was > initialized by calling > > the functions ahci_init() and scsi_scan(). Now I plan to use > driver/ata/sata_ceva.c as our sata driver. > > In board config file I enabled the following configs (dts was added > properly): > > > > +CONFIG_DM_SCSI=y > > +CONFIG_SATA_CEVA=y > > +CONFIG_AHCI=y > > +CONFIG_BLK=y > > +CONFIG_SCSI_AHCI=y > > +CONFIG_SCSI=y > > > > But I always got the "Synchronous Abort" error. I tracked the code and > found > > dev->uclass_priv was not allocated properly because > dev->uclass->uc_drv->per_device_auto_alloc_size is 0. > > But I didn’t find where I can set per_device_auto_alloc_size or attach > a uclass_priv structure to the device. > > > > I am new to DM. Could you please give me some suggestions here? So you are expecting that the SCSI uclass should have some per-device uclass data? I don't think this is the case at present. Which code is actually crashing here? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] help on DM
Hi Simon, I am working on enabling DM for sata driver. Previously sata was initialized by calling the functions ahci_init() and scsi_scan(). Now I plan to use driver/ata/sata_ceva.c as our sata driver. In board config file I enabled the following configs (dts was added properly): +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_AHCI=y +CONFIG_BLK=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y But I always got the "Synchronous Abort" error. I tracked the code and found dev->uclass_priv was not allocated properly because dev->uclass->uc_drv->per_device_auto_alloc_size is 0. But I didn't find where I can set per_device_auto_alloc_size or attach a uclass_priv structure to the device. I am new to DM. Could you please give me some suggestions here? Thanks, Andy ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: layerscape: refine port register configuration
Hi York, This patch is to adjust the OOB (out of bound) timing of sata port. It is totally hardware timing. I was asked to update those timing by hardware/validation team. They calculated those values from clock frequency. You can apply it safely. Please apply this patch with SATA added. Thanks, Andy > -Original Message- > From: York Sun > Sent: Tuesday, December 05, 2017 12:47 AM > To: Andy Tang <andy.t...@nxp.com> > Cc: albert.u.b...@aribaud.net; s...@chromium.org; u-boot@lists.denx.de > Subject: Re: [PATCH] armv8: layerscape: refine port register configuration > > On 12/04/2017 01:31 AM, Yuantian Tang wrote: > > These PP2C and PP3C registers control the configuration of the PHY > > control OOB timing for the COMINIT/COMWAKE parameters respectively > for > > sata port. Overwrite default values with calculated ones to get better > > OOB timing. > > > > Signed-off-by: Tang Yuantian <andy.t...@nxp.com> > > --- > > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 6 ++ > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++ > > 2 files changed, 8 insertions(+) > > Andy, > > Maybe it was obvious to you, but I couldn't understand why and what you > are changing, except you overwrite two registers. > > By the way, you may want to add SATA (in upper case) in the subject. > > York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: configs: ls1012a: correct the generic timer frequency issue
Hi York, Ls1012a uses the fixed 25Mhz clock, I will update the commit message and resend the patch. Thanks, Andy > -Original Message- > From: York Sun > Sent: Tuesday, October 10, 2017 12:00 AM > To: Andy Tang <andy.t...@nxp.com> > Cc: s...@chromium.org; u-boot@lists.denx.de > Subject: Re: [PATCH] armv8: configs: ls1012a: correct the generic timer > frequency issue > > On 10/08/2017 11:48 PM, andy.t...@nxp.com wrote: > > From: Yuantian Tang <andy.t...@nxp.com> > > > > Generic Timer frequency should be 25Mhz. Current setting is > > CONFIG_SYS_CLK_FREQ/4 which is about 31Mhz, which is not correct. > > So correct it. > > > > Signed-off-by: Tang Yuantian <andy.t...@nxp.com> > > --- > > include/configs/ls1012a_common.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/include/configs/ls1012a_common.h > > b/include/configs/ls1012a_common.h > > index 096799eb64..a4e78f335f 100644 > > --- a/include/configs/ls1012a_common.h > > +++ b/include/configs/ls1012a_common.h > > @@ -32,7 +32,7 @@ > > #define CONFIG_SYS_DDR_BLOCK2_BASE 0x88000ULL > > > > /* Generic Timer Definitions */ > > -#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 > /* 25MHz */ > > +#define COUNTER_FREQUENCY 2500/* 25MHz */ > > > > > Yuantian, > > LS1012A use fixed 25MHz clock, doesn't it? If so, that's the reason a fixed > value should be used, not because CONFIG_SYS_CLK_FREQ/4 isn't correct. It > is correct for many other platform. Please update the commit message. > > York > ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] armv8: ls1046aqds: enable ppa in default config
Hi York, Thanks for you reminder. Hou Ziqiang will continue to submit ppa patch for LS1046AQDS which will replace mine. Regards, Andy -Original Message- From: York Sun [mailto:york@nxp.com] Sent: Tuesday, April 18, 2017 11:46 PM To: Andy Tang <andy.t...@nxp.com> Cc: u-boot@lists.denx.de Subject: Re: [PATCH 2/2] armv8: ls1046aqds: enable ppa in default config On 03/09/2017 11:03 PM, Yuantian Tang wrote: > Signed-off-by: Tang Yuantian <andy.t...@nxp.com> > --- > configs/ls1046aqds_defconfig | 1 + > configs/ls1046aqds_lpuart_defconfig | 1 + > configs/ls1046aqds_nand_defconfig| 1 + > configs/ls1046aqds_qspi_defconfig| 1 + > configs/ls1046aqds_sdcard_ifc_defconfig | 1 + > configs/ls1046aqds_sdcard_qspi_defconfig | 1 + > 6 files changed, 6 insertions(+) > Applied to u-boot-fsl-qoriq master, awaiting upstream. Thanks. Please note, even this patch is applied, PPA for LS1046AQDS is not loaded until you add the support in board file. Please update your first patch in this set. York ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
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