Re: [USRP-users] Connect Eth Phy to FPGA
Hello, Thank you for your answers. Actually, we need to achieve this task. This task should be performed in B210 (I guess, ethernet MAC is drived by FPGA in here). So, how can i start to this task ? Where can i find an example or some information to drive built-in ethernet MAC in FPGA ? It will be appreciated, if you can give a point to start. Best regards. On 21.05.2019 22:14, Philip Balister wrote: On 05/21/2019 02:56 PM, Sylvain Munaut wrote: Hi, Yes, it's connected to the PS and not the PL. _However_ ... you could just remove the ethernet driver from the linux side, then drive the built-in ethernet mac from the FPGA by just acting as an AXI master. None of this is trivial however ... But it is possible. I'd love to see someone try it. Philip Cheers, Sylvain ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Connect Eth Phy to FPGA
Hello, We want to use E310 as a peripheral network device like N210. We want the RF samples come to ethernet interface through FPGA without passing from CPU. In short, we don't want to use CPU. So, can we configure FPGA to achieve this task? (Connecting ethernet interface directly to FPGA) Best regards. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Handling Stream Tags in RFNoC Block
Hello,
I am trying to make OFDM transmitter on E310. In attached flowgraph
there are lots of gnuradio blocks for OFDM TX. I want to put FFT block
into FPGA to reduce computation load on CPU.
But data is passed with tags like tagged stream, so when i used RFNoC:
FFT block instead of gnuradio FFT block, it gives this error;
thread[thread-per-block[18]: ]: Missing
length tag.
So, normally inside of rfnoc_block_impl.cc,
set_tag_propagation_policy(TPP_DONT) is specified. But, i wanted to pass
tags, so i changed this code to
set_tag_propagation_policy(TPP_ONE_TO_ONE). I tought now it can pass
length_tag to cyclic_prefix block. But this time it gave that error;
thread[thread-per-block[21]: ]: pmt_dict_keys:
wrong_type : #
thread[thread-per-block[17]: ]: pmt_dict_keys:
wrong_type : #
So, how can i pass the length_tag over RFNoC gnuradio block ?
Thanks, regards.
Ramazan
Wed Jul 9 15:50:17 2014
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Re: [USRP-users] Running E310 in Network Mode
Hello Robin, Thank you for your answer. I will explain my situation why we want this. I need to build a OFDM mesh networking setup and we bought several E310 devices due to some size limitations. So, i need to achieve OFDM mesh network in E310 devices. Firstly, i tried with embedded CPU but it cannot handle incoming data rate due to its limited computational capability. When i try RFNoC, just 3 of RFNoC blocks can fit into FPGA and there is no OFDM implementation with three blocks. So, i guess i need to place some blocks on FPGA and some blocks on CPU. Is it right? Can you suggest a way to achieve this task on E310? On 9.05.2019 09:37, Robin Coxe wrote: If you need higher BW streaming to a host PC in network mode with a similar front end to the E310, take a look at the USRP E320 if you need a 10gigE link or the B210 if USB 3.0 data rates are sufficient. The E310 was designed to be a standalone embedded SDR, not a networked device with full BW streaming capabilities. -Robin *From:* USRP-users on behalf of Ramazan Çetin via USRP-users *Sent:* Wednesday, May 8, 2019 11:21 PM *To:* Jason Matusiak; usrp-users@lists.ettus.com *Subject:* Re: [USRP-users] Running E310 in Network Mode Hello Jason, Thank you for your answer. Actually, i have investigated this link. But, i would like to remove limitations on network mode and use USRP E310 line USRP N210. Passing samples directly from FPGA to network. Is it possible? Regards. On 8.05.2019 17:14, Jason Matusiak wrote: See here: https://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_network_mode *From:* USRP-users on behalf of Ramazan Çetin via USRP-users *Sent:* Wednesday, May 8, 2019 8:02 AM *To:* Ettus Research Support; usrp-users@lists.ettus.com *Subject:* [USRP-users] Running E310 in Network Mode Hello, We want to run USRP E310 in network mode. I think the samples coming from FPGA passing through CPU before sending to network. This decreases bandwidth because of CPU limitations. So, is there any ettus image or suggestions that we can run E310 directly from FPGA to network without speed limitations? (like N210 or B210) Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Running E310 in Network Mode
Hello Jason, Thank you for your answer. Actually, i have investigated this link. But, i would like to remove limitations on network mode and use USRP E310 line USRP N210. Passing samples directly from FPGA to network. Is it possible? Regards. On 8.05.2019 17:14, Jason Matusiak wrote: See here: https://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_network_mode *From:* USRP-users on behalf of Ramazan Çetin via USRP-users *Sent:* Wednesday, May 8, 2019 8:02 AM *To:* Ettus Research Support; usrp-users@lists.ettus.com *Subject:* [USRP-users] Running E310 in Network Mode Hello, We want to run USRP E310 in network mode. I think the samples coming from FPGA passing through CPU before sending to network. This decreases bandwidth because of CPU limitations. So, is there any ettus image or suggestions that we can run E310 directly from FPGA to network without speed limitations? (like N210 or B210) Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Running E310 in Network Mode
Hello, We want to run USRP E310 in network mode. I think the samples coming from FPGA passing through CPU before sending to network. This decreases bandwidth because of CPU limitations. So, is there any ettus image or suggestions that we can run E310 directly from FPGA to network without speed limitations? (like N210 or B210) Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Installing opencv-python on E310
Hello all, I need to use opencv-python library on E310. When i try installing using pip, it gives me this error: root@ettus-e3xx-sg3:~# pip install opencv-python Collecting opencv-python Could not find a version that satisfies the requirement opencv-python (from versions: ) No matching distribution found for opencv-python We also tried adding opencv package to meta layer in bitbake. But, it also fails. (There is also no python-opencv layer in openembedded) So, can you suggest a way to install opencv-python? ( I could install matplotlib using pip) Best regards Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] N310 RFNoC OOT Module Build Issue
Hello, I am trying to build basic OOT module for N310. My UHD version is 3.14.0.0-rc1 (I also tried with 3.14.0.0). I can build FPGA image without OOT modules for N310. But when i try building with OOT module using this command, it gives this error: rcetin@rcetin-ThinkPad-W530:~/rfnoc/fpga/usrp3$ ./uhd_image_builder.py gain -I /home/rcetin/rfnoc/rfnoc-gohm -d N310 -t N310_RFNOC_HG --Using the following blocks to generate image: * gain Adding CE instantiation file for 'N310_RFNOC_HG' changing temporarily working directory to /home/rcetin/rfnoc/fpga/usrp3/tools/scripts/../../top/n3xx Setting up a 64-bit FPGA build environment for the USRP-N3x0... - Vivado: Found (/home/rcetin/opt/Xilinx/Vivado/2017.4/bin) Environment successfully initialized. make -f Makefile.n3xx.inc bin NAME=N310_RFNOC_HG ARCH=zynq PART_ID=xc7z100/ffg900/-2 SFP0_1GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_1G=1 BUILD_10G=1 RFNOC=1 N310=1 TOP_MODULE=n3xx EXTRA_DEFS="SFP0_1GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_1G=1 BUILD_10G=1 RFNOC=1 N310=1" make[1]: Entering directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx' BUILDER: Checking tools... * GNU bash, version 4.4.19(1)-release (x86_64-pc-linux-gnu) * Python 2.7.15rc1 * Vivado v2017.4 (64-bit) Using parser configuration from: /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dev_config.json [00:00:00] Executing command: vivado -mode batch -source /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/build_n3xx.tcl -log build.log -journal n3xx.jou [00:00:01] Current task: Initialization +++ Current Phase: Starting . . . ERROR: [Synth 8-439] module 'noc_block_gain' not found [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:22] ERROR: [Synth 8-285] failed synthesizing module 'n3xx_core' [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/n3xx_core.v:17] ERROR: [Synth 8-285] failed synthesizing module 'n3xx' [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v:13] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [00:07:18] Current task: Synthesis +++ Current Phase: Starting [00:07:19] Current task: Synthesis +++ Current Phase: Finished [00:07:19] Process terminated. Status: Failure Warnings: 322 Critical Warnings: 4 Errors: 4 Makefile.n3xx.inc:149: recipe for target 'bin' failed make[1]: *** [bin] Error 1 make[1]: Leaving directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx' Makefile:133: recipe for target 'N310_RFNOC_HG' failed make: *** [N310_RFNOC_HG] Error 2 This is my Makefile.OOT.inc ## # Include OOT makefiles ## OOT_DIR = $(BASE_DIR)/../../../rfnoc-gohm/rfnoc RFNOC_OOT_SRCS += $(addprefix /home/rcetin/rfnoc/rfnoc-gohm/rfnoc/fpga-src/, \ noc_block_gain.v \ ) \ I can build OOT modules for E310 but cannot for N310. Can you please help to solve this problem? Best regards. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] OFDM Transceiver on E310
Actually, i tried it. But i guess minimum sample rate is 1Ms/s, when i set less than it, it gives this warning on transmitter side; [WARNING] [MULTI_USRP] The hardware does not support the requested TX sample rate: Target sample rate: 0.50 MSps Actual sample rate: 1.00 MSps When i set 500Ks/s, transmitter again gives 'U's but receiver does not. I guess receiver can be set to lower sample rates, but transmitter not. Do you know any way to work transmitter on lower rates? On 4.04.2019 15:57, Malik Saad wrote: Just use sampling rate lesser than the existing mode. On Thursday, April 4, 2019, Ramazan Çetin via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: Hello all, I am trying to implement OFDM transceiver on E310. Lastly, i already implemented OFDM on N310 (in network mode connected to computer) using GNURadio blocks. But when i run same example (*ofdm_rx_tx_hier_blocks.grc)* on E310 it gives 'U' and 'O's. Processor cannot handle incoming and outgoing data. Then, i put OFDM transmit block to one E310 and OFDM receive to anther to decrease load on processor. Again, transmitter gives 'U' and receiver gives 'O's. Receiver also gives that info: INFO: Detected an invalid packet at item INFO: Parser returned #f So, it cannot decode OFDM header. I guess packets are corrupted because of bad transmission. I know that, processor cannot handle that much data. I should go to FPGA and RFNoC. But in here, available OFDM implementation in RFNoC using GNURadio is not fit into FPGA (i can put 3 RFNoC blocks). So should i implement my own OFDM implementation on FPGA? Or, can you please suggest another way to implement OFDM Transceiver on E310? Best regards. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] OFDM Transceiver on E310
Hello all,
I am trying to implement OFDM transceiver on E310. Lastly, i already
implemented OFDM on N310 (in network mode connected to computer) using
GNURadio blocks. But when i run same example
(*ofdm_rx_tx_hier_blocks.grc)* on E310 it gives 'U' and 'O's. Processor
cannot handle incoming and outgoing data.
Then, i put OFDM transmit block to one E310 and OFDM receive to anther
to decrease load on processor. Again, transmitter gives 'U' and receiver
gives 'O's. Receiver also gives that info:
INFO: Detected an invalid packet at item
INFO: Parser returned #f
So, it cannot decode OFDM header. I guess packets are corrupted because
of bad transmission.
I know that, processor cannot handle that much data. I should go to FPGA
and RFNoC. But in here, available OFDM implementation in RFNoC using
GNURadio is not fit into FPGA (i can put 3 RFNoC blocks).
So should i implement my own OFDM implementation on FPGA?
Or, can you please suggest another way to implement OFDM Transceiver on
E310?
Best regards.
Thu Jan 17 14:32:20 2019
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Re: [USRP-users] N310 Device Claim Issue
Hi again, I could resolve this issue by restarting hwdaemon; systemctl restart usrp-hwd.service This solves problem. After that i need to load the FPGA image again. Best regards. On 4.03.2019 13:18, Ramazan Çetin wrote: Hi all, I am using N310 for my gnuradio OFDM application. Sometimes, my gnuradio application closes abruptly (because of segfault, some errors etc.). After that, when i try restarting application it gives that error; [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501; UHD_3.14.0.HEAD-0-gc7941e05 [INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.10.2,type=n3xx,product=n310,serial=3175D89,claimed=True,addr=192.168.10.2,force_reinit=1 [ERROR] [RPC] Someone tried to claim this device again Traceback (most recent call last): File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 296, in main() File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 285, in main tb = top_block_cls() File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 58, in __init__ channels=range(1), File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py", line 122, in constructor_interceptor return old_constructor(*args) File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 2782, in make return _uhd_swig.usrp_source_make(*args) RuntimeError: RuntimeError: Error during RPC call to `claim'. Error message: Someone tried to claim this device again I cannot restart application until i reboot the device. Is there a solution for this issue? Do i have to reboot device each time if my application closes badly? Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] N310 Device Claim Issue
Hi all, I am using N310 for my gnuradio OFDM application. Sometimes, my gnuradio application closes abruptly (because of segfault, some errors etc.). After that, when i try restarting application it gives that error; [INFO] [UHD] linux; GNU C++ version 7.3.0; Boost_106501; UHD_3.14.0.HEAD-0-gc7941e05 [INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.10.2,type=n3xx,product=n310,serial=3175D89,claimed=True,addr=192.168.10.2,force_reinit=1 [ERROR] [RPC] Someone tried to claim this device again Traceback (most recent call last): File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 296, in main() File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 285, in main tb = top_block_cls() File "/home/rcetin/workspace/gohm/bitbucket/physicallayergnuradio/ofdm_rx_tx_hier_blocks.py", line 58, in __init__ channels=range(1), File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/__init__.py", line 122, in constructor_interceptor return old_constructor(*args) File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 2782, in make return _uhd_swig.usrp_source_make(*args) RuntimeError: RuntimeError: Error during RPC call to `claim'. Error message: Someone tried to claim this device again I cannot restart application until i reboot the device. Is there a solution for this issue? Do i have to reboot device each time if my application closes badly? Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] OFDM on E310 using RFNoC
Hello,
I am trying to implement OFDM on E310 using RFNoC. My software versions:
UHD: v3.14.0.0-rc1
gnuradio: 3.7.13.4
gr-ettus: master branch
FPGA: e57dfe0
I followed the FG in below that shown in GRCon15.
https://static1.squarespace.com/static/543ae9afe4b0c3b808d72acd/t/55f85aaee4b02e1b84d8ff51/1442339502956/7-pendlum_johathan-OFDM_RFNoC-2015-08-27.pdf
But FPGA of E310 is small so i just can place 3 RFNoC blocks in it. I
thought using some blocks from RFNoC and others from GNURadio.
Q1. Can you suggest a way to implement OFDM in E310? (Because i could
not find a OFDM implementation that includes both RFNoC and gnuradio
blocks. There is a example in gr-ettus which is rfnoc_ofdm, but its OFDM
receiver is also done with full of RFNoC blocks.)
Q2. For example, i can compile FPGA image using eq, schmidl_cox and
constellation_demap blocks. ( FFT dont fit) So i thought using FFT from
gnuradio. I created a FG which includes;
RFNoC: Radio --> RFNoC: OFDM Sync --> FFT --> RFNoC: OFDM Eq --> RFNoC:
OFDM constellation demap --> File Sink
When i run this it gives that error;
root@ettus-e3xx-sg3:~# ./rfnoc_ofdm_test.py
[INFO] [UHD] linux; GNU C++ version 4.9.2; Boost_105700;
UHD_3.14.0.HEAD-0-gc7941e05
[INFO] [E300] Loading FPGA image:
/home/root/usrp_e310_eq_sch_const_RFNOC_sg3.bit...
[INFO] [E300] FPGA image loaded
[INFO] [E300] Initializing core control (global registers)...
[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1000)
[WARNING] [RFNOC] Can't find a block controller for key OFDMEq, using
default block controller!
[INFO] [0/OFDMEq_0] Initializing block control (NOC ID: 0xFF42)
[WARNING] [RFNOC] Can't find a block controller for key OFDMDemap, using
default block controller!
[INFO] [0/OFDMDemap_0] Initializing block control (NOC ID:
0x0FCD)
[WARNING] [RFNOC] Can't find a block controller for key SchmidlCox,
using default block controller!
[INFO] [0/SchmidlCox_0] Initializing block control (NOC ID:
0x5CC0)
Traceback (most recent call last):
File "./rfnoc_ofdm_test.py", line 184, in
main()
File "./rfnoc_ofdm_test.py", line 173, in main
tb = top_block_cls()
File "./rfnoc_ofdm_test.py", line 129, in __init__
self.connect((self.uhd_rfnoc_ofdm_demap_0, 0),
(self.blocks_file_sink_0, 0))
File
"/home/root/localinstall/usr/lib/python2.7/site-packages/gnuradio/gr/hier_block2.py",
line 47, in wrapped
func(self, src, src_port, dst, dst_port)
File
"/home/root/localinstall/usr/lib/python2.7/site-packages/gnuradio/gr/hier_block2.py",
line 110, in connect
self.primitive_connect(*args)
File
"/home/root/localinstall/usr/lib/python2.7/site-packages/gnuradio/gr/runtime_swig.py",
line 3482, in primitive_connect
return _runtime_swig.top_block_sptr_primitive_connect(self, *args)
ValueError: itemsize mismatch: uhd_rfnoc_OFDMDemap0:0 using 8,
file_sink0:0 using 64
[INFO] [E300] Loading FPGA image:
/home/root/localinstall/usr/share/uhd/images/usrp_e3xx_fpga_idle_sg3.bit...
[INFO] [E300] FPGA image loaded
What is the problem in there?
Best regards.
Ramazan
Fri Nov 7 10:40:33 2014
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Re: [USRP-users] E310 RFNoC FFT Overrun Issue
Hi Jonathon, Thanks you for your suggestions. I have achieved getting 60 MHz spectrum samples to file on ARM processor using; RFNoC: Radio -> RFNoC: FFT -> RFNoC: Vector IIR -> RFNoC: Keep 1 in N -> File Sink It just getting overflows after 4-5 seconds such as "*overrun on chan 0*". Is this because of *RFNoC* side or *processor* side ? Also, Keep 1 in B block works as using packets not samples this is also perfect for me. I will not lose FFT bins. But i can not much understand Vector IIR part. Why is it used and good for FFT outputs? Is it for averaging results ? Thank you for your time. Best regards. Ramazan On 11.02.2019 08:09, Jonathon Pendlum wrote: Hi Ramazan, I would suggest first testing with a signal generated with GNU Radio. For example, use a Fast Noise Source + Low Pass Filter to crudely simulate receiving a wide band signal. See what it looks like without running it through RFNoC. Then replace the RFNoC radio block with those blocks and look at the result. You should also consider using the ZeroMQ blocks to forward data over Ethernet to a host PC to view your data in real time. Look at the gr-ettus example flowgraphs rfnoc_fft_network_usrp (runs on E310) and rfnoc_fft_network_host (runs on host PC). One guess I can make is try increasing the FFT RFNoC block gain. By default, it is set to a very conservative value, so try changing it to 21. That gain value sets the Xilinx's FFT IP core scaling schedule, which you can read about here: https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_0/pg109-xfft.pdf (see SCALE_SCH on page 15, the core uses Radix-4). You can also try adjusting it with a slider in real time. Note that it may behave a bit odd as it is not a linear mapping due to the scaling schedule format. The overflows are due to either the ARM processors cannot keep up with the processing load or the SD card write speed is too slow. Try increasing N in Keep One in N. Jonathon ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] E310 RFNoC FFT Overrun Issue
Hi Jonathon,
Thank you for your reply. I just tried what you said and investigated
gr-ettus/examples/rfnoc/rfnoc_vector_iir.grc. I firstly tried without
using keep 1 in N block. I just sampled 2MHz and try to get FM radio
samples of spectrum. My flowgraph is attached.
My problem is when i used RFNOC: radio -> RFNOC: FFT -> VecToStr ->
IIR_filter(not RFNOC) -> StrToVect -> CompToMag -> Log10 -> FileSink
with same coefficients it is working good. I can get spectrum samples.
But when i use RFNOC: radio -> RFNOC: FFT -> RFNOC: Vector_iir ->
CompToMag -> Log10 -> FileSink
it gives all zeros after its output. Coefficients are same. I just
changed IIR filter with RFNOC Vector IIR. Do you know why it is happening?
Best regards.
On 10.02.2019 10:21, Jonathon Pendlum wrote:
Hi Ramazan,
Q1. So, do you know any method to minimize signal distortion while
downsampling in frequency domain? or How can i get wifi signal
frequency
spectrum in E310 ?
You want to filter the vector of FFT bins individually, which is not
what the DDC block is designed to do. Instead, you should use the
VectorIIR and Keep 1 in N RFNoC blocks in this configuration: RFNoC
Radio -> RFNoC FFT -> RFNoC VectorIIR -> RFNoC Keep 1 in N -> Host.
For an example, look at the gr-ettus flowgraph in
gr-ettus/examples/rfnoc/rfnoc_vector_iir.grc.
Q2. When i try compiling FPGA image with 4 blocks, it gives "Placer
could not place all instances" error. But in guide, it says user
can put
up to 6 blocks. Why it give that error after 3 blocks?
The FPGA fabric has a finite amount of resources (LUTs, Registers,
BRAMs, DSP48s) and your configuration required more resources than
available. The 6 block limit is more of a rule of thumb, especially
when using small blocks like the RFNoC FIFO blocks. You can certainly
use up all the FPGA resources with less than 6 RFNoC blocks. In your
case, a build with just the FFT, VectorIIR, and Keep One in N RFNoC
blocks should fit.
Jonathon
Fri Nov 7 10:40:33 2014
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Re: [USRP-users] E310 RFNoC FFT Overrun Issue
Hi Marcus, I have compiled proper image(fft, ddc, keep 1 to n) and did what you said. Now, it looks better, i am getting very little overruns sometimes. I have another question. I am sorry if question is not related with this topic. I changed my flowgraph to this: RFNOC_radio --(56MHz)> RFNOC_FFT -> RFNOC_DDC --(2MHz)> complexToMag -> Log10 -> FileSink I want to get wifi samples from E310 which has 56 MHz analog BW. So, i can get wifi samples from FPGA but not in CPU. I want to see wifi samples on frequency spectrum on CPU. So, i thought that i can get 56 MHz signal on FPGA and get FFT. After FFT, downsample FFT results and push FFT samples to CPU as 1-5Ms/s. But when i looked my signal on CPU, its so distorted. Q1. So, do you know any method to minimize signal distortion while downsampling in frequency domain? or How can i get wifi signal frequency spectrum in E310 ? Q2. When i try compiling FPGA image with 4 blocks, it gives "Placer could not place all instances" error. But in guide, it says user can put up to 6 blocks. Why it give that error after 3 blocks? Best regards. On 9.02.2019 17:11, Marcus D. Leech wrote: On 02/09/2019 07:05 AM, Ramazan Çetin via USRP-users wrote: Hello all, I want to get fft of 50Ms/s signal and after fft using DDC i will pass the samples with 1-5Ms/s to ARM processor. I have compiled an FPGA image with FFT, DDC and FIFO. | | _ | | / | | | RFNoC blocks on this device: | | | | | | * Radio_0 | | | * DDC_0 | | | * FFT_0 | | | * FIFO_0 I have a gnuradio flowgraph (It is attached); Radio -> strToVector -> FIFO -> FFT -> vectorToStr -> CompToMag -> NullSink When i used master clock rate 1M, there is no overruns. After 1M for example (1.5M) i am getting overruns. [INFO] [E300] Performing register loopback test... [INFO] [E300] Register loopback test passed [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1000) [INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0) [WARNING] [RFNOC] Can't find a block controller for key FFT, using default block controller! [INFO] [0/FFT_0] Initializing block control (NOC ID: 0xFF70) [INFO] [0/FIFO_0] Initializing block control (NOC ID: 0xF1F0) [WARNING] [RFNOC] Assuming max packet size for 0/FIFO_0 Press Enter to quit: overrun on chan 0O overrun on chan 0 Ooverrun on chan 0 Ooverrun on chan 0 Ooverrun on chan 0 Ooverrun on chan 0 Ooverrun on chan O0 overrun on chan 0 So, why is this happening? I thought i am handling data in FPGA so i can get FFT of 50Ms/s signal. I just need to reduce sampling rate when i pass the samples to ARM processor. What is wrong with my setup? Thank you. Best regards. Ramazan Notice how there aren't strToVector blocks in the list of RFNOC blocks, nor complex-to-mag. That means the samples are visiting the CPU at high rate. The flow would be: Radio-->FFT--->IIR_FILTER-->KEEP_1_IN_N--->then do the complex-to-mag on the host. However, you're missing RFNoC blocks for the IIR filter and KEEP_1_IN_N ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] E310 RFNoC FFT Overrun Issue
Hello all,
I want to get fft of 50Ms/s signal and after fft using DDC i will pass
the samples with 1-5Ms/s to ARM processor.
I have compiled an FPGA image with FFT, DDC and FIFO.
| | _
| | /
| | | RFNoC blocks on this device:
| | |
| | | * Radio_0
| | | * DDC_0
| | | * FFT_0
| | | * FIFO_0
I have a gnuradio flowgraph (It is attached);
Radio -> strToVector -> FIFO -> FFT -> vectorToStr -> CompToMag -> NullSink
When i used master clock rate 1M, there is no overruns. After 1M for
example (1.5M) i am getting overruns.
[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD1000)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0)
[WARNING] [RFNOC] Can't find a block controller for key FFT, using
default block controller!
[INFO] [0/FFT_0] Initializing block control (NOC ID: 0xFF70)
[INFO] [0/FIFO_0] Initializing block control (NOC ID: 0xF1F0)
[WARNING] [RFNOC] Assuming max packet size for 0/FIFO_0
Press Enter to quit: overrun on chan 0O
overrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan O0
overrun on chan 0
So, why is this happening? I thought i am handling data in FPGA so i can
get FFT of 50Ms/s signal. I just need to reduce sampling rate when i
pass the samples to ARM processor. What is wrong with my setup?
Thank you. Best regards.
Ramazan
Fri Nov 7 10:40:33 2014
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Re: [USRP-users] Custom RFNOC fpga image build failed
ata/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
I installed Xilinx Vivado using root privileges. Can the
problem related with privileges ? I think Webpack version is
okay for E310 (No licence reuires).
Thank you for your time.
Best regards.
On 3.02.2019 06:22, Jonathon Pendlum wrote:
Hi Ramazan,
I was able to build an E310 RFNoC image with a DDC and FFT
block from master (e57dfe075) on the FPGA repo, so I don't
think there is an issue with the code base. The error
messages make me wonder if your Vivado install is corrupt.
Are you able to build any other images, such as the default
X310 image (i.e. run 'source setupenv.sh; make X310_HG' in
the fpga/usrp3/top/x300 dir)?
Jonathon
On Sun, Feb 3, 2019 at 6:53 AM Ramazan Çetin via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hello all, (Sorry about multiple messages. I guess i had
a problem about
my mail client)
I am trying to build custom FPGA image for E310 which
includes DDC and FFT.
I compiled and installed;
- UHD master branch (using -DENABLE_RFNOC=ON)
- gnuradio v3.7.13.4
- gr-ettus master
After installing i have checked version of UHD.
UHD version: 3.14.0.0-0-gabf0db4e
Then according to instructions in this page :
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
I cloned https://github.com/EttusResearch/fpga.git repo.
I have Xilinx
Vivado 2017.4 webpack.
Then, I setup environment from
fpga/usrp3/top/e300/setupenv.sh.
cd {USER_PREFIX}/fpga/usrp3/tools/scripts
./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3
-m 5
--fill-with-fifos
--Using the following blocks to generate image:
* ddc
* fft
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
Setting up a 64-bit FPGA build environment for the
USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1
EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory
'/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4 (64-bit)
BUILDER: Building IP axi_dma_stream
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
-log
axi_dma_stream.log -nojournal
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
This IP will not be included in the IP Catalog.
[00:00:13] Current task: Initialization +++ Current
Phase: Starting
[00:00:13] Current task: Initialization +++ Current
Phase: Finished
[00:00:13] Executing Tcl: synth_design -top
axi_dma_stream -part
xc7z020clg484-3 -mode out_of_context
[00:00:13] Starting Synthesis Command
[00:00:13] Current task: Synthesis +++ Current Phase:
Re: [USRP-users] Custom RFNOC fpga image build failed
.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file
'/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_ooc.xdc'
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
This IP will not be included in the IP Catalog.
[00:00:11] Current task: Initialization +++ Current Phase: Starting
[00:00:11] Current task: Initialization +++ Current Phase: Finished
[00:00:11] Executing Tcl: synth_design -top
axi4_to_axi3_protocol_converter -part xc7z020clg484-3 -mode
out_of_context
[00:00:11] Starting Synthesis Command
ERROR: [filemgmt 56-148]
@57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
ERROR: [Common 17-53] User Exception: No open design. Please open
an elaborated, synthesized or implemented design before executing
this command.
[00:00:12] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Vivado 12-398] No designs are open
[00:00:12] Current task: Synthesis +++ Current Phase: Finished
[00:00:12] Process terminated. Status: Failure
Warnings: 1
Critical Warnings: 4
Errors: 8
BUILDER: Releasing IP location:
/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter
/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/ip/axi4_to_axi3_protocol_converter/Makefile.inc:15:
recipe for target
'/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci'
failed
make[1]: ***
[/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci]
Error 1
make[1]: Leaving directory
'/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
Makefile:60: recipe for target 'E310_sg3' failed
make: *** [E310_sg3] Error 2
The error says it cannot read ip file.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
I installed Xilinx Vivado using root privileges. Can the problem
related with privileges ? I think Webpack version is okay for E310
(No licence reuires).
Thank you for your time.
Best regards.
On 3.02.2019 06:22, Jonathon Pendlum wrote:
Hi Ramazan,
I was able to build an E310 RFNoC image with a DDC and FFT block
from master (e57dfe075) on the FPGA repo, so I don't think there
is an issue with the code base. The error messages make me wonder
if your Vivado install is corrupt. Are you able to build any
other images, such as the default X310 image (i.e. run 'source
setupenv.sh; make X310_HG' in the fpga/usrp3/top/x300 dir)?
Jonathon
On Sun, Feb 3, 2019 at 6:53 AM Ramazan Çetin via USRP-users
mailto:usrp-users@lists.ettus.com>>
wrote:
Hello all, (Sorry about multiple messages. I guess i had a
problem about
my mail client)
I am trying to build custom FPGA image for E310 which
includes DDC and FFT.
I compiled and installed;
- UHD master branch (using -DENABLE_RFNOC=ON)
- gnuradio v3.7.13.4
- gr-ettus master
After installing i have checked version of UHD.
UHD version: 3.14.0.0-0-gabf0db4e
Then according to instructions in this page :
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
I cloned https://github.com/EttusResearch/fpga.git repo. I
have Xilinx
Vivado 2017.4 webpack.
Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
cd {USER_
Re: [USRP-users] Custom RFNOC fpga image build failed
[Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
[00:00:12] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Vivado 12-398] No designs are open
[00:00:12] Current task: Synthesis +++ Current Phase: Finished
[00:00:12] Process terminated. Status: Failure
Warnings: 1
Critical Warnings: 4
Errors: 8
BUILDER: Releasing IP location:
/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter
/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/ip/axi4_to_axi3_protocol_converter/Makefile.inc:15:
recipe for target
'/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci'
failed
make[1]: ***
[/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci]
Error 1
make[1]: Leaving directory
'/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
Makefile:60: recipe for target 'E310_sg3' failed
make: *** [E310_sg3] Error 2
The error says it cannot read ip file.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
I installed Xilinx Vivado using root privileges. Can the problem related
with privileges ? I think Webpack version is okay for E310 (No licence
reuires).
Thank you for your time.
Best regards.
On 3.02.2019 06:22, Jonathon Pendlum wrote:
Hi Ramazan,
I was able to build an E310 RFNoC image with a DDC and FFT block from
master (e57dfe075) on the FPGA repo, so I don't think there is an
issue with the code base. The error messages make me wonder if your
Vivado install is corrupt. Are you able to build any other images,
such as the default X310 image (i.e. run 'source setupenv.sh; make
X310_HG' in the fpga/usrp3/top/x300 dir)?
Jonathon
On Sun, Feb 3, 2019 at 6:53 AM Ramazan Çetin via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hello all, (Sorry about multiple messages. I guess i had a problem
about
my mail client)
I am trying to build custom FPGA image for E310 which includes DDC
and FFT.
I compiled and installed;
- UHD master branch (using -DENABLE_RFNOC=ON)
- gnuradio v3.7.13.4
- gr-ettus master
After installing i have checked version of UHD.
UHD version: 3.14.0.0-0-gabf0db4e
Then according to instructions in this page :
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
I cloned https://github.com/EttusResearch/fpga.git repo. I have
Xilinx
Vivado 2017.4 webpack.
Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
cd {USER_PREFIX}/fpga/usrp3/tools/scripts
./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3 -m 5
--fill-with-fifos
--Using the following blocks to generate image:
* ddc
* fft
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1
EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory
'/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4 (64-bit)
BUILDER: Building IP axi_dma_stream
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip
[USRP-users] Custom RFNOC fpga image build failed
Hello all, (Sorry about multiple messages. I guess i had a problem about
my mail client)
I am trying to build custom FPGA image for E310 which includes DDC and FFT.
I compiled and installed;
- UHD master branch (using -DENABLE_RFNOC=ON)
- gnuradio v3.7.13.4
- gr-ettus master
After installing i have checked version of UHD.
UHD version: 3.14.0.0-0-gabf0db4e
Then according to instructions in this page :
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
I cloned https://github.com/EttusResearch/fpga.git repo. I have Xilinx
Vivado 2017.4 webpack.
Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
cd {USER_PREFIX}/fpga/usrp3/tools/scripts
./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3 -m 5
--fill-with-fifos
--Using the following blocks to generate image:
* ddc
* fft
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1
EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4 (64-bit)
BUILDER: Building IP axi_dma_stream
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
axi_dma_stream.log -nojournal
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
/opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
This IP will not be included in the IP Catalog.
[00:00:13] Current task: Initialization +++ Current Phase: Starting
[00:00:13] Current task: Initialization +++ Current Phase: Finished
[00:00:13] Executing Tcl: synth_design -top axi_dma_stream -part
xc7z020clg484-3 -mode out_of_context
[00:00:13] Starting Synthesis Command
[00:00:13] Current task: Synthesis +++ Current Phase: Starting
ERROR: [filemgmt 56-148]
@57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
[00:00:14] Current task: Synthesis +++ Current Phase: Finished
[00:00:14] Process terminated. Status: Failure
Warnings: 0
Critical Warnings: 4
Errors: 8
BUILDER: Releasing IP location:
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/ip/axi_dma_stream/Makefile.inc:15:
recipe for target
'/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci'
failed
make[1]: ***
[/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci]
Error 1
make[1]: Leaving directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
make: *** [E310_RFNOC_sg3] Error 2
Can you
[USRP-users] Custom RFNOC fpga image build failed
Hello all,
I am trying to build custom FPGA image for E310 which includes DDC and FFT.
I compiled and installed;
- UHD master branch (using -DENABLE_RFNOC=ON)
- gnuradio v3.7.13.4
- gr-ettus master
After installing i have checked version of UHD.
UHD version: 3.14.0.0-0-gabf0db4e
Then according to instructions in this page : https://kb.ettus.com/Getting_Started_with_RFNoC_Development
I cloned https://github.com/EttusResearch/fpga.git repo. I have Xilinx Vivado 2017.4 webpack.
Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
cd {USER_PREFIX}/fpga/usrp3/tools/scripts
./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3 -m 5 --fill-with-fifos
--Using the following blocks to generate image:
* ddc
* fft
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2017.4 (64-bit)
BUILDER: Building IP axi_dma_stream
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_dma_stream.log -nojournal
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml. This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml. This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml. This IP will not be included in the IP Catalog.
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml. This IP will not be included in the IP Catalog.
[00:00:13] Current task: Initialization +++ Current Phase: Starting
[00:00:13] Current task: Initialization +++ Current Phase: Finished
[00:00:13] Executing Tcl: synth_design -top axi_dma_stream -part xc7z020clg484-3 -mode out_of_context
[00:00:13] Starting Synthesis Command
[00:00:13] Current task: Synthesis +++ Current Phase: Starting
ERROR: [filemgmt 56-148] @57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
[00:00:14] Current task: Synthesis +++ Current Phase: Finished
[00:00:14] Process terminated. Status: Failure
Warnings: 0
Critical Warnings: 4
Errors: 8
BUILDER: Releasing IP location: /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/ip/axi_dma_stream/Makefile.inc:15: recipe for target '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci' failed
make[1]: *** [/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci] Error 1
make[1]: Leaving directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
make: *** [E310_RFNOC_sg3] Error 2
Can you please point me what i did wrong ?
Best Regards.
___
USRP-users mailing
[USRP-users] USRP file Transmission Packet Loss
Hello all, I am trying to transmit a file using GMSK and USRP B210. I have created a flowgraph in gnuradio-companion. File Source -> Packet encoder -> GMSK Mod -> Multiply Const (1) -> USRP Sink USRP Source -> GMSK Demod -> Packet Decoder -> File Sink At the end, transmitter does not send whole file. It stops transmitting after a little time. In the receiver file, top of the file is received. When i use throttle instead of USRP, whole file is sent and demodulated. Any ideas what is the problem? BR. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] E310 receive architecture
Hello all, I am trying to understand what is going on while receiving RF data in USRP E310. I am using gnuradio in programming of USRP E310. I investigated AD9361 chip and the baseband data rate of AD9361 is maximum of 61.44MHz. So this is equal to master clock rate as i understood. For example, if i set the sample rate of USRP source block in gnuradio to 10MHz, What will happen? Q1. My Approach 1. There are several filters and decimators in AD9361. So, in AD9361 the ADC samples at rate of for example at 100MHz and using decimators in AD9361, the baseband data rate of 10MHz is obtained. Is this what happened ? (In this case FPGA blocks (DDC, DDU and radio) are not used) or, My Approach 2. The baseband rate of AD9361 is set to for example 40MHz using decimators and filters and data is passed to FPGA. In FPGA, using the DDC the rate of data is reduced to 10MHz. Is this what happened? Q2. Actually, i am confused in FPGA part of receiver. Normally, without using the RFNoC do the DDC and DDU blocks in FPGA are used to obtain desirable sample rate? or When i use the RFNoC programming in gnuradio, i can activate them. Relating to RFNoC and FPGA radio, DDC, DDU blocks, can you review my approaches? My questions are related to each other. FPGA and RFNoC part is big question mark in my mind. If you give some information about FPGA part with or without RFNoC, after answering my questions, i will appreciate. Best regards. Ramazan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
