Re: [linux-yocto] [PATCH 0/1] xilinx-zynqmp: remove CONFIG_VIRTIO=y from xilinx-zynqmp.cfg

[qwang2]

Hi Bruce,

On 2019/11/5 下午5:07, quanyang.w...@windriver.com wrote:

From: Quanyang Wang 

Hi Bruce & Michal,

This patch delete kernel option CONFIG_VIRTIO. This is because that 
CONFIG_VIRTIO
can be set to "Y" or "m". If set it to be "Y" explicitly, there will be build 
warning:

WARNING: linux-yocto-5.2.x+gitAUTOINC+343a633207_b039f25b0a-r0 
do_kernel_configcheck: [kernel config]: specified values did not make it into 
the kernel's final configuration:
-- CONFIG_VIRTIO -
Config: CONFIG_VIRTIO
Requested value: CONFIG_VIRTIO=y
Actual value: CONFIG_VIRTIO=m


Would you please help merge this patch to yocto-kernel-cache's branch yocto-5.2 
and master?

Thanks,
Quanyang



Thanks,
Quanyang

Quanyang Wang (1):
   xilinx-zynqmp: remove CONFIG_VIRTIO=y from xilinx-zynqmp.cfg

  bsp/xilinx-zynqmp/xilinx-zynqmp.cfg | 1 -
  1 file changed, 1 deletion(-)


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Re: [linux-yocto] [PATCH 1/1] xilinx-zyqn: Move disable_nonboot_cpus() in front of local_irq_disable()

[qwang2]

Hi Michal,

On 2019/10/21 下午6:45, Michal Simek wrote:

On 21. 10. 19 10:45, Quanyang Wang wrote:

Hi Michal,

On 10/21/19 4:16 PM, Michal Simek wrote:

On 21. 10. 19 7:50, quanyang.w...@windriver.com wrote:

From: Quanyang Wang 

When run kdump with enabling CONFIG_DEBUG_PREEMPT, there is a calltrace
as below:

BUG: using smp_processor_id() in preemptible [] code: sh/303
caller is machine_crash_shutdown+0x2c/0xe8
CPU: 0 PID: 303 Comm: sh Kdump: loaded Not tainted
5.2.20-yocto-standard #1
Hardware name: Xilinx Zynq Platform
[<80112ff4>] (unwind_backtrace) from [<8010ca4c>] (show_stack+0x18/0x1c)
[<8010ca4c>] (show_stack) from [<809b000c>] (dump_stack+0x70/0x8c)
[<809b000c>] (dump_stack) from [<80549a14>]
(debug_smp_processor_id+0xd4/0x118)
[<80549a14>] (debug_smp_processor_id) from [<80111428>]
(machine_crash_shutdown+0x2c/0xe8)
[<80111428>] (machine_crash_shutdown) from [<801afe24>]
(__crash_kexec+0x70/0xd0)
[<801afe24>] (__crash_kexec) from [<801259b4>] (panic+0x110/0x324)
[<801259b4>] (panic) from [<805f7018>] (sysrq_handle_crash+0x18/0x1c)
[<805f7018>] (sysrq_handle_crash) from [<805f7584>]
(__handle_sysrq+0x9c/0x14c)
[<805f7584>] (__handle_sysrq) from [<805f79e8>]
(write_sysrq_trigger+0x5c/0x6c)
[<805f79e8>] (write_sysrq_trigger) from [<8031e850>]
(proc_reg_write+0x78/0x8c)
[<8031e850>] (proc_reg_write) from [<802b1b28>] (vfs_write+0xc0/0x154)
[<802b1b28>] (vfs_write) from [<802b2a64>] (ksys_write+0x6c/0xd4)
[<802b2a64>] (ksys_write) from [<80101000>] (ret_fast_syscall+0x0/0x54)
Exception stack(0xba157fa8 to 0xba157ff0)
7fa0: 0002 005ab930 0001 005ab930 0002 
7fc0: 0002 005ab930 76fa2290 0004 76f3d124 76f3cc8c 

7fe0: 0004 7edec940 76edbfff 76e67d16

This is because that the function disable_nonboot_cpus is called in
order to make sure that the crash kernel runs in the boot CPU(cpu0).
And it will enable local irq by calling as below:

disable_nonboot_cpus
   -> freeze_secondary_cpus
    -> _cpu_down
     -> percpu_down_write
  -> rcu_sync_enter
   -> spin_unlock_irq(>rss_lock)
    -> local_irq_enable()

Then the functions including smp_processor_id() behind
disable_nonboot_cpus
will run at the irq-enabled context, and this will trigger the
calltrace.

So move disable_nonboot_cpus() in front of local_irq_disable() to avoid
it since disable_nonboot_cpus() not need run at an atomic context.

Signed-off-by: Quanyang Wang 
---
   arch/arm/kernel/machine_kexec.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/machine_kexec.c
b/arch/arm/kernel/machine_kexec.c
index 654f2b1f9ac0..83d2025a4ab1 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -145,9 +145,10 @@ static void machine_kexec_mask_interrupts(void)
     void machine_crash_shutdown(struct pt_regs *regs)
   {
-    local_irq_disable();
   disable_nonboot_cpus();
   +    local_irq_disable();
+
   crash_smp_send_stop();
     crash_save_cpu(regs, smp_processor_id());


ok. Can you please check before this if your usecases work without
disable_nonboot_cpus(). This patch was done pretty long time ago where
there was an issue with kexec. Long time ago I was talking to arm-soc
maintainers about this and they told me that mainline code should work
fine without any need to call disable_nonboot_cpus().
It means if kexec is working fine we can revert origin patch and use
what mainline is using.

It seems that the issue is still there. When crash at cpu1 and crash
kernel runs at cpu1,

it will hang, the log is as below:

root@xilinx-zynq:~# sh 1.sh
syscall kexec_file_load not available.
sysrq: Trigger a crash
Kernel panic - not syncing: sysrq triggered crash
CPU: 1 PID: 308 Comm: sh Kdump: loaded Not tainted 5.2.20-yocto-standard #4
Hardware name: Xilinx Zynq Platform
[<80112eb0>] (unwind_backtrace) from [<8010cc04>] (show_stack+0x18/0x1c)
[<8010cc04>] (show_stack) from [<8094f8f4>] (dump_stack+0x70/0x8c)
[<8094f8f4>] (dump_stack) from [<801256f4>] (panic+0xf8/0x320)
[<801256f4>] (panic) from [<805dbeb0>] (sysrq_handle_crash+0x18/0x1c)
[<805dbeb0>] (sysrq_handle_crash) from [<805dc3b8>]
(__handle_sysrq+0x9c/0x148)
[<805dc3b8>] (__handle_sysrq) from [<805dc804>]
(write_sysrq_trigger+0x5c/0x6c)
[<805dc804>] (write_sysrq_trigger) from [<8031b040>]
(proc_reg_write+0x78/0x8c)
[<8031b040>] (proc_reg_write) from [<802aeec4>] (vfs_write+0xc0/0x154)
[<802aeec4>] (vfs_write) from [<802afd18>] (ksys_write+0x64/0xc8)
[<802afd18>] (ksys_write) from [<80101000>] (ret_fast_syscall+0x0/0x54)
Exception stack(0xb905bfa8 to 0xb905bff0)
bfa0:   0002 0059afa0 0001 0059afa0 0002

bfc0: 0002 0059afa0 76f8e290 0004 76f29124 76f28c8c 

bfe0: 0004 7eb858c0 76ec7fff 76e53d16
CPU 0 will stop doing anything useful since another CPU has crashed
Loading crashdump kernel...
Bye!
Booting Linux on physical CPU 0x1
Linux version 5.2.20-yocto-standard (oe-user@oe-host) (gcc version 

Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/2] arm: dts: zynq: update coresight device node

[qwang2]

On 10/10/19 2:55 PM, Michal Simek wrote:

On 10. 10. 19 4:43, qwang2 wrote:

On 10/9/19 9:39 PM, Michal Simek wrote:

Hi,

On 09. 10. 19 4:38, quanyang.w...@windriver.com wrote:

From: Quanyang Wang 

Using new compatible value for funnel and replicator device nodes,
and use correct unit-address.

Signed-off-by: Quanyang Wang 
---
   arch/arm/boot/dts/zynq-7000.dtsi | 14 +++---
   1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index 5602f4f3ad1c..9b8f46d25d38 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -447,8 +447,8 @@
   };
   };
   -    funnel@0,f8804000 {
-    compatible = "arm,coresight-funnel", "arm,primecell";
+    funnel@f8804000 {
+    compatible = "arm,coresight-static-funnel",
"arm,primecell";
   reg = <0xf8804000 0x1000>;
   clocks = < 27>, < 46>, < 47>;
   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
@@ -503,7 +503,7 @@
   };
     replicator {
-    compatible = "arm,coresight-replicator";
+    compatible = "arm,coresight-static-replicator";
   clocks = < 27>, < 46>, < 47>;
   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
   @@ -536,8 +536,8 @@
   };
   };
   -    itm@0,f8805000 {
-    compatible = "arm,coresight-etm3x", "arm,primecell";
+    /* ITM is not supported by kernel, only leave device node
here */
+    itm@f8805000 {
   reg = <0xf8805000 0x1000>;
   clocks = < 27>, < 46>, < 47>;
   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
@@ -549,7 +549,7 @@
   };
   };
   -    ptm@0,f889c000 {
+    ptm@f889c000 {
   compatible = "arm,coresight-etm3x", "arm,primecell";
   reg = <0xf889c000 0x1000>;
   clocks = < 27>, < 46>, < 47>;
@@ -562,7 +562,7 @@
   };
   };
   -    ptm@0,f889d000 {
+    ptm@f889d000 {
   compatible = "arm,coresight-etm3x", "arm,primecell";
   reg = <0xf889d000 0x1000>;
   clocks = < 27>, < 46>, < 47>;


I don't think this is enough. I have attached the patch against mainline
how I think it should look like.

Hi Michal,

Will ITM still use "arm,coresight-etm3x" as compatible property?

you are right. It should be removed. I would keep there just
arm,primecell which should be pretty much correct.


Hi Michal,

Then I will wait for the review result for the patch in mainline, once 
it's done,


I will sent a V2 patch to yocto according to the new patch in mainline.

Thanks,

Quanyang



M


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Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/2] arm: dts: zynq: update coresight device node

[qwang2]

On 10/9/19 9:39 PM, Michal Simek wrote:

Hi,

On 09. 10. 19 4:38, quanyang.w...@windriver.com wrote:

From: Quanyang Wang 

Using new compatible value for funnel and replicator device nodes,
and use correct unit-address.

Signed-off-by: Quanyang Wang 
---
  arch/arm/boot/dts/zynq-7000.dtsi | 14 +++---
  1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5602f4f3ad1c..9b8f46d25d38 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -447,8 +447,8 @@
};
};
  
-		funnel@0,f8804000 {

-   compatible = "arm,coresight-funnel", "arm,primecell";
+   funnel@f8804000 {
+   compatible = "arm,coresight-static-funnel", 
"arm,primecell";
reg = <0xf8804000 0x1000>;
clocks = < 27>, < 46>, < 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
@@ -503,7 +503,7 @@
};
  
  		replicator {

-   compatible = "arm,coresight-replicator";
+   compatible = "arm,coresight-static-replicator";
clocks = < 27>, < 46>, < 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
  
@@ -536,8 +536,8 @@

};
};
  
-		itm@0,f8805000 {

-   compatible = "arm,coresight-etm3x", "arm,primecell";
+   /* ITM is not supported by kernel, only leave device node here 
*/
+   itm@f8805000 {
reg = <0xf8805000 0x1000>;
clocks = < 27>, < 46>, < 47>;
clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
@@ -549,7 +549,7 @@
};
};
  
-		ptm@0,f889c000 {

+   ptm@f889c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889c000 0x1000>;
clocks = < 27>, < 46>, < 47>;
@@ -562,7 +562,7 @@
};
};
  
-		ptm@0,f889d000 {

+   ptm@f889d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0xf889d000 0x1000>;
clocks = < 27>, < 46>, < 47>;



I don't think this is enough. I have attached the patch against mainline
how I think it should look like.


Hi Michal,

Will ITM still use "arm,coresight-etm3x" as compatible property?

Thanks,

Quanyang



M


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Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/3] arm: dts: zynq: enablement of coresight topology

[qwang2]

On 9/26/19 9:29 PM, Michal Simek wrote:

On 26. 09. 19 15:17, qwang2 wrote:

On 9/26/19 8:50 PM, Michal Simek wrote:

On 26. 09. 19 14:44, qwang2 wrote:

On 9/26/19 8:13 PM, Michal Simek wrote:

On 26. 09. 19 14:05, qwang2 wrote:

On 9/26/19 7:11 PM, Michal Simek wrote:

On 23. 09. 19 11:47, quanyang.w...@windriver.com wrote:

From: Zumeng Chen 

This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of
zynq-7000.

Signed-off-by: Zumeng Chen 
Signed-off-by: Quanyang Wang 
---
     arch/arm/boot/dts/zynq-7000.dtsi | 155
+++
     1 file changed, 155 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index 07bd31d2ed4a..5602f4f3ad1c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -419,5 +419,160 @@
     reg = <0xf8005000 0x1000>;
     timeout-sec = <10>;
     };
+
+    etb@f8801000 {
+    compatible = "arm,coresight-etb10", "arm,primecell";
+    reg = <0xf8801000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    etb_in_port: endpoint {
+    remote-endpoint = <_out_port1>;
+    };
+    };
+    };
+
+    tpiu@f8803000 {
+    compatible = "arm,coresight-tpiu", "arm,primecell";
+    reg = <0xf8803000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    tpiu_in_port: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port0>;
+    };
+    };
+    };
+
+    funnel@0,f8804000 {
+    compatible = "arm,coresight-funnel", "arm,primecell";
+    reg = <0xf8804000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    /* funnel output ports */
+    out-ports {
+    port {
+    funnel_out_port: endpoint {
+    remote-endpoint =
+    <_in_port0>;
+    };
+    };
+    };
+
+    in-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* funnel input ports */
+    port@0 {
+    reg = <0>;
+    funnel0_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@1 {
+    reg = <1>;
+    funnel0_in_port1: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@2 {
+    reg = <2>;
+    funnel0_in_port2: endpoint {
+    slave-mode;
+    };
+    };
+
+    port@3 {
+    reg = <3>;
+    funnel0_in_port3: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+    /*The other input ports are not connect to
anything */
+    };
+    };
+
+    replicator {
+    compatible = "arm,coresight-replicator";
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    out-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* replicator output ports */
+    port@0 {
+    reg = <0>;
+    replicator_out_port0: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    port@1 {
+    reg = <1>;
+    replicator_out_port1: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    };
+    in-ports {
+    /* replicator input port */
+    port {
+    replicator_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+

Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/3] arm: dts: zynq: enablement of coresight topology

[qwang2]

On 9/26/19 8:50 PM, Michal Simek wrote:

On 26. 09. 19 14:44, qwang2 wrote:

On 9/26/19 8:13 PM, Michal Simek wrote:

On 26. 09. 19 14:05, qwang2 wrote:

On 9/26/19 7:11 PM, Michal Simek wrote:

On 23. 09. 19 11:47, quanyang.w...@windriver.com wrote:

From: Zumeng Chen 

This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.

Signed-off-by: Zumeng Chen 
Signed-off-by: Quanyang Wang 
---
    arch/arm/boot/dts/zynq-7000.dtsi | 155
+++
    1 file changed, 155 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index 07bd31d2ed4a..5602f4f3ad1c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -419,5 +419,160 @@
    reg = <0xf8005000 0x1000>;
    timeout-sec = <10>;
    };
+
+    etb@f8801000 {
+    compatible = "arm,coresight-etb10", "arm,primecell";
+    reg = <0xf8801000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    etb_in_port: endpoint {
+    remote-endpoint = <_out_port1>;
+    };
+    };
+    };
+
+    tpiu@f8803000 {
+    compatible = "arm,coresight-tpiu", "arm,primecell";
+    reg = <0xf8803000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    tpiu_in_port: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port0>;
+    };
+    };
+    };
+
+    funnel@0,f8804000 {
+    compatible = "arm,coresight-funnel", "arm,primecell";
+    reg = <0xf8804000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    /* funnel output ports */
+    out-ports {
+    port {
+    funnel_out_port: endpoint {
+    remote-endpoint =
+    <_in_port0>;
+    };
+    };
+    };
+
+    in-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* funnel input ports */
+    port@0 {
+    reg = <0>;
+    funnel0_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@1 {
+    reg = <1>;
+    funnel0_in_port1: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@2 {
+    reg = <2>;
+    funnel0_in_port2: endpoint {
+    slave-mode;
+    };
+    };
+
+    port@3 {
+    reg = <3>;
+    funnel0_in_port3: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+    /*The other input ports are not connect to
anything */
+    };
+    };
+
+    replicator {
+    compatible = "arm,coresight-replicator";
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    out-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* replicator output ports */
+    port@0 {
+    reg = <0>;
+    replicator_out_port0: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    port@1 {
+    reg = <1>;
+    replicator_out_port1: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    };
+    in-ports {
+    /* replicator input port */
+    port {
+    replicator_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+    };
+    };
+
+    itm@0,f8805000 {
+    compatible = "arm,coresi

Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/3] arm: dts: zynq: enablement of coresight topology

[qwang2]

On 9/26/19 8:13 PM, Michal Simek wrote:

On 26. 09. 19 14:05, qwang2 wrote:

On 9/26/19 7:11 PM, Michal Simek wrote:

On 23. 09. 19 11:47, quanyang.w...@windriver.com wrote:

From: Zumeng Chen 

This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.

Signed-off-by: Zumeng Chen 
Signed-off-by: Quanyang Wang 
---
   arch/arm/boot/dts/zynq-7000.dtsi | 155 +++
   1 file changed, 155 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
b/arch/arm/boot/dts/zynq-7000.dtsi
index 07bd31d2ed4a..5602f4f3ad1c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -419,5 +419,160 @@
   reg = <0xf8005000 0x1000>;
   timeout-sec = <10>;
   };
+
+    etb@f8801000 {
+    compatible = "arm,coresight-etb10", "arm,primecell";
+    reg = <0xf8801000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    etb_in_port: endpoint {
+    remote-endpoint = <_out_port1>;
+    };
+    };
+    };
+
+    tpiu@f8803000 {
+    compatible = "arm,coresight-tpiu", "arm,primecell";
+    reg = <0xf8803000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    port {
+    tpiu_in_port: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port0>;
+    };
+    };
+    };
+
+    funnel@0,f8804000 {
+    compatible = "arm,coresight-funnel", "arm,primecell";
+    reg = <0xf8804000 0x1000>;
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    /* funnel output ports */
+    out-ports {
+    port {
+    funnel_out_port: endpoint {
+    remote-endpoint =
+    <_in_port0>;
+    };
+    };
+    };
+
+    in-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* funnel input ports */
+    port@0 {
+    reg = <0>;
+    funnel0_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@1 {
+    reg = <1>;
+    funnel0_in_port1: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+
+    port@2 {
+    reg = <2>;
+    funnel0_in_port2: endpoint {
+    slave-mode;
+    };
+    };
+
+    port@3 {
+    reg = <3>;
+    funnel0_in_port3: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+    /*The other input ports are not connect to anything */
+    };
+    };
+
+    replicator {
+    compatible = "arm,coresight-replicator";
+    clocks = < 27>, < 46>, < 47>;
+    clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+    out-ports {
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    /* replicator output ports */
+    port@0 {
+    reg = <0>;
+    replicator_out_port0: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    port@1 {
+    reg = <1>;
+    replicator_out_port1: endpoint {
+    remote-endpoint = <_in_port>;
+    };
+    };
+    };
+    in-ports {
+    /* replicator input port */
+    port {
+    replicator_in_port0: endpoint {
+    slave-mode;
+    remote-endpoint = <_out_port>;
+    };
+    };
+    };
+    };
+
+    itm@0,f8805000 {
+    compatible = "arm,coresight-etm3x", "arm,primecell";
+    reg = <0xf8805000 0

Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 2/3] arm: dts: zynq: enablement of coresight topology

[qwang2]

On 9/26/19 7:11 PM, Michal Simek wrote:

On 23. 09. 19 11:47, quanyang.w...@windriver.com wrote:

From: Zumeng Chen 

This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.

Signed-off-by: Zumeng Chen 
Signed-off-by: Quanyang Wang 
---
  arch/arm/boot/dts/zynq-7000.dtsi | 155 +++
  1 file changed, 155 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 07bd31d2ed4a..5602f4f3ad1c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -419,5 +419,160 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+   etb@f8801000 {
+   compatible = "arm,coresight-etb10", "arm,primecell";
+   reg = <0xf8801000 0x1000>;
+   clocks = < 27>, < 46>, < 47>;
+   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+   port {
+   etb_in_port: endpoint {
+   remote-endpoint = 
<_out_port1>;
+   };
+   };
+   };
+
+   tpiu@f8803000 {
+   compatible = "arm,coresight-tpiu", "arm,primecell";
+   reg = <0xf8803000 0x1000>;
+   clocks = < 27>, < 46>, < 47>;
+   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+   port {
+   tpiu_in_port: endpoint {
+   slave-mode;
+   remote-endpoint = 
<_out_port0>;
+   };
+   };
+   };
+
+   funnel@0,f8804000 {
+   compatible = "arm,coresight-funnel", "arm,primecell";
+   reg = <0xf8804000 0x1000>;
+   clocks = < 27>, < 46>, < 47>;
+   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+   /* funnel output ports */
+   out-ports {
+   port {
+   funnel_out_port: endpoint {
+   remote-endpoint =
+   <_in_port0>;
+   };
+   };
+   };
+
+   in-ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   /* funnel input ports */
+   port@0 {
+   reg = <0>;
+   funnel0_in_port0: endpoint {
+   slave-mode;
+   remote-endpoint = 
<_out_port>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   funnel0_in_port1: endpoint {
+   slave-mode;
+   remote-endpoint = 
<_out_port>;
+   };
+   };
+
+   port@2 {
+   reg = <2>;
+   funnel0_in_port2: endpoint {
+   slave-mode;
+   };
+   };
+
+   port@3 {
+   reg = <3>;
+   funnel0_in_port3: endpoint {
+   slave-mode;
+   remote-endpoint = 
<_out_port>;
+   };
+   };
+   /*The other input ports are not connect to 
anything */
+   };
+   };
+
+   replicator {
+   compatible = "arm,coresight-replicator";
+   clocks = < 27>, < 46>, < 47>;
+   clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+   out-ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   /* replicator output ports */
+   port@0 {
+   reg = <0>;
+   replicator_out_port0: endpoint {
+  

Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 0/3] patches for zynq7000

[qwang2]

On 9/25/19 3:35 PM, Michal Simek wrote:

On 25. 09. 19 8:18, qwang2 wrote:

On 9/25/19 1:34 PM, Michal Simek wrote:

On 25. 09. 19 0:16, Bruce Ashfield wrote:

In message: [linux-yocto][kernel v5.2/standard/xlnx-soc][PATCH 0/3]
patches for zynq7000
on 23/09/2019 quanyang.w...@windriver.com wrote:


From: Quanyang Wang 

Hi Bruce,

Would you please help merge these patches to linux-yocto
v5.2/standard/xlnx-soc branch?

These are now merged.

Are these changes already done upstream, or applicable to upstream ?
I just
want to make sure we aren't only fixes these in the yocto kernel when
there
are other places that we can fix as well.

We don't have this in mainline or xilinx kernel simply because none has
asked for it.
I am completely missing any manual/description how this should be tested
but I expect this is based on mainline binding.

Hi Bruce & Michal,

1.  The patch "ARM: dts: zc702: Fix I2C bus warnings"  fix some dtb
building warnings. And

this warnings will not happen in SDK (v4.19) and upstream. Because dtc
in SDK not check this

and in upstream the zynq-zc702 dts file is in correct format. This patch
is needed only because I

apply SDK patch to v5.2 kernel.

I just need to take a look but not a problem with it at all.


2. The patch "mmc: sdhci-of-arasan: Fix the incorrect soft reset
operation when runtime resuming"

is also because that SDK patch use old function API and v5.2.16 use a
new one.

ditto - it should be ok.


3. The patch "arm: dts: zynq: enablement of coresight topology" is for
coresight. It is not mature now

and I only simply verify it by using ptm2human, but will need more test
on this patch.

Do you have any description somewhere how to use it? Or can you please
put together any manual how to use it?


Hi Michal,

I just follow the document "Documentation/trace/coresight.txt" to test 
the coresight.


On target:

root@xilinx-zynq:/sys/bus/coresight/devices# echo 1 > 
f8801000.etb/enable_sink
root@xilinx-zynq:/sys/bus/coresight/devices# echo 1 > 
f889c000.ptm/enable_source

root@xilinx-zynq:/sys/bus/coresight/devices# sleep 2
root@xilinx-zynq:/sys/bus/coresight/devices# echo 0 > 
f889c000.ptm/enable_source
root@xilinx-zynq:/sys/bus/coresight/devices# dd if=/dev/f8801000.etb 
of=/root/1.bin

8+0 records in
8+0 records out
4096 bytes (4.1 kB, 4.0 KiB) copied, 0.00170529 s, 2.4 MB/s

On PC:

./ptm2human -p -i 1.bin > 1.txt

In 1.txt, I get some lines as below:

instruction addr at 0x0018, ARM state, exception (IRQ), secure state,
instruction addr at 0x80102160, ARM state,
instruction addr at 0x805ae280, ARM state,
instruction addr at 0x80177ac8, ARM state,
instruction addr at 0x80177ad8, ARM state,
instruction addr at 0x801893a8, ARM state,
instruction addr at 0x801881d8, ARM state,
instruction addr at 0x801893e8, ARM state,

I checked the System.map and the addresses like 0x80102160, 0x805ae280 
are for


__irq_svc and gic_handle_irq.  So these instructions which are captured 
should be in a irq call routine.


But ptm2human can't parse detailedly the tracing packets.

So I can't say that the coresight function works well with this patch. 
More test methods are needed to verify it.


In ./Documentation/trace/coresight.txt, it says that DS-5 and Trace32 
can also parse the


tracing packets and will get more detailed data as below:

Info    Tracing enabled
Instruction 106378866   0x8026B53C  E52DE004 false   
PUSH {lr}
Instruction 0   0x8026B540  E24DD00C    false SUB  
sp,sp,#0xc

Instruction 0   0x8026B544  E3A03000    false MOV  r3,#0
Instruction 0   0x8026B548  E58D3004    false STR  
r3,[sp,#4]
Instruction 0   0x8026B54C  E59D3004    false LDR  
r3,[sp,#4]

Instruction 0   0x8026B550  E3530004    false CMP  r3,#4
Instruction 0   0x8026B554  E2833001    false ADD  
r3,r3,#1
Instruction 0   0x8026B558  E58D3004    false STR  
r3,[sp,#4]


But I am still striving to find out how to use DS-5 to parse the data.

Is there any plan for xilinx SDK to support coresight?

Thanks,

Quanyang



M

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Re: [linux-yocto] [kernel v5.2/standard/xlnx-soc][PATCH 0/3] patches for zynq7000

[qwang2]

On 9/25/19 1:34 PM, Michal Simek wrote:

On 25. 09. 19 0:16, Bruce Ashfield wrote:

In message: [linux-yocto][kernel v5.2/standard/xlnx-soc][PATCH 0/3] patches for 
zynq7000
on 23/09/2019 quanyang.w...@windriver.com wrote:


From: Quanyang Wang 

Hi Bruce,

Would you please help merge these patches to linux-yocto v5.2/standard/xlnx-soc 
branch?

These are now merged.

Are these changes already done upstream, or applicable to upstream ? I just
want to make sure we aren't only fixes these in the yocto kernel when there
are other places that we can fix as well.

We don't have this in mainline or xilinx kernel simply because none has
asked for it.
I am completely missing any manual/description how this should be tested
but I expect this is based on mainline binding.


Hi Bruce & Michal,

1.  The patch "ARM: dts: zc702: Fix I2C bus warnings"  fix some dtb 
building warnings. And


this warnings will not happen in SDK (v4.19) and upstream. Because dtc 
in SDK not check this


and in upstream the zynq-zc702 dts file is in correct format. This patch 
is needed only because I


apply SDK patch to v5.2 kernel.

2. The patch "mmc: sdhci-of-arasan: Fix the incorrect soft reset 
operation when runtime resuming"


is also because that SDK patch use old function API and v5.2.16 use a 
new one.


3. The patch "arm: dts: zynq: enablement of coresight topology" is for 
coresight. It is not mature now


and I only simply verify it by using ptm2human, but will need more test 
on this patch.


Thanks,

Quanyang



Thanks,
Michal

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Re: [linux-yocto] [PATCH 0000/1228] xilinx-zynqmp: add sdk patches

[qwang2]

On 7/31/19 5:13 PM, Michal Simek wrote:

On 19. 07. 19 21:12, Bruce Ashfield wrote:

On Thu, Jul 18, 2019 at 9:36 AM Bruce Ashfield  wrote:

On Thu, Jul 18, 2019 at 8:30 AM Michal Simek  wrote:

On 16. 07. 19 21:44, Bruce Ashfield wrote:

On Mon, Jul 15, 2019 at 2:19 AM Wei, Yunguo  wrote:


On 7/8/2019 9:14 PM, Bruce Ashfield wrote:

On Thu, Jul 4, 2019 at 5:59 AM  wrote:

From: Quanyang Wang 

Hi Bruce,

I am working on BSP xilinx-zynqmp.

Could you please help to merge these patches to:

linux-yocto-dev standard/xilinx-zynqmp

These patches are picked from:

https://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v4.19

We already have a 4.19 branch based on Michal's tree, which was
curated and selected for the soc support.
Did you you look at the one in linux-yocto 4.19 ? Since it is a
specifically selected set of patches and might be a better starting
point.

Before I introduce a 5.x branch, I'd want to hear his opinion on the
branch and the selections that you made, versus what he would have
done.

Hi Bruce, Michal,

Any further comments on it?


I'll try getting comments from Michal via another method, he may be on
vacation. I'd still like to hear from him.

But generally speaking, since the base is the same, I have no issues
with the branch. I'll likely call the branch the same as we have in
4.19, but otherwise, will leave things as they are.

Xilinx is going to stay at 4.19 for the whole 2019 and new patches are
coming to our master branch and then they will be propagated to rebased
branch. After the initial patchset adding new patches is easy.
It means at some point in future I will sync current master with rebase
branch and ask you for adding these patches to yocto tree too.
If there is any immediate need to add/fix something there we can do it
earlier.
Please let me know what you think. I should be back in August.

No issues on my end, that strategy works for me.

I'll create the -dev (5.2) branches and stage the patches there.
Incremental updates are fine, and we can handle them as they come.

See the standard/xlnx-soc branch in the -dev kernel for the results of
the merge.

Bruce

I have pushed the latest changed to v4.19 rebased branch.
https://github.com/Xilinx/linux-xlnx/tree/xlnx_rebase_v4.19

You should be able to take patches from it and apply them.

Will be good to CC me patches which targets zynq/zynqmp.

OK, I will CC you.


"drm: xlnx: zynqmp_dp: initialize delayed work before enable interrupts"
should be added also to Xilinx tree but
"driver: pcie: reset pcie device with MIO31 on xilinx-zcu102 platform"
should be explained better especially in connection to mdelay/udelay
used there.


I will make a detailed commit log when porting to 5.3.



Thanks,
Michal

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Re: [linux-yocto] [linux-yocto-dev standard/xlnx-soc][PATCH 0/1] correct the code position

[qwang2]

Hi Bruce,

Could this patch be merged to linux-yocto-dev now?

Thanks,

Quanyang

On 2019/7/23 上午11:11, quanyang.w...@windriver.com wrote:

From: Quanyang Wang 

Hi Bruce,

Would you please help to merge this patch to
linux-yocto-dev standard/xlnx-soc
linux-yocto v5.2/standard/xlnx-soc

Thanks,
Quanyang

Quanyang Wang (1):
   net: phy: dp83867: correct the code postion

  drivers/net/phy/dp83867.c | 38 +++---
  1 file changed, 19 insertions(+), 19 deletions(-)


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Re: [linux-yocto] [linux-yocto-dev standard/xlnx-soc][PATCH 0/2] xilinx-zynqmp: fix 2 issues in zcu102 Rev1.0 board

[qwang2]

On 7/23/19 10:32 PM, Bruce Ashfield wrote:

On Tue, Jul 23, 2019 at 9:20 AM Yunguo Wei  wrote:



在 2019/7/23 21:03, qwang2 写道:

On 7/23/19 8:41 PM, Bruce Ashfield wrote:

On Tue, Jul 23, 2019 at 1:29 AM qwang2 
wrote:

On 7/22/19 11:34 PM, Bruce Ashfield wrote:

On Mon, Jul 22, 2019 at 1:24 AM  wrote:

From: Quanyang Wang 

Hi Bruce,

Would you please help merge these 2 patches to linux-yocto-dev
standard/xlnx-soc branch?

I've merged the patches.

Also note: I'm about to move linux-yocto-dev to v5.3-rc1, so I've
created a set of v5.2 branches in the main linux-yocto repository, and
I have merged the xlnx-soc work there.

So if you can try switching to:

https://git.yoctoproject.org/cgit/cgit.cgi/linux-yocto/log/?h=v5.2/standard/xlnx-soc


The content is the same as the linux-yocto-dev branch.

I'm going to generate linux-yocto_5.2 recipes shortly, but they aren't
quite ready yet. Contact me if you have trouble building that branch
without the recipes and I  can send you the in progress ones.

Also, if you do a port to 5.3, let me know and we can re-establish the
branch in linux-yocto-dev.

Hi Bruce,

I will do a port to 5.3.  But before I finish porting, I hope we can
retain the branch standard/xlnx-soc

I have 5.3-rc1 building and booting with the base set of features now.

Is there a reason why the branch I created in linux-yocto/5.2 won't
work while you are doing the port ? I'd like to push the 5.3 kernel
changes in the next day or so, and they will clobber that branch.

Hi Bruce,

For me, I plan to begin porting to 5.3 after I fix bugs and enable the
remaining

features. So I hope to maintain this branch in linux-yocto-dev but not
only linux-yocto.

But if retaining this branch bring inconvience, you can delete it.

I will switch to linux-yocto/5.2 to do the fixing bug.

Bruce,

Another reason is we have some test always tracking on
linux-yocto-dev/standard/xlnx-soc, rather than
linux-yocto/v5.2/standard/xlnx-soc.
There might be a gap between 5.3 changes is pushed and port for v5.3 is
done. So the xlnx SDK full features can't be tested during that time.

But anyway, please go ahead with your change if that is a standard
procedure, we will tune our internal plan accordingly. And we will do

Outside of the repo being different, and the branch having a v5.2/
prefix, the content is identical between linux-yocto-dev and the
linux-yocto tree. So hopefully, outside of updating which recipe you
use to build the BSP, that's the only difference. As I mentioned, I
can provide you with the linux-yocto_5.2 recipes before I complete all
my system level testing on them, if not having the recipes is a
problem for using that branch.

I always move linux-yocto-dev forward as soon as I can, and those
jumps are rebases/non-fastforward.

That being said, I can keep the old branch in -dev around on 5.2
content, while the rest of the tree is v5.3. There just won't be the
branch prefixes to keep things straight. Since you are likely the only
developers using that -soc branch, it shouldn't be a problem.

Let me know what is easiest for you, since I do want to support your
development efforts.


Hi Bruce,

It would be best that the standard/xlnx-soc branch in linux-yocto-dev is 
kept


at 5.2 content. Then after I fix bugs and finishing porting to 5.3, I 
will send request


to re-create this branch.

Thanks,

Quanyang



Bruce


the v5.3 port ASAP.

Regards,
Yunguo


Thanks,

Quanyang


Bruce


and don't delete it.

Thanks,

Quanyang


Bruce


Limeng (1):
 driver: pcie: reset pcie device with MIO31 on xilinx-zcu102
platform

Quanyang Wang (1):
 drm: xlnx: zynqmp_dp: initialize delayed work before enable
interrupts

.../boot/dts/xilinx/zynqmp-zcu102-revA.dts|  1 +
drivers/gpu/drm/xlnx/zynqmp_dp.c  |  3 +-
drivers/pci/controller/pcie-xilinx-nwl.c  | 35
+++
3 files changed, 38 insertions(+), 1 deletion(-)

--
2.17.1






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Re: [linux-yocto] [linux-yocto-dev standard/xlnx-soc][PATCH 0/2] xilinx-zynqmp: fix 2 issues in zcu102 Rev1.0 board

[qwang2]

On 7/23/19 8:41 PM, Bruce Ashfield wrote:

On Tue, Jul 23, 2019 at 1:29 AM qwang2  wrote:


On 7/22/19 11:34 PM, Bruce Ashfield wrote:

On Mon, Jul 22, 2019 at 1:24 AM  wrote:

From: Quanyang Wang 

Hi Bruce,

Would you please help merge these 2 patches to linux-yocto-dev 
standard/xlnx-soc branch?

I've merged the patches.

Also note: I'm about to move linux-yocto-dev to v5.3-rc1, so I've
created a set of v5.2 branches in the main linux-yocto repository, and
I have merged the xlnx-soc work there.

So if you can try switching to:

https://git.yoctoproject.org/cgit/cgit.cgi/linux-yocto/log/?h=v5.2/standard/xlnx-soc

The content is the same as the linux-yocto-dev branch.

I'm going to generate linux-yocto_5.2 recipes shortly, but they aren't
quite ready yet. Contact me if you have trouble building that branch
without the recipes and I  can send you the in progress ones.

Also, if you do a port to 5.3, let me know and we can re-establish the
branch in linux-yocto-dev.

Hi Bruce,

I will do a port to 5.3.  But before I finish porting, I hope we can
retain the branch standard/xlnx-soc

I have 5.3-rc1 building and booting with the base set of features now.

Is there a reason why the branch I created in linux-yocto/5.2 won't
work while you are doing the port ? I'd like to push the 5.3 kernel
changes in the next day or so, and they will clobber that branch.


Hi Bruce,

For me, I plan to begin porting to 5.3 after I fix bugs and enable the 
remaining


features. So I hope to maintain this branch in linux-yocto-dev but not 
only linux-yocto.


But if retaining this branch bring inconvience, you can delete it.

I will switch to linux-yocto/5.2 to do the fixing bug.

Thanks,

Quanyang



Bruce


and don't delete it.

Thanks,

Quanyang


Bruce


Limeng (1):
driver: pcie: reset pcie device with MIO31 on xilinx-zcu102 platform

Quanyang Wang (1):
drm: xlnx: zynqmp_dp: initialize delayed work before enable interrupts

   .../boot/dts/xilinx/zynqmp-zcu102-revA.dts|  1 +
   drivers/gpu/drm/xlnx/zynqmp_dp.c  |  3 +-
   drivers/pci/controller/pcie-xilinx-nwl.c  | 35 +++
   3 files changed, 38 insertions(+), 1 deletion(-)

--
2.17.1





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Re: [linux-yocto] [linux-yocto-dev standard/xlnx-soc][PATCH 0/2] xilinx-zynqmp: fix 2 issues in zcu102 Rev1.0 board

[qwang2]

On 7/22/19 11:34 PM, Bruce Ashfield wrote:

On Mon, Jul 22, 2019 at 1:24 AM  wrote:

From: Quanyang Wang 

Hi Bruce,

Would you please help merge these 2 patches to linux-yocto-dev 
standard/xlnx-soc branch?

I've merged the patches.

Also note: I'm about to move linux-yocto-dev to v5.3-rc1, so I've
created a set of v5.2 branches in the main linux-yocto repository, and
I have merged the xlnx-soc work there.

So if you can try switching to:

https://git.yoctoproject.org/cgit/cgit.cgi/linux-yocto/log/?h=v5.2/standard/xlnx-soc

The content is the same as the linux-yocto-dev branch.

I'm going to generate linux-yocto_5.2 recipes shortly, but they aren't
quite ready yet. Contact me if you have trouble building that branch
without the recipes and I  can send you the in progress ones.

Also, if you do a port to 5.3, let me know and we can re-establish the
branch in linux-yocto-dev.


Hi Bruce,

I will do a port to 5.3.  But before I finish porting, I hope we can 
retain the branch standard/xlnx-soc


and don't delete it.

Thanks,

Quanyang



Bruce



Limeng (1):
   driver: pcie: reset pcie device with MIO31 on xilinx-zcu102 platform

Quanyang Wang (1):
   drm: xlnx: zynqmp_dp: initialize delayed work before enable interrupts

  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts|  1 +
  drivers/gpu/drm/xlnx/zynqmp_dp.c  |  3 +-
  drivers/pci/controller/pcie-xilinx-nwl.c  | 35 +++
  3 files changed, 38 insertions(+), 1 deletion(-)

--
2.17.1




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Re: [linux-yocto] [yocto-4.12] [standard/*/axxia/base] [PATCH] tools/perf: Include inttypes.h to avoid error in cs-etm.c

[qwang2]

On 2018年04月25日 21:38, Bruce Ashfield wrote:

On 04/25/2018 09:39 AM, Daniel Dragomir wrote:

| util/cs-etm.c:1264:40: error: expected '}' before 'PRIx64'
|    [CS_ETM_MAGIC] = "   Magic number  %"PRIx64"\n",
| ^~



Is this something my -stable merges, or other BSP work has
introduced ?

I'd like to log the commit that caused the error, so I can
avoid the mistake in the future.

Hi Bruce,

This issue is introduced by axxiaarm's BSP patches and it only exist at 
axxia/base branch.
The commit which introduced it is 362f8417b1cc ("opencsd: This is a 
Backport of the Following") at axxia/base.


Thanks,
Quanyang


Bruce


Signed-off-by: Quanyang Wang 
Signed-off-by: Daniel Dragomir 
---
  tools/perf/util/cs-etm.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index d48b9a4..d34d7d5 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -37,6 +37,7 @@
  #include "debug.h"
    #include 
+#include 
    #define KiB(x) ((x) * 1024)
  #define MiB(x) ((x) * 1024 * 1024)





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Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[qwang2]

On 2018年01月10日 23:37, Bruce Ashfield wrote:

On 2018-01-10 10:26 AM, Bruce Ashfield wrote:

On 2018-01-10 12:44 AM, qwang2 wrote:



On 2018年01月10日 11:11, Bruce Ashfield wrote:

On 2018-01-09 9:07 PM, qwang2 wrote:

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html. 



It seems that those patches hasn't been merged, would you please 
help to check it?


Send them all in a completes series.

Hi Bruce,

I made all these patches in a completes series, and they are at the 
git-tree as below.


Something isn't adding up for me.

The series you sent was 3 patches, and the one you referenced was CQM
based.

I did look at the original pull request you referenced on the list, but
when I followed up that I had found the patches (in December), that was
for a 4 patch series, not something as large as you have below.


And to be clear, that 4 patch series was for rdt changes, but
looking at my 4.12 standard/base .. they aren't staged either
(although I claim that I did stage them). I see the rdt patches
in that branch you sent, so I assume you are seeing them missing
as well.

I'm not sure what happened there, but let's reset and clarify
things.

Question 1: are there three functional blocks (aka features) that
you are looking to be merged ?


There are 2 functional blocks.

1. The 1st functional block at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html
comprises 51 patches and it fixes the current upstream CQM major issues 
and enable CQM enhancementI .


2. The 2sd functional block which is sent in this commit comprise 3 
patches and  implement the function that
enable RDT (contains CQM(Cache Qulity Monitor) and CAT(Cache Allocation 
Technology)) by passing kernel

command line option "rdt=".

Question 2: can you resend that pull request with a clear division
between the three features (or two).

I have split them into 2 pull request as below:

The 1st functional block:
===
The following changes since commit 4226b065fca4f630901d99b99d18c395ae3866fb:

  ipv4: net namespace does not inherit network configurations 
(2017-12-05 17:17:05 -0500)


are available in the git repository at:

  https://github.com/wangquanyang/linux-yocto-4.12.git CQM_branch

for you to fetch changes up to 2453602a06e94f4a26aee5ad9441bdef2a79d8d6:

  perf tests: Remove Intel CQM perf test (2017-12-19 17:56:01 +0800)


Alexei Starovoitov (1):
  perf, bpf: Add BPF support to all perf_event types

Arnaldo Carvalho de Melo (5):
  tools: Adopt __noreturn from kernel sources
  perf event-parse: Use pr_warning()
  tools: Adopt __printf from kernel sources
  perf tools: Remove warning()
  perf test: Add 'struct test *' to the test functions

Colin Ian King (2):
  x86/intel_rdt: Remove redundant ternary operator on return
  x86/intel_rdt/cqm: Make integer rmid_limbo_count static

Fenghua Yu (1):
  x86/intel_rdt: Show bitmask of shareable resource with other 
executing units


Jithu Joseph (1):
  x86/intel_rdt: Remove redundant assignment

Reinette Chatre (2):
  x86/intel_rdt: Mark rdt_root and closid_alloc as static
  x86/intel_rdt: Initialize bitmask of shareable resource if CDP 
enabled


Sebastian Andrzej Siewior (1):
  perf/x86/intel/cqm: Use cpuhp_setup_state_cpuslocked()

Tony Luck (7):
  x86/intel_rdt: Simplify info and base file lists
  x86/intel_rdt/mbm: Basic counting of MBM events (total and local)
  x86/intel_rdt: Add framework for better RDT UI diagnostics
  x86/intel_rdt: Add diagnostics when writing the schemata file
  x86/intel_rdt: Add diagnostics when writing the tasks file
  x86/intel_rdt: Add diagnostics when writing the cpus file
  x86/intel_rdt: Add diagnostics when making directories

Vikas Shivappa (29):
  x86/perf/cqm: Wipe out perf based cqm
  x86/intel_rdt/cqm: Documentation for resctrl based RDT Monitoring
  x86/intel_rdt: Introduce a common compile option for RDT
  x86/intel_rdt: Change file names to accommodate RDT monitor code
  x86/intel_rdt: Cleanup namespace to support RDT monitoring
  x86/intel_rdt: Make rdt_resources_all more readable
  x86/intel_rdt/cqm: Add RDT monitoring initialization
  x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management
  x86/intel_rdt/cqm: Add info files for RDT monitoring
  x86/intel_rdt: Prepare for RDT monitoring mkdir support
  x86/intel_rdt/cqm: Add mkdir support for RDT monitoring
  x86/intel_rdt: Change closid type from int to u32
  x86/intel_rdt/cqm: Add tasks file support
  x86/intel_rdt: Prepare to add RDT monitor cpus file support
  x86/intel_rdt/cqm: Add cpus file support
  x86/intel_rdt: Prepare for RDT monitor data support
  x86/intel_rdt/cqm: Add mon_data
  x86/intel_rdt: Separate the ctrl bits from rmdir
  x86/intel_rdt/cqm:

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[qwang2]

On 2018年01月10日 11:11, Bruce Ashfield wrote:

On 2018-01-09 9:07 PM, qwang2 wrote:

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html.


It seems that those patches hasn't been merged, would you please help 
to check it?


Send them all in a completes series.

Hi Bruce,

I made all these patches in a completes series, and they are at the 
git-tree as below.


Thanks,
Quanyang

The following changes since commit 4226b065fca4f630901d99b99d18c395ae3866fb:

  ipv4: net namespace does not inherit network configurations 
(2017-12-05 17:17:05 -0500)


are available in the git repository at:

  https://github.com/wangquanyang/linux-yocto-4.12.git standard/base

for you to fetch changes up to 1d07c0cde181b7746c6091dc276ff6a205d5ca23:

  x86/intel_rdt: Turn off most RDT features on Skylake (2018-01-10 
13:13:22 +0800)



Alexei Starovoitov (1):
  perf, bpf: Add BPF support to all perf_event types

Arnaldo Carvalho de Melo (5):
  tools: Adopt __noreturn from kernel sources
  perf event-parse: Use pr_warning()
  tools: Adopt __printf from kernel sources
  perf tools: Remove warning()
  perf test: Add 'struct test *' to the test functions

Colin Ian King (2):
  x86/intel_rdt: Remove redundant ternary operator on return
  x86/intel_rdt/cqm: Make integer rmid_limbo_count static

Fenghua Yu (1):
  x86/intel_rdt: Show bitmask of shareable resource with other 
executing units


Jithu Joseph (1):
  x86/intel_rdt: Remove redundant assignment

Reinette Chatre (2):
  x86/intel_rdt: Mark rdt_root and closid_alloc as static
  x86/intel_rdt: Initialize bitmask of shareable resource if CDP 
enabled


Sebastian Andrzej Siewior (1):
  perf/x86/intel/cqm: Use cpuhp_setup_state_cpuslocked()

Tony Luck (10):
  x86/intel_rdt: Simplify info and base file lists
  x86/intel_rdt/mbm: Basic counting of MBM events (total and local)
  x86/intel_rdt: Add framework for better RDT UI diagnostics
  x86/intel_rdt: Add diagnostics when writing the schemata file
  x86/intel_rdt: Add diagnostics when writing the tasks file
  x86/intel_rdt: Add diagnostics when writing the cpus file
  x86/intel_rdt: Add diagnostics when making directories
  x86/intel_rdt: Move special case code for Haswell to a quirk function
  x86/intel_rdt: Add command line options for resource director 
technology

  x86/intel_rdt: Turn off most RDT features on Skylake

Vikas Shivappa (29):
  x86/perf/cqm: Wipe out perf based cqm
  x86/intel_rdt/cqm: Documentation for resctrl based RDT Monitoring
  x86/intel_rdt: Introduce a common compile option for RDT
  x86/intel_rdt: Change file names to accommodate RDT monitor code
  x86/intel_rdt: Cleanup namespace to support RDT monitoring
  x86/intel_rdt: Make rdt_resources_all more readable
  x86/intel_rdt/cqm: Add RDT monitoring initialization
  x86/intel_rdt/cqm: Add RMID (Resource monitoring ID) management
  x86/intel_rdt/cqm: Add info files for RDT monitoring
  x86/intel_rdt: Prepare for RDT monitoring mkdir support
  x86/intel_rdt/cqm: Add mkdir support for RDT monitoring
  x86/intel_rdt: Change closid type from int to u32
  x86/intel_rdt/cqm: Add tasks file support
  x86/intel_rdt: Prepare to add RDT monitor cpus file support
  x86/intel_rdt/cqm: Add cpus file support
  x86/intel_rdt: Prepare for RDT monitor data support
  x86/intel_rdt/cqm: Add mon_data
  x86/intel_rdt: Separate the ctrl bits from rmdir
  x86/intel_rdt/cqm: Add rmdir support
  x86/intel_rdt/cqm: Add mount,umount support
  x86/intel_rdt: Introduce rdt_enable_key for scheduling
  x86/intel_rdt/cqm: Add sched_in support
  x86/intel_rdt/cqm: Add CPU hotplug support
  x86/intel_rdt/mbm: Add mbm counter initialization
  x86/intel_rdt/mbm: Handle counter overflow
  x86/intel_rdt/mbm: Fix MBM overflow handler during CPU hotplug
  x86/intel_rdt/cqm: Improve limbo list processing
  x86/intel_rdt/cqm: Clear the default RMID during hotcpu
  x86/intel_rdt: Modify the intel_pqr_state for better performance

Xiaochen Shen (2):
  x86/intel_rdt: Fix a silent failure when writing zero value schemata
  perf tests: Remove Intel CQM perf test

 Documentation/admin-guide/kernel-parameters.rst |1 +
 Documentation/admin-guide/kernel-parameters.txt |6 +
 Documentation/x86/intel_rdt_ui.txt |  323 --
 MAINTAINERS |2 +-
 arch/x86/Kconfig |   12 +-
 arch/x86/events/intel/Makefile |2 +-
 arch/x86/events/intel/cqm.c   
| 1766 
-

 arch/x86/include/asm/intel_rdt.h |  286 
 arch/x86/include/asm/intel_rdt_common.h |   27 --
 arch/x86/include/asm/intel_rdt_sched.h |   92 
 arch/x86/kernel/cpu

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

[qwang2]

Hi Bruce,

This commit is based on the patches at 
https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html.


It seems that those patches hasn't been merged, would you please help to 
check it?


Thanks,

Quanyang


On 2018年01月10日 02:19, Bruce Ashfield wrote:

This series doesn't apply to the current 4.12:

-
Applying: x86/intel_rdt: Move special case code for Haswell to a quirk 
function

error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172
error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply
Patch failed at 0001 x86/intel_rdt: Move special case code for Haswell 
to a quirk function

The copy of the patch that failed is found in:
/home/bruce/poky-kernel/linux-yocto-4.12.git/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---

Can you double check that the 4.12 you used to generate this series
matches what I have staged on git.yoctoproject.org.

Bruce

On 01/08/2018 10:20 PM, quanyang.w...@windriver.com wrote:

From: Tony Luck 

commit 0576113a387e0c8a5d9e24b4cd62605d1c9c0db8 upstream

No functional change, but lay the ground work for other per-model
quirks.

Signed-off-by: Tony Luck 
Signed-off-by: Thomas Gleixner 
Cc: Fenghua" 
Cc: Ravi V" 
Cc: "Peter Zijlstra" 
Cc: "Stephane Eranian" 
Cc: "Andi Kleen" 
Cc: "David Carrillo-Cisneros" 
Cc: Vikas Shivappa 
Link: 
http://lkml.kernel.org/r/f195a83751b5f8b1d8a78bd3c1914300c8fa3142.1503512900.git.tony.l...@intel.com

---
  arch/x86/kernel/cpu/intel_rdt.c | 52 
++---

  1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c 
b/arch/x86/kernel/cpu/intel_rdt.c

index dfc7c48..5af2f8f 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -172,34 +172,28 @@ static unsigned int cbm_idx(struct rdt_resource 
*r, unsigned int closid)

   * is always 20 on hsw server parts. The minimum cache bitmask length
   * allowed for HSW server is always 2 bits. Hardcode all of them.
   */
-static inline bool cache_alloc_hsw_probe(void)
+static inline void cache_alloc_hsw_probe(void)
  {
-if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-boot_cpu_data.x86 == 6 &&
-boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
-struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
-u32 l, h, max_cbm = BIT_MASK(20) - 1;
+struct rdt_resource *r  = _resources_all[RDT_RESOURCE_L3];
+u32 l, h, max_cbm = BIT_MASK(20) - 1;
  -if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
-return false;
-rdmsr(IA32_L3_CBM_BASE, l, h);
-
-/* If all the bits were set in MSR, return success */
-if (l != max_cbm)
-return false;
+if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
+return;
+rdmsr(IA32_L3_CBM_BASE, l, h);
  -r->num_closid = 4;
-r->default_ctrl = max_cbm;
-r->cache.cbm_len = 20;
-r->cache.shareable_bits = 0xc;
-r->cache.min_cbm_bits = 2;
-r->alloc_capable = true;
-r->alloc_enabled = true;
+/* If all the bits were set in MSR, return success */
+if (l != max_cbm)
+return;
  -return true;
-}
+r->num_closid = 4;
+r->default_ctrl = max_cbm;
+r->cache.cbm_len = 20;
+r->cache.shareable_bits = 0xc;
+r->cache.min_cbm_bits = 2;
+r->alloc_capable = true;
+r->alloc_enabled = true;
  -return false;
+rdt_alloc_capable = true;
  }
/*
@@ -648,7 +642,7 @@ static __init bool get_rdt_alloc_resources(void)
  {
  bool ret = false;
  -if (cache_alloc_hsw_probe())
+if (rdt_alloc_capable)
  return true;
if (!boot_cpu_has(X86_FEATURE_RDT_A))
@@ -690,8 +684,18 @@ static __init bool get_rdt_mon_resources(void)
  return 
!rdt_get_mon_l3_config(_resources_all[RDT_RESOURCE_L3]);

  }
  +static __init void rdt_quirks(void)
+{
+switch (boot_cpu_data.x86_model) {
+case INTEL_FAM6_HASWELL_X:
+cache_alloc_hsw_probe();
+break;
+}
+}
+
  static __init bool get_rdt_resources(void)
  {
+rdt_quirks();
  rdt_alloc_capable = get_rdt_alloc_resources();
  rdt_mon_capable = get_rdt_mon_resources();






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[linux-yocto] [yocto-4.12] CQM(Cache monitoring) enhancement

[qwang2]

Hi Bruce,

These patches enable CQM (Cache monitoring) enhancement. And they are 
alll picked from upstream.


Thanks,

Quanyang


The following changes since commit 4226b065fca4f630901d99b99d18c395ae3866fb:

  ipv4: net namespace does not inherit network configurations 
(2017-12-05 17:17:05 -0500)


are available in the git repository at:

  https://github.com/wangquanyang/linux-yocto-4.12.git standard/base

for you to fetch changes up to 2453602a06e94f4a26aee5ad9441bdef2a79d8d6:

  perf tests: Remove Intel CQM perf test (2017-12-19 17:56:01 +0800)



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