Hi,
since nobody is using these mailing lists anymore (these days the
preferred channels seem to be GitHub/Gitea issues, IRC/mattermost, and
the forum), I will close them next week, Dec 24th - unless someone objects.
Sébastien
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Hi,
ARTIQ-5 is released today. To update, follow the stable branch manual at
https://m-labs.hk/artiq/manual/installing.html.
Highlights of this new release (compared to 4.0):
* Performance improvements:
- Faster RTIO event submission (1.5x improvement in pulse rate test)
See:
On 9/12/19 11:05 PM, Andrew Risinger via ARTIQ wrote:
> Is there a timeline for the release of ARTIQ 5?
https://github.com/m-labs/artiq/milestone/14
The main item is Sayma v2 support.
> Also, is there any reason that the conda builds only still support
> python >=3.5.3 <3.6, when Nix supports
Hi,
I have set up a web-based forum as another place (that some may find
friendlier and easier to use) to discuss all things ARTIQ, (n)Migen,
MiSoC and HeavyX with the community.
Visit it here: https://forum.m-labs.hk/
Sébastien
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Hi,
The Grabber card is not compatible with CoaXpress.
Using CoaXpress with Kasli should be possible via its SATA connector,
but requires nontrivial development in hardware and gateware.
Sébastien
On 2/1/19 12:02 AM, Harry Parke via ARTIQ wrote:
Dear ARTIQ list members,
Does anybody
Hi,
The attached PDF covers the work since the last report sent on October 9th.
Sébastien
2018-November-December.pdf
Description: Adobe PDF document
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On 10/01/2018 10:30 PM, Hanhijärvi Kalle via ARTIQ wrote:
On Kasli, I'm using SFP0 port for the fiber.
Is the LED next to SFP0 turned on? That's the Ethernet connection status
indicator.
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Please see the attached PDF.
2018-August.pdf
Description: Adobe PDF document
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On Thursday, August 09, 2018 03:12 PM, Thomas Harty wrote:
So, the questions are: how much do we need to simplify the SAWG to make
it okay to debug and maintain at the 1GSPS data rate? and, what's the
way of doing that, which has the least impact on users?
"In anything at all, perfection is
On Thursday, August 09, 2018 03:15 AM, Thomas Harty via ARTIQ wrote:
it's a big FPGA and IIRC we're not
really pushing the resources limits yet (but maybe I'm wrong about
that?), so it's not clear that's actually a problem. I get that
multi-hour compile times are death, but at least we haven't
On Wednesday, July 11, 2018 04:59 AM, Thomas Harty via ARTIQ wrote:
My view is that we shouldn't give up the flexibility of being able to
fine-tune the DUC frequency unless there is a good reason to do so.
For example: if the complexity/compile times of the current code make
Hi,
I'm trying to determine what is the best way forward to support sample
rates better than the current 600MHz with the Sayma DAC and SAWG.
What sample rate(s) would you like to see and why?
With high sample rates, there are two ways to ease the FPGA resource burden:
* use the DAC
Hi,
any objections to supporting only the RTIO clock frequency (currently
150MHz) at the Sayma input, instead of 100MHz?
Are you using non-programmable 100MHz references?
Sébastien
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On Thursday, May 24, 2018 02:16 AM, Joe Britton wrote:
Has M-Labs tested SAWG on Sayma since the DRAM, Ethernet, gateware bug
patching in recent months?
Sure, I did it just before sending the board to Duke two weeks ago. Why?
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Please see the attached PDF.
2018-May.pdf
Description: Adobe PDF document
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Please see the attached PDF.
2018-March.pdf
Description: Adobe PDF document
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Hi,
We have released ARTIQ 3.4 to fix an intermittent core device crash (#902).
Sébastien
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Hi everyone,
We have completed the ARTIQ core development for Kasli in single-board
configurations (i.e. without DRTIO). This includes DDR3 support, and
1000BASE-X Ethernet PHY using Artix-7 GTP transceivers. The full ARTIQ
runtime works properly on the board and is ready to execute kernels
Here is the current report. Happy new year everyone!
Sébastien
2018-January.pdf
Description: Adobe PDF document
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Hi Greg,
just a quick note about the SFP/SATA cable that is necessary to connect
Ethernet on a Sayma directly. I suggest building them from a passive SFP
copper cable (e.g. http://www.fs.com/products/36649.html) cut in half,
with a male (motherboard or disk) connector soldered at the end.
Please disregard this message.
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Please see the attached PDF.
2017-November.pdf
Description: Adobe PDF document
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On Friday, October 20, 2017 12:36 AM, Slichter, Daniel H. (Fed) wrote:
Judging from the absence of replies to this email, we will not
support generators on the core device nor MultiScanManager.
My main question with this is about time efficiency -- if you were to
go to the effort to support
Hi,
Judging from the absence of replies to this email, we will not support
generators on the core device nor MultiScanManager.
Sébastien
On Tuesday, October 10, 2017 02:34 PM, Sébastien Bourdeauducq wrote:
Hi,
to implement scans on the core device
(https://github.com/m-labs/artiq/issues
Hi,
to implement scans on the core device
(https://github.com/m-labs/artiq/issues/118) in the best way possible,
we need some information about how ARTIQ is used and will be used:
* are Python generators (i.e. using "yield") something that you know
about, use, and would like to see supported
On Saturday, October 07, 2017 09:13 AM, Arpit Agrawal via ARTIQ wrote:
return Instance("IOBUFDS",
i_I=self.i, o_O=self.o, i_T=self.oe,
OE means "output enable". T means "tristate", i.e. not driving. You need
to invert that signal.
Sébastien
Please see the attached PDF.
2017-October.pdf
Description: Adobe PDF document
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Hello,
We have just released ARTIQ 2.5 and new conda packages are available.
This is a bugfix release that you can use if you do not wish to move to
ARTIQ-3 yet.
Sébastien
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Hello,
After a year since the last major release, we are pleased to announce
ARTIQ 3.0.
There were ~1300 commits since 2.0, for many different features such as
RTIO DMA that can dramatically improve the throughput of long pulse
sequences, and asynchronous RPCs to speed up the reporting
Please see the attached PDF.
2017-September.pdf
Description: Adobe PDF document
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Joe,
Why is this better than the mailing list? And why add another place to
get support?
On Sunday, August 13, 2017 05:10 PM, Joe Britton via ARTIQ wrote:
- news and topics of community-wide interest
(https://ssl.serverraum.org/lists/listinfo/artiq)
The mailing list was never intended for
Please see the attached PDF.
2017-August.pdf
Description: Adobe PDF document
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On Friday, June 30, 2017 07:54 PM, Grzegorz Kasprowicz via ARTIQ wrote:
additional 30$ does not make any difference.
OK, fine.
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On Thursday, June 29, 2017 06:16 PM, Thomas Harty via ARTIQ wrote:
The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4
on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is
an added benefit.
Kasli was meant to be a simple and low-cost board without a backplane,
On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote:
Have we settled on the 50T as the FPGA for the first version of Kasli,
and what speed grade?
I would advocate for the 50T in -2 speed grade for two main reasons:
a) I don't think we need that much FPGA resources for the 100T to be
Hi,
I would like to relay the information about this upcoming conference on
trapped ions organized at NIST Boulder. M-Labs will be participating
with an exhibit (including some Sinara boards) and the hosting of a
networking event and panel discussion at Sanitas Brewery one evening.
The panel
Hi,
ARTIQ 2.3 is available and fixes various bugs that were present in 2.2.
We encourage all users to update to 2.3. When using conda, make sure to
add the conda-forge channel before updating, as ARTIQ now depends on the
new pyqtgraph 0.10 package available there.
Sébastien
On Friday, March 17, 2017 07:34 AM, Grzegorz Kasprowicz via ARTIQ wrote:
look here
https://cloud.githubusercontent.com/assets/4325054/24015076/98f7653a-0a87-11e7-93d2-7df1831b2422.jpg
Looks nice! Thanks for all your work!
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Hi,
RTIOCollision is a bit tedious to implement with DRTIO, since the master
does not know if a given channel should do replace or collision. The
satellite would need to report this information for each of its channels
(and this also needs to be passed from the gateware scripts to the
Hi,
On Wednesday, March 08, 2017 06:11 AM, Neal Pisenti via ARTIQ wrote:
* For ARTIQ core device, we would ideally jump straight to using a
Kasli, but as that isn't likely to be done in the next few months, I was
planning to use a KC705 as the core.
The "EEM" DDS/synth Kasli extensions may
Hi,
ARTIQ 2.2 is available, and contains bugfixes (SPI and some compiler
corner cases) and a relicensing under LGPL. The new license resolves
concerns about experiments being potentially considered derived works
under the GPL. We encourage all users to update to 2.2.
Sébastien
On Monday, December 19, 2016 10:08 PM, Slichter, Daniel H. (Fed) via
ARTIQ wrote:
It seems that JQI would be a good potential location because:
Sounds good. Jonathan, Joe, Jason - what do you think about hosting such
a meeting?
* Would you present something?
Depending on the structure and
On Saturday, December 17, 2016 12:02 PM, Sébastien Bourdeauducq via
ARTIQ wrote:
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
Strictly speaking: this is needed only for the two-KC705 system. But we
might as well use the same scheme
Hi,
Before DRTIO can operate, the clock chip (HMC* on Sayma and AD9516 on
KC705) needs to be running.
This setup should be done by the comms CPU on the DRTIO master, and the
management CPU on a DRTIO satellite.
For initialization, the comms or management CPU would configure the
clock
Hi,
The idea of organizing an in-person meeting for current and prospective
ARTIQ users has been floating for a while. We'd like to get a
conversation started on this topic. Some of this email is taken from
Joe's GitHub issue #582.
* Venue? some ideas: NIST, JQI, DESY, Oxford, CERN, Warsaw
Hi,
ARTIQ 2.1 is out and is a simple bugfix release. We recommend that all
2.0 users upgrade.
Sébastien
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--- Begin Message ---
Another test
On Thursday, December 01, 2016 01:24 PM, Sébastien Bourdeauducq via
ARTIQ wrote:
Testing new Mailman options that hopefully will stop triggerring the
NIST/Microsoft email spoofing detector. Can someome from NIST reply to
this message and confirm
Testing new Mailman options that hopefully will stop triggerring the
NIST/Microsoft email spoofing detector. Can someome from NIST reply to
this message and confirm that they don't get "This sender failed our
fraud detection checks" messages anymore?
On Thursday, November 24, 2016 06:24 PM, Robert Jördens wrote:
How do you want to do the replacement?
Optimizing the sequence in advance in CPU/runtime would be
channel-dependent and mode-dependent special casing.
Doing so in gateware before it enters the DMA buffer would require
gateware there
On Thursday, November 24, 2016 04:54 AM, Srinivas, Raghavendra
(IntlAssoc) wrote:
Replacing is very channel dependent. It can only happen on certain
data and certain state of the channel. Not generally. It needs to be
fine tuned for each channel. And it needs to happen at the input side
of the
Joe,
I think some clarification is badly required about what DRTIO does and
does not.
DRTIO gives you:
1) time transfer
2) low-latency low-level control of remote RTIO channels
3) an auxiliary low-bandwidth low-priority general-purpose data channel
(which can be used for moninj, flashing
On Saturday, November 05, 2016 09:57 PM, Grzegorz Kasprowicz wrote:
We can use multiple 10Gbit links in parallel between Metlinos
That's doable, but we'd have to write the gateware for inter-lane
synchronization while keeping deterministic latency, which is a bit tricky.
Hi,
does anyone have serious plans to use more than one Sinara crate?
A crate already contains one Metlino and up to 12 Sayma cards, which
means 96 DAC and 96 ADC channels. A Metlino could also be connected to
several Kaslis (if the Kasli ends up being made).
Multi-crate configurations
On Saturday, October 29, 2016 12:00 AM, Sébastien Bourdeauducq wrote:
The last line assumes that a non-transmitting device (weakly) pulls down
MISO.
You can enable a pull-down resistor inside the FPGA.
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https
On Friday, October 28, 2016 11:55 PM, Jonathan Mizrahi wrote:
How do you recommend I do that?
Something like:
self.comb += [
mosi_dev1.eq(mosi_spi_core),
mosi_dev2.eq(mosi_spi_core),
miso_spi_core.eq(miso_dev_1 | miso_dev_2)
]
The last line assumes that a non-transmitting device
On Friday, October 28, 2016 08:49 PM, Jonathan Mizrahi wrote:
In the platform extension file, when I specify the SPI buses, there is a
clock subsignal "clk." If I want to have multiple SPI buses that share
the same clock, I'm going to need to reference the same clock subsignal
in each bus, which
Hi,
See here:
https://github.com/m-labs/artiq/blob/master/artiq/gateware/nist_qc1.py#L4
The A/B/C connectors and numbers match the silkscreen of the board.
Sébastien
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On Sunday, October 09, 2016 10:20 PM, Grzegorz Kasprowicz wrote:
I mean connection of HMC7043 RFSYNCIN pins.
And it's HMC7044, not HMC7043.
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Hi,
On Wednesday, October 05, 2016 12:17 PM, Cornelius Hempel wrote:
At this stage, we are just trying to get an understanding of the size and
functional requirements (FPGA space and features) at the verilog level - which
both Trung, our FPGA engineer, and Moglabs speak.
you can simply look
Hi,
On Wednesday, October 05, 2016 09:49 AM, Trung Nguyen wrote:
My goal is to extract the Verilog comprising that gets compiled into the
FPGA bitstream in order to establish how and if we can deploy it on
another SPARTAN 6 board (= the pipistrello FPGA) made commercially by
moglabs here in
Dear Thomas,
On Monday, October 03, 2016 11:18 PM, Thomas Harty wrote:
I guess you mean propagation delay temp. co. + long-term stability,
right?
Yes. Your document mentions a <0.1deg error at 3GHz which corresponds to
100fs, but it doesn't say over what period of time that error is
On Friday, September 30, 2016 07:18 PM, Sébastien Bourdeauducq wrote:
AD9516-1 has more coarse delay range.
Scratch this. I just noticed the HMC has another "slip" mechanism that
essentially gives it infinite range. So there is no reason to use the
AD9516-1, other than com
Hi,
Here is a plan for clocking the Sinara system. Please comment.
Crate clock distribution
The crate distributes a 100MHz clock on a RTM RF backplane. This clock
is typically externally supplied from a high quality source, but it is
desirable to include a 100MHz
Hi,
the mailing list I was referring to is the ARTIQ list
(https://ssl.serverraum.org/lists/listinfo/artiq).
You need to use a modified Rust:
https://github.com/m-labs/rust
Full compilation instructions for the upcoming ARTIQ 3.0 are here:
Hi,
On Tuesday, September 20, 2016 09:35 AM, Jonathan Mizrahi wrote:
Thanks! I assume this is the part I need to buy?
http://www.ti.com/tool/usb-to-gpio
Yes.
The ARTIQ manual doesn't say anything about removing and replacing the
J65 jumper, which the kc705 manual talks about (p. 74). Is
On Tuesday, August 02, 2016 11:55 PM, Stevens, Kelly E. M. wrote:
Double click the content in the "Command" column and edit the line
such that "Y_DATASET" is replaced with "parabola". Also, you can
remove --x, --error, and --fit options for this example.
The problem with this kind of detail
Hi,
On Tuesday, August 02, 2016 02:07 AM, Stevens, Kelly E. M. wrote:
I ran the example run() function and tried to get a plot generated
but wasn’t able to figure it out. The manual says I need to edit the
applet command line so that it retrieves the parabola dataset. How
do I do that?
For
On Tuesday, July 26, 2016 06:20 AM, j arl wrote:
Kintex UltraScale SYSMONE1 interface supports digitization of 4 power
supply voltages and up to 17 external analog signals. The resulting
data can be readout by FPGA (DRP), exposed to MMC using I2C and
readout using JTAG.
My read of the docs
On Sunday, July 24, 2016 10:04 PM, Grzegorz Kasprowicz wrote:
This can be also done using single FLASH and multi boot. Xilinx has
such option but never tested it.
I have used some of the multiboot features on Spartan-6, and it worked
fine. Never tried on other FPGAs.
Well, we already have
Hi,
On Sunday, July 24, 2016 07:33 PM, Grzegorz Kasprowicz wrote:
> When receiving a bitfile, a board (Metlino/Sayma) writes it to its
> flash memory (via a SPI master core inside the FPGA) and then reboots
> (using ICAP) to load the new bitfile.
We used this approach some
time ago in AFC/AFCK
On Sunday, July 24, 2016 11:27 AM, Sébastien Bourdeauducq wrote:
It is reasonable to use the same approach to (a) and (c) on
metlino_motherboard?
I suggest (a) and (b) on all boards. (c) involves gadgetry.
And by "all boards" I also mean Kasli, which (c) would not support.
Hi,
On Sunday, July 24, 2016 07:59 AM, j arl wrote:
The bitfiles for the sayma_motherboard FPGA will be stored in flash.
We've discussed several ways of updating the bitfiles. a) serial JTAG
b) DRTIO over microTCA Port4 c) Ethernet microTCA Port0.
Update method (a) is implemented by a directly
Hi,
ARTIQ 1.2 is out and packages are available in our main Anaconda channel.
This is a pure bugfix release and we recommend that all 1.0 and 1.1
users upgrade to 1.2. Thanks to everyone who submitted detailed bug reports.
Best,
Sébastien for the ARTIQ team
List of changes:
* pipistrello:
Hi,
On Monday, July 11, 2016 05:27 PM, Peter Jansweijer wrote:
Both sides of the the tx and rx fifos are clocked with the same
frequency so there are no under- or overflows.
Yes, I understand this.
For high speed devices the region where you would hit a jump point is
extremely small, you
ted as good enough.
Are you aiming for better precision than the 1 ns specification, and is
this why you are concerned about latency variations?
Cheers,
Peter
On 7-7-2016 10:24, Sébastien Bourdeauducq wrote:
Hi,
Yes. But how do you ensure that the phase relation between the two
domains is
On Tuesday, June 28, 2016 04:00 PM, Grzegorz Kasprowicz wrote:
For Sayma board to not waste precious GTX we will add PHY with
1000Base-X. We can also route it to SATA connector and provide dedicated
SATA-SFP cables. Most of these PHYs apart from RGMII to 1000base-X offer
1000base-T, so we can
On Tuesday, July 05, 2016 09:34 PM, Stevens, Kelly E. M. wrote:
I noticed that artiq_gui.py is not in the trunk git repository
(2.0dev). What is the new equivalent?
artiq_dashboard. See the release notes for the complete list of changes
that break compatibility with 1.x.
Sébastien
Hi,
is anyone other than Chris having this problem:
https://github.com/m-labs/artiq/issues/456
If yes: can you post your precise network setup and would you consider
shipping us hardware that would allow us to reproduce the problem?
If no, I will reduce the priority of this issue.
Sébastien
Please see the attached PDF.
2016-June.pdf
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On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:
In case of WR it already worked quite well 6 years ago but later on this
circuit was modified several times:)
All the time little things.
So since we have more important things to do I'd leave it as it is.
Since we are not going
Hi,
my question was whether one can get rid of all those 6 parts and replace
them with a Si5324 circuit (instead of #1 and supporting parts) and
internal FPGA PLL(s) (instead of #2 and supporting parts). Why did you
design it that way - what do all those additional parts bring exactly?
On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
For synchronisation over fibre we can use existing White Rabbit core.
The card requires only 2 VCXO oscillators and FPGA logic. The WR core
consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.
We probably won't use
Hi,
On Tuesday, June 07, 2016 03:34 PM, Hankin, Aaron M. (Assoc) wrote:
The main attraction of the X11-forwarding-over-ssh approach is that it
feels more responsive, which helps when working remotely from home
rather than the office.
What about running the ARTIQ GUI locally and passing the
Hi,
Have you tried VNC? X is a flawed protocol that rarely works.
Sébastien
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On Tuesday, May 24, 2016 12:47 PM, Ken Brown wrote:
I am having a problem with the socket connection. After I run pppd, I
receive a modem hangup message and the connection is terminated.
It seems to connect fine based on the rcvd and sent commands logged in
verbose.
Please post the exact
Hi,
ARTIQ 1.0rc3 is now in the main conda channel and contains a number of
bugfixes and a faster compiler. Please upgrade.
The last hardware test necessary before 1.0 is the PDQ:
https://github.com/m-labs/artiq/issues/178
Sébastien
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On Tuesday, 12 April 2016 1:55:45 AM HKT Slichter, Daniel H. (Fed) wrote:
> On the DSP/"Sayma" boards, a hard SoC could have use for reducing the time
> it takes to perform feedback calculations (e.g. shifts of output signal
> frequency based on ADC readings).
Can't this be done on the Metlino
On Saturday, 9 April 2016 6:10:36 PM HKT Grzegorz Kasprowicz wrote:
> Why do you think that CPUs have negative value? You don't have to use them
> at all.
I already explained that the MPSoC has to be dealt with and cannot be
completely ignored. If we have two SDRAM systems, maybe we can to a
On Friday, 8 April 2016 12:37:02 PM HKT Grzegorz Kasprowicz wrote:
> Modification of the backplane is quite difficult and expensive.
If we have a minimalistic backplane with just power, maybe IPMI, 4x
differential pairs between MCH and each AMCs, and clock - why is that
particularly expensive?
On Friday, 8 April 2016 11:53:25 AM HKT Grzegorz Kasprowicz wrote:
> Btw,
> ZU11 FPGA costs more or less the same as 7K325 and offers almost twice more
> logic resources. The price of ZU11 is $1,376.00 at 100pcs.
> Since we will buy such quantity for our CBM project (Fair facility in GSI),
> we
he only think I worry about is performance of the DACs.
> ZynQ US+ can run IOserdes with almost 2Gbit/s performance - one can make
> 1000base-x directly on IO pins using oversampling technique.
> Greg
>
> -Original Message-
> From: Sébastien Bourdeauducq [mailto:s...@m-labs.
Hi,
ARTIQ 1.0rc2 is out and contains fixes for most of the problems reported so
far.
There is one API change from 1.0rc1: set_dataset in broadcast mode no longer
returns a Notifier. Mutating datasets should be done with mutate_dataset
instead (https://github.com/m-labs/artiq/issues/345).
On Friday, 1 April 2016 5:25:19 PM HKT Thomas Harty wrote:
> d) Something else I'm missing?
Low-frequency jitter of the PLL?
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On Wednesday, 30 March 2016 9:37:51 PM HKT Grzegorz Kasprowicz wrote:
> Well, you don't have to write it.
> It is already available for RTOS and linux.
We are not using RTOS or Linux.
> But it's true - it occupies MIO bank and dedicated DDR port. But this is axi
> and can be easily accessible
On Tuesday, 29 March 2016 11:14:14 PM HKT Grzegorz Kasprowicz wrote:
> [GK] If you don't use ARM, you still get hardened SDRAM controller and GBE
> MACs.
Yes, that's what I was saying: you cannot get rid of them (i.e. use their pins
like other IOs). So you need to use the Zynq-specific features
On Saturday, 26 March 2016 4:06:17 PM HKT Slichter, Daniel H. (Fed) wrote:
> The cost savings from using FMC, which might amount to $50 per AMC, are not
> worth if the crosstalk will make the cards not useful for researchers.
It's not only about cost of the connector - the RF daughter cards
-- Forwarded Message --
Subject: RE: FW: initial specification of the project
Date: Friday, 25 March 2016, 12:24:02 PM HKT
From: Grzegorz Kasprowicz <gkasp...@elka.pw.edu.pl>
To: 'Robert Jördens' <r...@m-labs.hk>, 'Sébastien Bourdeauducq' <s...@m-labs.hk>
On Friday, 18 March 2016 4:27:53 PM HKT Ben Keitch wrote:
> This gives me a 404:
>
> http://ssl.serverraum.org/lists-archive/artiq/attachments/20160318/ce9d656c/
> attachment.pdf
This links works fine here. Anyway, here is the slightly updated version.
Change log:
Hi,
I've been collecting ideas about the new hardware we've been talking about for
a while. Please see the attached document and let me know what you think.
Sébastien
artiq_hardware.pdf
Description: Adobe PDF document
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On Wednesday, 16 March 2016 3:55:53 AM HKT Jonathan Mizrahi wrote:
> Ah, adding the dev channel allowed me to install it. The installation
> instructions say that the dev channel is only necessary to use the
> development version of ARTIQ, so I had not added it.
Well, there aren't any
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